2 * Copyright (c) 2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include "arch/kernel_stats.hh"
35 #include "arch/vtophys.hh"
36 #include "cpu/checker/cpu.hh"
37 #include "cpu/base.hh"
38 #include "cpu/simple_thread.hh"
39 #include "cpu/static_inst.hh"
40 #include "cpu/thread_context.hh"
43 //The CheckerCPU does alpha only
44 using namespace AlphaISA
;
51 CheckerCPU::CheckerCPU(Params
*p
)
52 : BaseCPU(p
), thread(NULL
), tc(NULL
)
62 changedPC
= willChangePC
= changedNextPC
= false;
64 exitOnError
= p
->exitOnError
;
65 warnOnlyOnLoadError
= p
->warnOnlyOnLoadError
;
70 thread
= new SimpleThread(this, /* thread_num */ 0, process
);
73 threadContexts
.push_back(tc
);
78 CheckerCPU::~CheckerCPU()
83 CheckerCPU::setSystem(System
*system
)
87 thread
= new SimpleThread(this, 0, systemPtr
, itb
, dtb
, false);
90 threadContexts
.push_back(tc
);
91 delete thread
->kernelStats
;
92 thread
->kernelStats
= NULL
;
96 CheckerCPU::setIcachePort(Port
*icache_port
)
98 icachePort
= icache_port
;
102 CheckerCPU::setDcachePort(Port
*dcache_port
)
104 dcachePort
= dcache_port
;
108 CheckerCPU::serialize(ostream
&os
)
111 BaseCPU::serialize(os);
112 SERIALIZE_SCALAR(inst);
113 nameOut(os, csprintf("%s.xc", name()));
114 thread->serialize(os);
115 cacheCompletionEvent.serialize(os);
120 CheckerCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
123 BaseCPU::unserialize(cp, section);
124 UNSERIALIZE_SCALAR(inst);
125 thread->unserialize(cp, csprintf("%s.xc", section));
131 CheckerCPU::read(Addr addr
, T
&data
, unsigned flags
)
133 // need to fill in CPU & thread IDs here
134 memReq
= new Request();
136 memReq
->setVirt(0, addr
, sizeof(T
), flags
, thread
->readPC());
138 // translate to physical address
139 dtb
->translateAtomic(memReq
, tc
, false);
141 PacketPtr pkt
= new Packet(memReq
, Packet::ReadReq
, Packet::Broadcast
);
143 pkt
->dataStatic(&data
);
145 if (!(memReq
->isUncacheable())) {
146 // Access memory to see if we have the same data
147 dcachePort
->sendFunctional(pkt
);
149 // Assume the data is correct if it's an uncached access
150 memcpy(&data
, &unverifiedResult
.integer
, sizeof(T
));
158 #ifndef DOXYGEN_SHOULD_SKIP_THIS
162 CheckerCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
166 CheckerCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
170 CheckerCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
174 CheckerCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
176 #endif //DOXYGEN_SHOULD_SKIP_THIS
180 CheckerCPU::read(Addr addr
, double &data
, unsigned flags
)
182 return read(addr
, *(uint64_t*)&data
, flags
);
187 CheckerCPU::read(Addr addr
, float &data
, unsigned flags
)
189 return read(addr
, *(uint32_t*)&data
, flags
);
194 CheckerCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
196 return read(addr
, (uint32_t&)data
, flags
);
201 CheckerCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
203 // need to fill in CPU & thread IDs here
204 memReq
= new Request();
206 memReq
->setVirt(0, addr
, sizeof(T
), flags
, thread
->readPC());
208 // translate to physical address
209 dtb
->translateAtomic(memReq
, tc
, true);
211 // Can compare the write data and result only if it's cacheable,
212 // not a store conditional, or is a store conditional that
214 // @todo: Verify that actual memory matches up with these values.
215 // Right now it only verifies that the instruction data is the
216 // same as what was in the request that got sent to memory; there
217 // is no verification that it is the same as what is in memory.
218 // This is because the LSQ would have to be snooped in the CPU to
221 !(unverifiedReq
->isUncacheable()) &&
222 (!(unverifiedReq
->isLLSC()) ||
223 ((unverifiedReq
->isLLSC()) &&
224 unverifiedReq
->getExtraData() == 1))) {
227 // This code would work if the LSQ allowed for snooping.
228 PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
229 pkt.dataStatic(&inst_data);
231 dcachePort->sendFunctional(pkt);
235 memcpy(&inst_data
, unverifiedMemData
, sizeof(T
));
237 if (data
!= inst_data
) {
238 warn("%lli: Store value does not match value in memory! "
239 "Instruction: %#x, memory: %#x",
240 curTick(), inst_data
, data
);
245 // Assume the result was the same as the one passed in. This checker
246 // doesn't check if the SC should succeed or fail, it just checks the
248 if (res
&& unverifiedReq
->scResultValid())
249 *res
= unverifiedReq
->getExtraData();
255 #ifndef DOXYGEN_SHOULD_SKIP_THIS
258 CheckerCPU::write(uint64_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
262 CheckerCPU::write(uint32_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
266 CheckerCPU::write(uint16_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
270 CheckerCPU::write(uint8_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
272 #endif //DOXYGEN_SHOULD_SKIP_THIS
276 CheckerCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
278 return write(*(uint64_t*)&data
, addr
, flags
, res
);
283 CheckerCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
285 return write(*(uint32_t*)&data
, addr
, flags
, res
);
290 CheckerCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
292 return write((uint32_t)data
, addr
, flags
, res
);
297 CheckerCPU::dbg_vtophys(Addr addr
)
299 return vtophys(tc
, addr
);
303 CheckerCPU::checkFlags(Request
*req
)
305 // Remove any dynamic flags that don't have to do with the request itself.
306 unsigned flags
= unverifiedReq
->getFlags();
307 unsigned mask
= LOCKED
| PHYSICAL
| VPTE
| ALTMODE
| UNCACHEABLE
| PREFETCH
;
308 flags
= flags
& (mask
);
309 if (flags
== req
->getFlags()) {
317 CheckerCPU::dumpAndExit()
319 warn("%lli: Checker PC:%#x, next PC:%#x",
320 curTick(), thread
->readPC(), thread
->readNextPC());
321 panic("Checker found an error!");