src/cpu/checker/cpu.cc

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Geoffrey Blake
  42  */
  43
  44 #include <list>
  45 #include <string>
  46
  47 #include "arch/kernel_stats.hh"
  48 #include "arch/vtophys.hh"
  49 #include "cpu/checker/cpu.hh"
  50 #include "cpu/base.hh"
  51 #include "cpu/simple_thread.hh"
  52 #include "cpu/static_inst.hh"
  53 #include "cpu/thread_context.hh"
  54 #include "params/CheckerCPU.hh"
  55 #include "sim/tlb.hh"
  56
  57 using namespace std;
  58 using namespace TheISA;
  59
  60 void
  61 CheckerCPU::init()
  62 {
  63 }
  64
  65 CheckerCPU::CheckerCPU(Params *p)
  66     : BaseCPU(p), thread(NULL), tc(NULL)
  67 {
  68     memReq = NULL;
  69     curStaticInst = NULL;
  70     curMacroStaticInst = NULL;
  71
  72     numInst = 0;
  73     startNumInst = 0;
  74     numLoad = 0;
  75     startNumLoad = 0;
  76     youngestSN = 0;
  77
  78     changedPC = willChangePC = changedNextPC = false;
  79
  80     exitOnError = p->exitOnError;
  81     warnOnlyOnLoadError = p->warnOnlyOnLoadError;
  82     itb = p->itb;
  83     dtb = p->dtb;
  84     systemPtr = NULL;
  85     workload = p->workload;
  86     // XXX: This is a hack to get this to work some
  87     thread = new SimpleThread(this, /* thread_num */ 0, workload[0], itb, dtb);
  88
  89     tc = thread->getTC();
  90     threadContexts.push_back(tc);
  91
  92     updateOnError = true;
  93 }
  94
  95 CheckerCPU::~CheckerCPU()
  96 {
  97 }
  98
  99 void
 100 CheckerCPU::setSystem(System *system)
 101 {
 102     systemPtr = system;
 103
 104     thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
 105
 106     tc = thread->getTC();
 107     threadContexts.push_back(tc);
 108     delete thread->kernelStats;
 109     thread->kernelStats = NULL;
 110 }
 111
 112 void
 113 CheckerCPU::setIcachePort(Port *icache_port)
 114 {
 115     icachePort = icache_port;
 116 }
 117
 118 void
 119 CheckerCPU::setDcachePort(Port *dcache_port)
 120 {
 121     dcachePort = dcache_port;
 122 }
 123
 124 void
 125 CheckerCPU::serialize(ostream &os)
 126 {
 127 }
 128
 129 void
 130 CheckerCPU::unserialize(Checkpoint *cp, const string &section)
 131 {
 132 }
 133
 134 Fault
 135 CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
 136 {
 137     Fault fault = NoFault;
 138     unsigned blockSize = dcachePort->peerBlockSize();
 139     int fullSize = size;
 140     Addr secondAddr = roundDown(addr + size - 1, blockSize);
 141     bool checked_flags = false;
 142     bool flags_match = true;
 143     Addr pAddr = 0x0;
 144
 145
 146     if (secondAddr > addr)
 147        size = secondAddr - addr;
 148
 149     // Need to account for multiple accesses like the Atomic and TimingSimple
 150     while (1) {
 151         memReq = new Request();
 152         memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
 153
 154         // translate to physical address
 155         fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
 156
 157         if (!checked_flags && fault == NoFault && unverifiedReq) {
 158             flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
 159                                      memReq->getPaddr(), memReq->getFlags());
 160             pAddr = memReq->getPaddr();
 161             checked_flags = true;
 162         }
 163
 164         // Now do the access
 165         if (fault == NoFault &&
 166             !memReq->getFlags().isSet(Request::NO_ACCESS)) {
 167             PacketPtr pkt = new Packet(memReq,
 168                               memReq->isLLSC() ?
 169                               MemCmd::LoadLockedReq : MemCmd::ReadReq,
 170                               Packet::Broadcast);
 171
 172             pkt->dataStatic(data);
 173
 174             if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
 175                 // Access memory to see if we have the same data
 176                 dcachePort->sendFunctional(pkt);
 177             } else {
 178                 // Assume the data is correct if it's an uncached access
 179                 memcpy(data, unverifiedMemData, size);
 180             }
 181
 182             delete memReq;
 183             memReq = NULL;
 184             delete pkt;
 185         }
 186
 187         if (fault != NoFault) {
 188             if (memReq->isPrefetch()) {
 189                 fault = NoFault;
 190             }
 191             delete memReq;
 192             memReq = NULL;
 193             break;
 194         }
 195
 196         if (memReq != NULL) {
 197             delete memReq;
 198         }
 199
 200         //If we don't need to access a second cache line, stop now.
 201         if (secondAddr <= addr)
 202         {
 203             break;
 204         }
 205
 206         // Setup for accessing next cache line
 207         data += size;
 208         unverifiedMemData += size;
 209         size = addr + fullSize - secondAddr;
 210         addr = secondAddr;
 211     }
 212
 213     if (!flags_match) {
 214         warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
 215              curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
 216              unverifiedReq->getFlags(), addr, pAddr, flags);
 217         handleError();
 218     }
 219
 220     return fault;
 221 }
 222
 223 Fault
 224 CheckerCPU::writeMem(uint8_t *data, unsigned size,
 225                      Addr addr, unsigned flags, uint64_t *res)
 226 {
 227     Fault fault = NoFault;
 228     bool checked_flags = false;
 229     bool flags_match = true;
 230     Addr pAddr = 0x0;
 231
 232     unsigned blockSize = dcachePort->peerBlockSize();
 233     int fullSize = size;
 234
 235     Addr secondAddr = roundDown(addr + size - 1, blockSize);
 236
 237     if (secondAddr > addr)
 238         size = secondAddr - addr;
 239
 240     // Need to account for a multiple access like Atomic and Timing CPUs
 241     while (1) {
 242         memReq = new Request();
 243         memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
 244
 245         // translate to physical address
 246         fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
 247
 248         if (!checked_flags && fault == NoFault && unverifiedReq) {
 249            flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
 250                                     memReq->getPaddr(), memReq->getFlags());
 251            pAddr = memReq->getPaddr();
 252            checked_flags = true;
 253         }
 254
 255         /*
 256          * We don't actually check memory for the store because there
 257          * is no guarantee it has left the lsq yet, and therefore we
 258          * can't verify the memory on stores without lsq snooping
 259          * enabled.  This is left as future work for the Checker: LSQ snooping
 260          * and memory validation after stores have committed.
 261          */
 262
 263         delete memReq;
 264
 265         //If we don't need to access a second cache line, stop now.
 266         if (fault != NoFault || secondAddr <= addr)
 267         {
 268             if (fault != NoFault && memReq->isPrefetch()) {
 269               fault = NoFault;
 270             }
 271             break;
 272         }
 273
 274         //Update size and access address
 275         size = addr + fullSize - secondAddr;
 276         //And access the right address.
 277         addr = secondAddr;
 278    }
 279
 280    if (!flags_match) {
 281        warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
 282             curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
 283             unverifiedReq->getFlags(), addr, pAddr, flags);
 284        handleError();
 285    }
 286
 287    // Assume the result was the same as the one passed in.  This checker
 288    // doesn't check if the SC should succeed or fail, it just checks the
 289    // value.
 290    if (unverifiedReq && res && unverifiedReq->extraDataValid())
 291        *res = unverifiedReq->getExtraData();
 292
 293    // Entire purpose here is to make sure we are getting the
 294    // same data to send to the mem system as the CPU did.
 295    // Cannot check this is actually what went to memory because
 296    // there stores can be in ld/st queue or coherent operations
 297    // overwriting values.
 298    bool extraData;
 299    if (unverifiedReq) {
 300        extraData = unverifiedReq->extraDataValid() ?
 301                         unverifiedReq->getExtraData() : 1;
 302    }
 303
 304    if (unverifiedReq && unverifiedMemData &&
 305        memcmp(data, unverifiedMemData, fullSize) && extraData) {
 306            warn("%lli: Store value does not match value sent to memory!\
 307                   data: %#x inst_data: %#x", curTick(), data,
 308                   unverifiedMemData);
 309        handleError();
 310    }
 311
 312    return fault;
 313 }
 314
 315 Addr
 316 CheckerCPU::dbg_vtophys(Addr addr)
 317 {
 318     return vtophys(tc, addr);
 319 }
 320
 321 /**
 322  * Checks if the flags set by the Checker and Checkee match.
 323  */
 324 bool
 325 CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
 326                        Addr pAddr, int flags)
 327 {
 328     Addr unverifiedVAddr = unverified_req->getVaddr();
 329     Addr unverifiedPAddr = unverified_req->getPaddr();
 330     int unverifiedFlags = unverified_req->getFlags();
 331
 332     if (unverifiedVAddr != vAddr ||
 333         unverifiedPAddr != pAddr ||
 334         unverifiedFlags != flags) {
 335         return false;
 336     }
 337
 338     return true;
 339 }
 340
 341 void
 342 CheckerCPU::dumpAndExit()
 343 {
 344     warn("%lli: Checker PC:%s",
 345          curTick(), thread->pcState());
 346     panic("Checker found an error!");
 347 }