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31 #ifndef __CPU_CHECKER_CPU_HH__
32 #define __CPU_CHECKER_CPU_HH__
38 #include "arch/types.hh"
39 #include "base/statistics.hh"
40 #include "config/full_system.hh"
41 #include "cpu/base.hh"
42 #include "cpu/base_dyn_inst.hh"
43 #include "cpu/simple_thread.hh"
44 #include "cpu/pc_event.hh"
45 #include "cpu/static_inst.hh"
46 #include "sim/eventq.hh"
48 // forward declarations
71 * CheckerCPU class. Dynamically verifies instructions as they are
72 * completed by making sure that the instruction and its results match
73 * the independent execution of the benchmark inside the checker. The
74 * checker verifies instructions in order, regardless of the order in
75 * which instructions complete. There are certain results that can
76 * not be verified, specifically the result of a store conditional or
77 * the values of uncached accesses. In these cases, and with
78 * instructions marked as "IsUnverifiable", the checker assumes that
79 * the value from the main CPU's execution is correct and simply
80 * copies that value. It provides a CheckerThreadContext (see
81 * checker/thread_context.hh) that provides hooks for updating the
82 * Checker's state through any ThreadContext accesses. This allows the
83 * checker to be able to correctly verify instructions, even with
84 * external accesses to the ThreadContext that change state.
86 class CheckerCPU : public BaseCPU
89 typedef TheISA::MachInst MachInst;
90 typedef TheISA::FloatReg FloatReg;
91 typedef TheISA::FloatRegBits FloatRegBits;
92 typedef TheISA::MiscReg MiscReg;
96 struct Params : public BaseCPU::Params
106 bool warnOnlyOnLoadError;
110 CheckerCPU(Params *p);
111 virtual ~CheckerCPU();
115 void setMemory(MemObject *mem);
119 void setSystem(System *system);
123 void setIcachePort(Port *icache_port);
127 void setDcachePort(Port *dcache_port);
131 virtual Port *getPort(const std::string &name, int idx)
133 panic("Not supported on checker!");
138 // Primary thread being run.
139 SimpleThread *thread;
147 Addr dbg_vtophys(Addr addr);
158 // current instruction
161 // Pointer to the one memory request.
164 StaticInstPtr curStaticInst;
166 // number of simulated instructions
168 Counter startNumInst;
170 std::queue<int> miscRegIdxs;
172 virtual Counter totalInstructions() const
177 // number of simulated loads
179 Counter startNumLoad;
181 virtual void serialize(std::ostream &os);
182 virtual void unserialize(Checkpoint *cp, const std::string §ion);
185 Fault read(Addr addr, T &data, unsigned flags);
188 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
190 // These functions are only used in CPU models that split
191 // effective address computation from the actual memory access.
192 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
193 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
195 void prefetch(Addr addr, unsigned flags)
197 // need to do this...
200 void writeHint(Addr addr, int size, unsigned flags)
202 // need to do this...
205 Fault copySrcTranslate(Addr src);
207 Fault copy(Addr dest);
209 // The register accessor methods provide the index of the
210 // instruction's operand (e.g., 0 or 1), not the architectural
211 // register index, to simplify the implementation of register
212 // renaming. We find the architectural register index by indexing
213 // into the instruction's own operand index table. Note that a
214 // raw pointer to the StaticInst is provided instead of a
215 // ref-counted StaticInstPtr to redice overhead. This is fine as
216 // long as these methods don't copy the pointer into any long-term
217 // storage (which is pretty hard to imagine they would have reason
220 uint64_t readIntReg(const StaticInst *si, int idx)
222 return thread->readIntReg(si->srcRegIdx(idx));
225 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
227 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
228 return thread->readFloatReg(reg_idx, width);
231 FloatReg readFloatReg(const StaticInst *si, int idx)
233 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
234 return thread->readFloatReg(reg_idx);
237 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
239 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
240 return thread->readFloatRegBits(reg_idx, width);
243 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
245 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
246 return thread->readFloatRegBits(reg_idx);
249 void setIntReg(const StaticInst *si, int idx, uint64_t val)
251 thread->setIntReg(si->destRegIdx(idx), val);
252 result.integer = val;
255 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
258 thread->setFloatReg(reg_idx, val, width);
261 result.dbl = (double)val;
269 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
271 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
272 thread->setFloatReg(reg_idx, val);
273 result.dbl = (double)val;
276 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
279 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
280 thread->setFloatRegBits(reg_idx, val, width);
281 result.integer = val;
284 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
286 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
287 thread->setFloatRegBits(reg_idx, val);
288 result.integer = val;
291 uint64_t readPC() { return thread->readPC(); }
293 uint64_t readNextPC() { return thread->readNextPC(); }
295 void setNextPC(uint64_t val) {
296 thread->setNextPC(val);
299 MiscReg readMiscReg(int misc_reg)
301 return thread->readMiscReg(misc_reg);
304 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
306 return thread->readMiscRegWithEffect(misc_reg, fault);
309 Fault setMiscReg(int misc_reg, const MiscReg &val)
311 result.integer = val;
312 miscRegIdxs.push(misc_reg);
313 return thread->setMiscReg(misc_reg, val);
316 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
318 miscRegIdxs.push(misc_reg);
319 return thread->setMiscRegWithEffect(misc_reg, val);
322 void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
323 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
325 bool translateInstReq(Request *req);
326 void translateDataWriteReq(Request *req);
327 void translateDataReadReq(Request *req);
330 Fault hwrei() { return thread->hwrei(); }
331 int readIntrFlag() { return thread->readIntrFlag(); }
332 void setIntrFlag(int val) { thread->setIntrFlag(val); }
333 bool inPalMode() { return thread->inPalMode(); }
334 void ev5_trap(Fault fault) { fault->invoke(tc); }
335 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
337 // Assume that the normal CPU's call to syscall was successful.
338 // The checker's state would have already been updated by the syscall.
339 void syscall(uint64_t callnum) { }
348 bool checkFlags(Request *req);
352 ThreadContext *tcBase() { return tc; }
353 SimpleThread *threadBase() { return thread; }
355 Result unverifiedResult;
356 Request *unverifiedReq;
357 uint8_t *unverifiedMemData;
365 bool warnOnlyOnLoadError;
367 InstSeqNum youngestSN;
371 * Templated Checker class. This Checker class is templated on the
372 * DynInstPtr of the instruction type that will be verified. Proper
373 * template instantiations of the Checker must be placed at the bottom
376 template <class DynInstPtr>
377 class Checker : public CheckerCPU
381 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
385 void takeOverFrom(BaseCPU *oldCPU);
387 void verify(DynInstPtr &inst);
389 void validateInst(DynInstPtr &inst);
390 void validateExecution(DynInstPtr &inst);
391 void validateState();
393 void copyResult(DynInstPtr &inst);
396 void handleError(DynInstPtr &inst)
400 } else if (updateOnError) {
401 updateThisCycle = true;
405 void dumpAndExit(DynInstPtr &inst);
407 bool updateThisCycle;
409 DynInstPtr unverifiedInst;
411 std::list<DynInstPtr> instList;
412 typedef typename std::list<DynInstPtr>::iterator InstListIt;
416 #endif // __CPU_CHECKER_CPU_HH__