src/cpu/checker/cpu.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  */
  43
  44 #ifndef __CPU_CHECKER_CPU_HH__
  45 #define __CPU_CHECKER_CPU_HH__
  46
  47 #include <list>
  48 #include <map>
  49 #include <queue>
  50
  51 #include "arch/types.hh"
  52 #include "base/statistics.hh"
  53 #include "cpu/base.hh"
  54 #include "cpu/base_dyn_inst.hh"
  55 #include "cpu/exec_context.hh"
  56 #include "cpu/pc_event.hh"
  57 #include "cpu/simple_thread.hh"
  58 #include "cpu/static_inst.hh"
  59 #include "debug/Checker.hh"
  60 #include "mem/request.hh"
  61 #include "params/CheckerCPU.hh"
  62 #include "sim/eventq.hh"
  63
  64 // forward declarations
  65 namespace TheISA
  66 {
  67     class TLB;
  68 }
  69
  70 template <class>
  71 class BaseDynInst;
  72 class ThreadContext;
  73 class Request;
  74
  75 /**
  76  * CheckerCPU class.  Dynamically verifies instructions as they are
  77  * completed by making sure that the instruction and its results match
  78  * the independent execution of the benchmark inside the checker.  The
  79  * checker verifies instructions in order, regardless of the order in
  80  * which instructions complete.  There are certain results that can
  81  * not be verified, specifically the result of a store conditional or
  82  * the values of uncached accesses.  In these cases, and with
  83  * instructions marked as "IsUnverifiable", the checker assumes that
  84  * the value from the main CPU's execution is correct and simply
  85  * copies that value.  It provides a CheckerThreadContext (see
  86  * checker/thread_context.hh) that provides hooks for updating the
  87  * Checker's state through any ThreadContext accesses.  This allows the
  88  * checker to be able to correctly verify instructions, even with
  89  * external accesses to the ThreadContext that change state.
  90  */
  91 class CheckerCPU : public BaseCPU, public ExecContext
  92 {
  93   protected:
  94     typedef TheISA::MachInst MachInst;
  95     typedef TheISA::FloatReg FloatReg;
  96     typedef TheISA::FloatRegBits FloatRegBits;
  97     typedef TheISA::MiscReg MiscReg;
  98
  99     /** id attached to all issued requests */
 100     MasterID masterId;
 101   public:
 102     void init() override;
 103
 104     typedef CheckerCPUParams Params;
 105     CheckerCPU(Params *p);
 106     virtual ~CheckerCPU();
 107
 108     void setSystem(System *system);
 109
 110     void setIcachePort(MasterPort *icache_port);
 111
 112     void setDcachePort(MasterPort *dcache_port);
 113
 114     MasterPort &getDataPort() override
 115     {
 116         // the checker does not have ports on its own so return the
 117         // data port of the actual CPU core
 118         assert(dcachePort);
 119         return *dcachePort;
 120     }
 121
 122     MasterPort &getInstPort() override
 123     {
 124         // the checker does not have ports on its own so return the
 125         // data port of the actual CPU core
 126         assert(icachePort);
 127         return *icachePort;
 128     }
 129
 130   protected:
 131
 132     std::vector<Process*> workload;
 133
 134     System *systemPtr;
 135
 136     MasterPort *icachePort;
 137     MasterPort *dcachePort;
 138
 139     ThreadContext *tc;
 140
 141     TheISA::TLB *itb;
 142     TheISA::TLB *dtb;
 143
 144     Addr dbg_vtophys(Addr addr);
 145
 146     union Result {
 147         uint64_t integer;
 148         double dbl;
 149         void set(uint64_t i) { integer = i; }
 150         void set(double d) { dbl = d; }
 151         void get(uint64_t& i) { i = integer; }
 152         void get(double& d) { d = dbl; }
 153     };
 154
 155     // ISAs like ARM can have multiple destination registers to check,
 156     // keep them all in a std::queue
 157     std::queue<Result> result;
 158
 159     // Pointer to the one memory request.
 160     RequestPtr memReq;
 161
 162     StaticInstPtr curStaticInst;
 163     StaticInstPtr curMacroStaticInst;
 164
 165     // number of simulated instructions
 166     Counter numInst;
 167     Counter startNumInst;
 168
 169     std::queue<int> miscRegIdxs;
 170
 171   public:
 172
 173     // Primary thread being run.
 174     SimpleThread *thread;
 175
 176     TheISA::TLB* getITBPtr() { return itb; }
 177     TheISA::TLB* getDTBPtr() { return dtb; }
 178
 179     virtual Counter totalInsts() const override
 180     {
 181         return 0;
 182     }
 183
 184     virtual Counter totalOps() const override
 185     {
 186         return 0;
 187     }
 188
 189     // number of simulated loads
 190     Counter numLoad;
 191     Counter startNumLoad;
 192
 193     void serialize(CheckpointOut &cp) const override;
 194     void unserialize(CheckpointIn &cp) override;
 195
 196     // These functions are only used in CPU models that split
 197     // effective address computation from the actual memory access.
 198     void setEA(Addr EA) override
 199     { panic("CheckerCPU::setEA() not implemented\n"); }
 200     Addr getEA() const  override
 201     { panic("CheckerCPU::getEA() not implemented\n"); }
 202
 203     // The register accessor methods provide the index of the
 204     // instruction's operand (e.g., 0 or 1), not the architectural
 205     // register index, to simplify the implementation of register
 206     // renaming.  We find the architectural register index by indexing
 207     // into the instruction's own operand index table.  Note that a
 208     // raw pointer to the StaticInst is provided instead of a
 209     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 210     // long as these methods don't copy the pointer into any long-term
 211     // storage (which is pretty hard to imagine they would have reason
 212     // to do).
 213
 214     IntReg readIntRegOperand(const StaticInst *si, int idx) override
 215     {
 216         return thread->readIntReg(si->srcRegIdx(idx));
 217     }
 218
 219     FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
 220     {
 221         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
 222         return thread->readFloatReg(reg_idx);
 223     }
 224
 225     FloatRegBits readFloatRegOperandBits(const StaticInst *si,
 226                                          int idx) override
 227     {
 228         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
 229         return thread->readFloatRegBits(reg_idx);
 230     }
 231
 232     CCReg readCCRegOperand(const StaticInst *si, int idx) override
 233     {
 234         int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
 235         return thread->readCCReg(reg_idx);
 236     }
 237
 238     template <class T>
 239     void setResult(T t)
 240     {
 241         Result instRes;
 242         instRes.set(t);
 243         result.push(instRes);
 244     }
 245
 246     void setIntRegOperand(const StaticInst *si, int idx,
 247                           IntReg val) override
 248     {
 249         thread->setIntReg(si->destRegIdx(idx), val);
 250         setResult<uint64_t>(val);
 251     }
 252
 253     void setFloatRegOperand(const StaticInst *si, int idx,
 254                             FloatReg val) override
 255     {
 256         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
 257         thread->setFloatReg(reg_idx, val);
 258         setResult<double>(val);
 259     }
 260
 261     void setFloatRegOperandBits(const StaticInst *si, int idx,
 262                                 FloatRegBits val) override
 263     {
 264         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
 265         thread->setFloatRegBits(reg_idx, val);
 266         setResult<uint64_t>(val);
 267     }
 268
 269     void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
 270     {
 271         int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
 272         thread->setCCReg(reg_idx, val);
 273         setResult<uint64_t>(val);
 274     }
 275
 276     bool readPredicate() override { return thread->readPredicate(); }
 277     void setPredicate(bool val) override
 278     {
 279         thread->setPredicate(val);
 280     }
 281
 282     TheISA::PCState pcState() const override { return thread->pcState(); }
 283     void pcState(const TheISA::PCState &val) override
 284     {
 285         DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
 286                          val, thread->pcState());
 287         thread->pcState(val);
 288     }
 289     Addr instAddr() { return thread->instAddr(); }
 290     Addr nextInstAddr() { return thread->nextInstAddr(); }
 291     MicroPC microPC() { return thread->microPC(); }
 292     //////////////////////////////////////////
 293
 294     MiscReg readMiscRegNoEffect(int misc_reg) const
 295     {
 296         return thread->readMiscRegNoEffect(misc_reg);
 297     }
 298
 299     MiscReg readMiscReg(int misc_reg) override
 300     {
 301         return thread->readMiscReg(misc_reg);
 302     }
 303
 304     void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 305     {
 306         DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg);
 307         miscRegIdxs.push(misc_reg);
 308         return thread->setMiscRegNoEffect(misc_reg, val);
 309     }
 310
 311     void setMiscReg(int misc_reg, const MiscReg &val) override
 312     {
 313         DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
 314         miscRegIdxs.push(misc_reg);
 315         return thread->setMiscReg(misc_reg, val);
 316     }
 317
 318     MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
 319     {
 320         int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
 321         return thread->readMiscReg(reg_idx);
 322     }
 323
 324     void setMiscRegOperand(const StaticInst *si, int idx,
 325                            const MiscReg &val) override
 326     {
 327         int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
 328         return this->setMiscReg(reg_idx, val);
 329     }
 330
 331 #if THE_ISA == MIPS_ISA
 332     MiscReg readRegOtherThread(int misc_reg, ThreadID tid) override
 333     {
 334         panic("MIPS MT not defined for CheckerCPU.\n");
 335         return 0;
 336     }
 337
 338     void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) override
 339     {
 340         panic("MIPS MT not defined for CheckerCPU.\n");
 341     }
 342 #endif
 343
 344     /////////////////////////////////////////
 345
 346     void recordPCChange(const TheISA::PCState &val)
 347     {
 348        changedPC = true;
 349        newPCState = val;
 350     }
 351
 352     void demapPage(Addr vaddr, uint64_t asn) override
 353     {
 354         this->itb->demapPage(vaddr, asn);
 355         this->dtb->demapPage(vaddr, asn);
 356     }
 357
 358     // monitor/mwait funtions
 359     void armMonitor(Addr address) override
 360     { BaseCPU::armMonitor(0, address); }
 361     bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
 362     void mwaitAtomic(ThreadContext *tc) override
 363     { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
 364     AddressMonitor *getAddrMonitor() override
 365     { return BaseCPU::getCpuAddrMonitor(0); }
 366
 367     void demapInstPage(Addr vaddr, uint64_t asn)
 368     {
 369         this->itb->demapPage(vaddr, asn);
 370     }
 371
 372     void demapDataPage(Addr vaddr, uint64_t asn)
 373     {
 374         this->dtb->demapPage(vaddr, asn);
 375     }
 376
 377     Fault readMem(Addr addr, uint8_t *data, unsigned size,
 378                   Request::Flags flags) override;
 379     Fault writeMem(uint8_t *data, unsigned size, Addr addr,
 380                    Request::Flags flags, uint64_t *res) override;
 381
 382     unsigned int readStCondFailures() const override {
 383         return thread->readStCondFailures();
 384     }
 385
 386     void setStCondFailures(unsigned int sc_failures) override
 387     {}
 388     /////////////////////////////////////////////////////
 389
 390     Fault hwrei() override { return thread->hwrei(); }
 391     bool simPalCheck(int palFunc) override
 392     { return thread->simPalCheck(palFunc); }
 393     void wakeup(ThreadID tid) override { }
 394     // Assume that the normal CPU's call to syscall was successful.
 395     // The checker's state would have already been updated by the syscall.
 396     void syscall(int64_t callnum) override { }
 397
 398     void handleError()
 399     {
 400         if (exitOnError)
 401             dumpAndExit();
 402     }
 403
 404     bool checkFlags(Request *unverified_req, Addr vAddr,
 405                     Addr pAddr, int flags);
 406
 407     void dumpAndExit();
 408
 409     ThreadContext *tcBase() override { return tc; }
 410     SimpleThread *threadBase() { return thread; }
 411
 412     Result unverifiedResult;
 413     Request *unverifiedReq;
 414     uint8_t *unverifiedMemData;
 415
 416     bool changedPC;
 417     bool willChangePC;
 418     TheISA::PCState newPCState;
 419     bool exitOnError;
 420     bool updateOnError;
 421     bool warnOnlyOnLoadError;
 422
 423     InstSeqNum youngestSN;
 424 };
 425
 426 /**
 427  * Templated Checker class.  This Checker class is templated on the
 428  * DynInstPtr of the instruction type that will be verified.  Proper
 429  * template instantiations of the Checker must be placed at the bottom
 430  * of checker/cpu.cc.
 431  */
 432 template <class Impl>
 433 class Checker : public CheckerCPU
 434 {
 435   private:
 436     typedef typename Impl::DynInstPtr DynInstPtr;
 437
 438   public:
 439     Checker(Params *p)
 440         : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
 441     { }
 442
 443     void switchOut();
 444     void takeOverFrom(BaseCPU *oldCPU);
 445
 446     void advancePC(const Fault &fault);
 447
 448     void verify(DynInstPtr &inst);
 449
 450     void validateInst(DynInstPtr &inst);
 451     void validateExecution(DynInstPtr &inst);
 452     void validateState();
 453
 454     void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx);
 455     void handlePendingInt();
 456
 457   private:
 458     void handleError(DynInstPtr &inst)
 459     {
 460         if (exitOnError) {
 461             dumpAndExit(inst);
 462         } else if (updateOnError) {
 463             updateThisCycle = true;
 464         }
 465     }
 466
 467     void dumpAndExit(DynInstPtr &inst);
 468
 469     bool updateThisCycle;
 470
 471     DynInstPtr unverifiedInst;
 472
 473     std::list<DynInstPtr> instList;
 474     typedef typename std::list<DynInstPtr>::iterator InstListIt;
 475     void dumpInsts();
 476 };
 477
 478 #endif // __CPU_CHECKER_CPU_HH__