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43 #ifndef __CPU_CHECKER_CPU_HH__
44 #define __CPU_CHECKER_CPU_HH__
50 #include "arch/types.hh"
51 #include "base/statistics.hh"
52 #include "cpu/base.hh"
53 #include "cpu/base_dyn_inst.hh"
54 #include "cpu/pc_event.hh"
55 #include "cpu/simple_thread.hh"
56 #include "cpu/static_inst.hh"
57 #include "debug/Checker.hh"
58 #include "params/CheckerCPU.hh"
59 #include "sim/eventq.hh"
61 // forward declarations
73 * CheckerCPU class. Dynamically verifies instructions as they are
74 * completed by making sure that the instruction and its results match
75 * the independent execution of the benchmark inside the checker. The
76 * checker verifies instructions in order, regardless of the order in
77 * which instructions complete. There are certain results that can
78 * not be verified, specifically the result of a store conditional or
79 * the values of uncached accesses. In these cases, and with
80 * instructions marked as "IsUnverifiable", the checker assumes that
81 * the value from the main CPU's execution is correct and simply
82 * copies that value. It provides a CheckerThreadContext (see
83 * checker/thread_context.hh) that provides hooks for updating the
84 * Checker's state through any ThreadContext accesses. This allows the
85 * checker to be able to correctly verify instructions, even with
86 * external accesses to the ThreadContext that change state.
88 class CheckerCPU : public BaseCPU
91 typedef TheISA::MachInst MachInst;
92 typedef TheISA::FloatReg FloatReg;
93 typedef TheISA::FloatRegBits FloatRegBits;
94 typedef TheISA::MiscReg MiscReg;
96 /** id attached to all issued requests */
101 typedef CheckerCPUParams Params;
102 CheckerCPU(Params *p);
103 virtual ~CheckerCPU();
105 void setSystem(System *system);
107 void setIcachePort(MasterPort *icache_port);
109 void setDcachePort(MasterPort *dcache_port);
111 MasterPort &getDataPort()
113 // the checker does not have ports on its own so return the
114 // data port of the actual CPU core
119 MasterPort &getInstPort()
121 // the checker does not have ports on its own so return the
122 // data port of the actual CPU core
129 std::vector<Process*> workload;
133 MasterPort *icachePort;
134 MasterPort *dcachePort;
141 Addr dbg_vtophys(Addr addr);
146 void set(uint64_t i) { integer = i; }
147 void set(double d) { dbl = d; }
148 void get(uint64_t& i) { i = integer; }
149 void get(double& d) { d = dbl; }
152 // ISAs like ARM can have multiple destination registers to check,
153 // keep them all in a std::queue
154 std::queue<Result> result;
156 // Pointer to the one memory request.
159 StaticInstPtr curStaticInst;
160 StaticInstPtr curMacroStaticInst;
162 // number of simulated instructions
164 Counter startNumInst;
166 std::queue<int> miscRegIdxs;
170 // Primary thread being run.
171 SimpleThread *thread;
173 TheISA::TLB* getITBPtr() { return itb; }
174 TheISA::TLB* getDTBPtr() { return dtb; }
176 virtual Counter totalInsts() const
181 virtual Counter totalOps() const
186 // number of simulated loads
188 Counter startNumLoad;
190 virtual void serialize(std::ostream &os);
191 virtual void unserialize(Checkpoint *cp, const std::string §ion);
193 // These functions are only used in CPU models that split
194 // effective address computation from the actual memory access.
195 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
196 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
198 // The register accessor methods provide the index of the
199 // instruction's operand (e.g., 0 or 1), not the architectural
200 // register index, to simplify the implementation of register
201 // renaming. We find the architectural register index by indexing
202 // into the instruction's own operand index table. Note that a
203 // raw pointer to the StaticInst is provided instead of a
204 // ref-counted StaticInstPtr to redice overhead. This is fine as
205 // long as these methods don't copy the pointer into any long-term
206 // storage (which is pretty hard to imagine they would have reason
209 uint64_t readIntRegOperand(const StaticInst *si, int idx)
211 return thread->readIntReg(si->srcRegIdx(idx));
214 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
216 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
217 return thread->readFloatReg(reg_idx);
220 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
222 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
223 return thread->readFloatRegBits(reg_idx);
231 result.push(instRes);
234 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
236 thread->setIntReg(si->destRegIdx(idx), val);
237 setResult<uint64_t>(val);
240 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
242 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
243 thread->setFloatReg(reg_idx, val);
244 setResult<double>(val);
247 void setFloatRegOperandBits(const StaticInst *si, int idx,
250 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
251 thread->setFloatRegBits(reg_idx, val);
252 setResult<uint64_t>(val);
255 bool readPredicate() { return thread->readPredicate(); }
256 void setPredicate(bool val)
258 thread->setPredicate(val);
261 TheISA::PCState pcState() { return thread->pcState(); }
262 void pcState(const TheISA::PCState &val)
264 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
265 val, thread->pcState());
266 thread->pcState(val);
268 Addr instAddr() { return thread->instAddr(); }
269 Addr nextInstAddr() { return thread->nextInstAddr(); }
270 MicroPC microPC() { return thread->microPC(); }
271 //////////////////////////////////////////
273 MiscReg readMiscRegNoEffect(int misc_reg)
275 return thread->readMiscRegNoEffect(misc_reg);
278 MiscReg readMiscReg(int misc_reg)
280 return thread->readMiscReg(misc_reg);
283 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
285 miscRegIdxs.push(misc_reg);
286 return thread->setMiscRegNoEffect(misc_reg, val);
289 void setMiscReg(int misc_reg, const MiscReg &val)
291 miscRegIdxs.push(misc_reg);
292 return thread->setMiscReg(misc_reg, val);
295 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
297 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
298 return thread->readMiscReg(reg_idx);
301 void setMiscRegOperand(
302 const StaticInst *si, int idx, const MiscReg &val)
304 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
305 return thread->setMiscReg(reg_idx, val);
308 #if THE_ISA == MIPS_ISA
309 uint64_t readRegOtherThread(int misc_reg)
311 panic("MIPS MT not defined for CheckerCPU.\n");
315 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
317 panic("MIPS MT not defined for CheckerCPU.\n");
321 /////////////////////////////////////////
323 void recordPCChange(const TheISA::PCState &val)
329 void demapPage(Addr vaddr, uint64_t asn)
331 this->itb->demapPage(vaddr, asn);
332 this->dtb->demapPage(vaddr, asn);
335 void demapInstPage(Addr vaddr, uint64_t asn)
337 this->itb->demapPage(vaddr, asn);
340 void demapDataPage(Addr vaddr, uint64_t asn)
342 this->dtb->demapPage(vaddr, asn);
345 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
346 Fault writeMem(uint8_t *data, unsigned size,
347 Addr addr, unsigned flags, uint64_t *res);
349 void setStCondFailures(unsigned sc_failures)
351 /////////////////////////////////////////////////////
353 Fault hwrei() { return thread->hwrei(); }
354 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
356 // Assume that the normal CPU's call to syscall was successful.
357 // The checker's state would have already been updated by the syscall.
358 void syscall(uint64_t callnum) { }
366 bool checkFlags(Request *unverified_req, Addr vAddr,
367 Addr pAddr, int flags);
371 ThreadContext *tcBase() { return tc; }
372 SimpleThread *threadBase() { return thread; }
374 Result unverifiedResult;
375 Request *unverifiedReq;
376 uint8_t *unverifiedMemData;
380 TheISA::PCState newPCState;
384 bool warnOnlyOnLoadError;
386 InstSeqNum youngestSN;
390 * Templated Checker class. This Checker class is templated on the
391 * DynInstPtr of the instruction type that will be verified. Proper
392 * template instantiations of the Checker must be placed at the bottom
395 template <class Impl>
396 class Checker : public CheckerCPU
399 typedef typename Impl::DynInstPtr DynInstPtr;
403 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
407 void takeOverFrom(BaseCPU *oldCPU);
409 void advancePC(Fault fault);
411 void verify(DynInstPtr &inst);
413 void validateInst(DynInstPtr &inst);
414 void validateExecution(DynInstPtr &inst);
415 void validateState();
417 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx);
418 void handlePendingInt();
421 void handleError(DynInstPtr &inst)
425 } else if (updateOnError) {
426 updateThisCycle = true;
430 void dumpAndExit(DynInstPtr &inst);
432 bool updateThisCycle;
434 DynInstPtr unverifiedInst;
436 std::list<DynInstPtr> instList;
437 typedef typename std::list<DynInstPtr>::iterator InstListIt;
441 #endif // __CPU_CHECKER_CPU_HH__