2 * Copyright (c) 2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #ifndef __CPU_CHECKER_CPU_HH__
32 #define __CPU_CHECKER_CPU_HH__
38 #include "arch/types.hh"
39 #include "base/statistics.hh"
40 #include "config/full_system.hh"
41 #include "cpu/base.hh"
42 #include "cpu/base_dyn_inst.hh"
43 #include "cpu/simple_thread.hh"
44 #include "cpu/pc_event.hh"
45 #include "cpu/static_inst.hh"
46 #include "sim/eventq.hh"
48 // forward declarations
72 * CheckerCPU class. Dynamically verifies instructions as they are
73 * completed by making sure that the instruction and its results match
74 * the independent execution of the benchmark inside the checker. The
75 * checker verifies instructions in order, regardless of the order in
76 * which instructions complete. There are certain results that can
77 * not be verified, specifically the result of a store conditional or
78 * the values of uncached accesses. In these cases, and with
79 * instructions marked as "IsUnverifiable", the checker assumes that
80 * the value from the main CPU's execution is correct and simply
81 * copies that value. It provides a CheckerThreadContext (see
82 * checker/thread_context.hh) that provides hooks for updating the
83 * Checker's state through any ThreadContext accesses. This allows the
84 * checker to be able to correctly verify instructions, even with
85 * external accesses to the ThreadContext that change state.
87 class CheckerCPU : public BaseCPU
90 typedef TheISA::MachInst MachInst;
91 typedef TheISA::FloatReg FloatReg;
92 typedef TheISA::FloatRegBits FloatRegBits;
93 typedef TheISA::MiscReg MiscReg;
97 struct Params : public BaseCPU::Params
106 bool warnOnlyOnLoadError;
110 CheckerCPU(Params *p);
111 virtual ~CheckerCPU();
115 void setMemory(MemObject *mem);
119 void setSystem(System *system);
123 void setIcachePort(Port *icache_port);
127 void setDcachePort(Port *dcache_port);
132 // Primary thread being run.
133 SimpleThread *thread;
141 Addr dbg_vtophys(Addr addr);
152 // current instruction
155 // Pointer to the one memory request.
158 StaticInstPtr curStaticInst;
160 // number of simulated instructions
162 Counter startNumInst;
164 std::queue<int> miscRegIdxs;
166 virtual Counter totalInstructions() const
168 return numInst - startNumInst;
171 // number of simulated loads
173 Counter startNumLoad;
175 virtual void serialize(std::ostream &os);
176 virtual void unserialize(Checkpoint *cp, const std::string §ion);
179 Fault read(Addr addr, T &data, unsigned flags);
182 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
184 // These functions are only used in CPU models that split
185 // effective address computation from the actual memory access.
186 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
187 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
189 void prefetch(Addr addr, unsigned flags)
191 // need to do this...
194 void writeHint(Addr addr, int size, unsigned flags)
196 // need to do this...
199 Fault copySrcTranslate(Addr src);
201 Fault copy(Addr dest);
203 // The register accessor methods provide the index of the
204 // instruction's operand (e.g., 0 or 1), not the architectural
205 // register index, to simplify the implementation of register
206 // renaming. We find the architectural register index by indexing
207 // into the instruction's own operand index table. Note that a
208 // raw pointer to the StaticInst is provided instead of a
209 // ref-counted StaticInstPtr to redice overhead. This is fine as
210 // long as these methods don't copy the pointer into any long-term
211 // storage (which is pretty hard to imagine they would have reason
214 uint64_t readIntReg(const StaticInst *si, int idx)
216 return thread->readIntReg(si->srcRegIdx(idx));
219 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
221 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
222 return thread->readFloatReg(reg_idx, width);
225 FloatReg readFloatReg(const StaticInst *si, int idx)
227 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
228 return thread->readFloatReg(reg_idx);
231 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
233 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
234 return thread->readFloatRegBits(reg_idx, width);
237 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
239 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
240 return thread->readFloatRegBits(reg_idx);
243 void setIntReg(const StaticInst *si, int idx, uint64_t val)
245 thread->setIntReg(si->destRegIdx(idx), val);
246 result.integer = val;
249 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
251 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
252 thread->setFloatReg(reg_idx, val, width);
263 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
265 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
266 thread->setFloatReg(reg_idx, val);
270 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
273 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
274 thread->setFloatRegBits(reg_idx, val, width);
275 result.integer = val;
278 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
280 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
281 thread->setFloatRegBits(reg_idx, val);
282 result.integer = val;
285 uint64_t readPC() { return thread->readPC(); }
287 uint64_t readNextPC() { return thread->readNextPC(); }
289 void setNextPC(uint64_t val) {
290 thread->setNextPC(val);
293 MiscReg readMiscReg(int misc_reg)
295 return thread->readMiscReg(misc_reg);
298 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
300 return thread->readMiscRegWithEffect(misc_reg, fault);
303 Fault setMiscReg(int misc_reg, const MiscReg &val)
305 result.integer = val;
306 miscRegIdxs.push(misc_reg);
307 return thread->setMiscReg(misc_reg, val);
310 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
312 miscRegIdxs.push(misc_reg);
313 return thread->setMiscRegWithEffect(misc_reg, val);
316 void recordPCChange(uint64_t val) { changedPC = true; }
317 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
319 bool translateInstReq(Request *req);
320 void translateDataWriteReq(Request *req);
321 void translateDataReadReq(Request *req);
324 Fault hwrei() { return thread->hwrei(); }
325 int readIntrFlag() { return thread->readIntrFlag(); }
326 void setIntrFlag(int val) { thread->setIntrFlag(val); }
327 bool inPalMode() { return thread->inPalMode(); }
328 void ev5_trap(Fault fault) { fault->invoke(tc); }
329 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
331 // Assume that the normal CPU's call to syscall was successful.
332 // The checker's state would have already been updated by the syscall.
333 void syscall(uint64_t callnum) { }
342 bool checkFlags(Request *req);
346 ThreadContext *tcBase() { return tc; }
347 SimpleThread *threadBase() { return thread; }
349 Result unverifiedResult;
350 Request *unverifiedReq;
351 uint8_t *unverifiedMemData;
358 bool warnOnlyOnLoadError;
360 InstSeqNum youngestSN;
364 * Templated Checker class. This Checker class is templated on the
365 * DynInstPtr of the instruction type that will be verified. Proper
366 * template instantiations of the Checker must be placed at the bottom
369 template <class DynInstPtr>
370 class Checker : public CheckerCPU
377 void switchOut(Sampler *s);
378 void takeOverFrom(BaseCPU *oldCPU);
380 void verify(DynInstPtr &inst);
382 void validateInst(DynInstPtr &inst);
383 void validateExecution(DynInstPtr &inst);
384 void validateState();
386 void copyResult(DynInstPtr &inst);
389 void handleError(DynInstPtr &inst)
395 void dumpAndExit(DynInstPtr &inst);
397 std::list<DynInstPtr> instList;
398 typedef typename std::list<DynInstPtr>::iterator InstListIt;
402 #endif // __CPU_CHECKER_CPU_HH__