src/cpu/checker/cpu.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_CHECKER_CPU_HH__
  32 #define __CPU_CHECKER_CPU_HH__
  33
  34 #include <list>
  35 #include <queue>
  36 #include <map>
  37
  38 #include "arch/types.hh"
  39 #include "base/statistics.hh"
  40 #include "config/full_system.hh"
  41 #include "cpu/base.hh"
  42 #include "cpu/base_dyn_inst.hh"
  43 #include "cpu/simple_thread.hh"
  44 #include "cpu/pc_event.hh"
  45 #include "cpu/static_inst.hh"
  46 #include "sim/eventq.hh"
  47
  48 // forward declarations
  49 #if FULL_SYSTEM
  50 class Processor;
  51 class AlphaITB;
  52 class AlphaDTB;
  53 class PhysicalMemory;
  54
  55 class RemoteGDB;
  56 class GDBListener;
  57
  58 #else
  59
  60 class Process;
  61
  62 #endif // FULL_SYSTEM
  63 template <class>
  64 class BaseDynInst;
  65 class ThreadContext;
  66 class MemInterface;
  67 class Checkpoint;
  68 class Request;
  69 class Sampler;
  70
  71 /**
  72  * CheckerCPU class.  Dynamically verifies instructions as they are
  73  * completed by making sure that the instruction and its results match
  74  * the independent execution of the benchmark inside the checker.  The
  75  * checker verifies instructions in order, regardless of the order in
  76  * which instructions complete.  There are certain results that can
  77  * not be verified, specifically the result of a store conditional or
  78  * the values of uncached accesses.  In these cases, and with
  79  * instructions marked as "IsUnverifiable", the checker assumes that
  80  * the value from the main CPU's execution is correct and simply
  81  * copies that value.  It provides a CheckerThreadContext (see
  82  * checker/thread_context.hh) that provides hooks for updating the
  83  * Checker's state through any ThreadContext accesses.  This allows the
  84  * checker to be able to correctly verify instructions, even with
  85  * external accesses to the ThreadContext that change state.
  86  */
  87 class CheckerCPU : public BaseCPU
  88 {
  89   protected:
  90     typedef TheISA::MachInst MachInst;
  91     typedef TheISA::FloatReg FloatReg;
  92     typedef TheISA::FloatRegBits FloatRegBits;
  93     typedef TheISA::MiscReg MiscReg;
  94   public:
  95     virtual void init();
  96
  97     struct Params : public BaseCPU::Params
  98     {
  99 #if FULL_SYSTEM
 100         AlphaITB *itb;
 101         AlphaDTB *dtb;
 102 #else
 103         Process *process;
 104 #endif
 105         bool exitOnError;
 106         bool warnOnlyOnLoadError;
 107     };
 108
 109   public:
 110     CheckerCPU(Params *p);
 111     virtual ~CheckerCPU();
 112
 113     Process *process;
 114
 115     void setMemory(MemObject *mem);
 116
 117     MemObject *memPtr;
 118
 119     void setSystem(System *system);
 120
 121     System *systemPtr;
 122
 123     void setIcachePort(Port *icache_port);
 124
 125     Port *icachePort;
 126
 127     void setDcachePort(Port *dcache_port);
 128
 129     Port *dcachePort;
 130
 131   public:
 132     // Primary thread being run.
 133     SimpleThread *thread;
 134
 135     ThreadContext *tc;
 136
 137     AlphaITB *itb;
 138     AlphaDTB *dtb;
 139
 140 #if FULL_SYSTEM
 141     Addr dbg_vtophys(Addr addr);
 142 #endif
 143
 144     union Result {
 145         uint64_t integer;
 146         float fp;
 147         double dbl;
 148     };
 149
 150     Result result;
 151
 152     // current instruction
 153     MachInst machInst;
 154
 155     // Pointer to the one memory request.
 156     RequestPtr memReq;
 157
 158     StaticInstPtr curStaticInst;
 159
 160     // number of simulated instructions
 161     Counter numInst;
 162     Counter startNumInst;
 163
 164     std::queue<int> miscRegIdxs;
 165
 166     virtual Counter totalInstructions() const
 167     {
 168         return numInst - startNumInst;
 169     }
 170
 171     // number of simulated loads
 172     Counter numLoad;
 173     Counter startNumLoad;
 174
 175     virtual void serialize(std::ostream &os);
 176     virtual void unserialize(Checkpoint *cp, const std::string &section);
 177
 178     template <class T>
 179     Fault read(Addr addr, T &data, unsigned flags);
 180
 181     template <class T>
 182     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 183
 184     // These functions are only used in CPU models that split
 185     // effective address computation from the actual memory access.
 186     void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
 187     Addr getEA()        { panic("SimpleCPU::getEA() not implemented\n"); }
 188
 189     void prefetch(Addr addr, unsigned flags)
 190     {
 191         // need to do this...
 192     }
 193
 194     void writeHint(Addr addr, int size, unsigned flags)
 195     {
 196         // need to do this...
 197     }
 198
 199     Fault copySrcTranslate(Addr src);
 200
 201     Fault copy(Addr dest);
 202
 203     // The register accessor methods provide the index of the
 204     // instruction's operand (e.g., 0 or 1), not the architectural
 205     // register index, to simplify the implementation of register
 206     // renaming.  We find the architectural register index by indexing
 207     // into the instruction's own operand index table.  Note that a
 208     // raw pointer to the StaticInst is provided instead of a
 209     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 210     // long as these methods don't copy the pointer into any long-term
 211     // storage (which is pretty hard to imagine they would have reason
 212     // to do).
 213
 214     uint64_t readIntReg(const StaticInst *si, int idx)
 215     {
 216         return thread->readIntReg(si->srcRegIdx(idx));
 217     }
 218
 219     FloatReg readFloatReg(const StaticInst *si, int idx, int width)
 220     {
 221         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 222         return thread->readFloatReg(reg_idx, width);
 223     }
 224
 225     FloatReg readFloatReg(const StaticInst *si, int idx)
 226     {
 227         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 228         return thread->readFloatReg(reg_idx);
 229     }
 230
 231     FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
 232     {
 233         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 234         return thread->readFloatRegBits(reg_idx, width);
 235     }
 236
 237     FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
 238     {
 239         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 240         return thread->readFloatRegBits(reg_idx);
 241     }
 242
 243     void setIntReg(const StaticInst *si, int idx, uint64_t val)
 244     {
 245         thread->setIntReg(si->destRegIdx(idx), val);
 246         result.integer = val;
 247     }
 248
 249     void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
 250     {
 251         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 252         thread->setFloatReg(reg_idx, val, width);
 253         switch(width) {
 254           case 32:
 255             result.fp = val;
 256             break;
 257           case 64:
 258             result.dbl = val;
 259             break;
 260         };
 261     }
 262
 263     void setFloatReg(const StaticInst *si, int idx, FloatReg val)
 264     {
 265         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 266         thread->setFloatReg(reg_idx, val);
 267         result.fp = val;
 268     }
 269
 270     void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
 271                          int width)
 272     {
 273         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 274         thread->setFloatRegBits(reg_idx, val, width);
 275         result.integer = val;
 276     }
 277
 278     void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
 279     {
 280         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 281         thread->setFloatRegBits(reg_idx, val);
 282         result.integer = val;
 283     }
 284
 285     uint64_t readPC() { return thread->readPC(); }
 286
 287     uint64_t readNextPC() { return thread->readNextPC(); }
 288
 289     void setNextPC(uint64_t val) {
 290         thread->setNextPC(val);
 291     }
 292
 293     MiscReg readMiscReg(int misc_reg)
 294     {
 295         return thread->readMiscReg(misc_reg);
 296     }
 297
 298     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
 299     {
 300         return thread->readMiscRegWithEffect(misc_reg, fault);
 301     }
 302
 303     Fault setMiscReg(int misc_reg, const MiscReg &val)
 304     {
 305         result.integer = val;
 306         miscRegIdxs.push(misc_reg);
 307         return thread->setMiscReg(misc_reg, val);
 308     }
 309
 310     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 311     {
 312         miscRegIdxs.push(misc_reg);
 313         return thread->setMiscRegWithEffect(misc_reg, val);
 314     }
 315
 316     void recordPCChange(uint64_t val) { changedPC = true; }
 317     void recordNextPCChange(uint64_t val) { changedNextPC = true; }
 318
 319     bool translateInstReq(Request *req);
 320     void translateDataWriteReq(Request *req);
 321     void translateDataReadReq(Request *req);
 322
 323 #if FULL_SYSTEM
 324     Fault hwrei() { return thread->hwrei(); }
 325     int readIntrFlag() { return thread->readIntrFlag(); }
 326     void setIntrFlag(int val) { thread->setIntrFlag(val); }
 327     bool inPalMode() { return thread->inPalMode(); }
 328     void ev5_trap(Fault fault) { fault->invoke(tc); }
 329     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
 330 #else
 331     // Assume that the normal CPU's call to syscall was successful.
 332     // The checker's state would have already been updated by the syscall.
 333     void syscall(uint64_t callnum) { }
 334 #endif
 335
 336     void handleError()
 337     {
 338         if (exitOnError)
 339             dumpAndExit();
 340     }
 341
 342     bool checkFlags(Request *req);
 343
 344     void dumpAndExit();
 345
 346     ThreadContext *tcBase() { return tc; }
 347     SimpleThread *threadBase() { return thread; }
 348
 349     Result unverifiedResult;
 350     Request *unverifiedReq;
 351     uint8_t *unverifiedMemData;
 352
 353     bool changedPC;
 354     bool willChangePC;
 355     uint64_t newPC;
 356     bool changedNextPC;
 357     bool exitOnError;
 358     bool warnOnlyOnLoadError;
 359
 360     InstSeqNum youngestSN;
 361 };
 362
 363 /**
 364  * Templated Checker class.  This Checker class is templated on the
 365  * DynInstPtr of the instruction type that will be verified.  Proper
 366  * template instantiations of the Checker must be placed at the bottom
 367  * of checker/cpu.cc.
 368  */
 369 template <class DynInstPtr>
 370 class Checker : public CheckerCPU
 371 {
 372   public:
 373     Checker(Params *p)
 374         : CheckerCPU(p)
 375     { }
 376
 377     void switchOut(Sampler *s);
 378     void takeOverFrom(BaseCPU *oldCPU);
 379
 380     void verify(DynInstPtr &inst);
 381
 382     void validateInst(DynInstPtr &inst);
 383     void validateExecution(DynInstPtr &inst);
 384     void validateState();
 385
 386     void copyResult(DynInstPtr &inst);
 387
 388   private:
 389     void handleError(DynInstPtr &inst)
 390     {
 391         if (exitOnError)
 392             dumpAndExit(inst);
 393     }
 394
 395     void dumpAndExit(DynInstPtr &inst);
 396
 397     std::list<DynInstPtr> instList;
 398     typedef typename std::list<DynInstPtr>::iterator InstListIt;
 399     void dumpInsts();
 400 };
 401
 402 #endif // __CPU_CHECKER_CPU_HH__