src/cpu/checker/cpu.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_CHECKER_CPU_HH__
  32 #define __CPU_CHECKER_CPU_HH__
  33
  34 #include <list>
  35 #include <queue>
  36 #include <map>
  37
  38 #include "arch/types.hh"
  39 #include "base/statistics.hh"
  40 #include "config/full_system.hh"
  41 #include "cpu/base.hh"
  42 #include "cpu/base_dyn_inst.hh"
  43 #include "cpu/simple_thread.hh"
  44 #include "cpu/pc_event.hh"
  45 #include "cpu/static_inst.hh"
  46 #include "sim/eventq.hh"
  47
  48 // forward declarations
  49 #if FULL_SYSTEM
  50 class Processor;
  51 class AlphaITB;
  52 class AlphaDTB;
  53 class PhysicalMemory;
  54
  55 class RemoteGDB;
  56 class GDBListener;
  57
  58 #else
  59
  60 class Process;
  61
  62 #endif // FULL_SYSTEM
  63 template <class>
  64 class BaseDynInst;
  65 class ThreadContext;
  66 class MemInterface;
  67 class Checkpoint;
  68 class Request;
  69
  70 /**
  71  * CheckerCPU class.  Dynamically verifies instructions as they are
  72  * completed by making sure that the instruction and its results match
  73  * the independent execution of the benchmark inside the checker.  The
  74  * checker verifies instructions in order, regardless of the order in
  75  * which instructions complete.  There are certain results that can
  76  * not be verified, specifically the result of a store conditional or
  77  * the values of uncached accesses.  In these cases, and with
  78  * instructions marked as "IsUnverifiable", the checker assumes that
  79  * the value from the main CPU's execution is correct and simply
  80  * copies that value.  It provides a CheckerThreadContext (see
  81  * checker/thread_context.hh) that provides hooks for updating the
  82  * Checker's state through any ThreadContext accesses.  This allows the
  83  * checker to be able to correctly verify instructions, even with
  84  * external accesses to the ThreadContext that change state.
  85  */
  86 class CheckerCPU : public BaseCPU
  87 {
  88   protected:
  89     typedef TheISA::MachInst MachInst;
  90     typedef TheISA::FloatReg FloatReg;
  91     typedef TheISA::FloatRegBits FloatRegBits;
  92     typedef TheISA::MiscReg MiscReg;
  93   public:
  94     virtual void init();
  95
  96     struct Params : public BaseCPU::Params
  97     {
  98 #if FULL_SYSTEM
  99         AlphaITB *itb;
 100         AlphaDTB *dtb;
 101 #else
 102         Process *process;
 103 #endif
 104         bool exitOnError;
 105         bool updateOnError;
 106         bool warnOnlyOnLoadError;
 107     };
 108
 109   public:
 110     CheckerCPU(Params *p);
 111     virtual ~CheckerCPU();
 112
 113     Process *process;
 114
 115     void setSystem(System *system);
 116
 117     System *systemPtr;
 118
 119     void setIcachePort(Port *icache_port);
 120
 121     Port *icachePort;
 122
 123     void setDcachePort(Port *dcache_port);
 124
 125     Port *dcachePort;
 126
 127     virtual Port *getPort(const std::string &name, int idx)
 128     {
 129         panic("Not supported on checker!");
 130         return NULL;
 131     }
 132
 133   public:
 134     // Primary thread being run.
 135     SimpleThread *thread;
 136
 137     ThreadContext *tc;
 138
 139     AlphaITB *itb;
 140     AlphaDTB *dtb;
 141
 142 #if FULL_SYSTEM
 143     Addr dbg_vtophys(Addr addr);
 144 #endif
 145
 146     union Result {
 147         uint64_t integer;
 148 //        float fp;
 149         double dbl;
 150     };
 151
 152     Result result;
 153
 154     // current instruction
 155     MachInst machInst;
 156
 157     // Pointer to the one memory request.
 158     RequestPtr memReq;
 159
 160     StaticInstPtr curStaticInst;
 161
 162     // number of simulated instructions
 163     Counter numInst;
 164     Counter startNumInst;
 165
 166     std::queue<int> miscRegIdxs;
 167
 168     virtual Counter totalInstructions() const
 169     {
 170         return 0;
 171     }
 172
 173     // number of simulated loads
 174     Counter numLoad;
 175     Counter startNumLoad;
 176
 177     virtual void serialize(std::ostream &os);
 178     virtual void unserialize(Checkpoint *cp, const std::string &section);
 179
 180     template <class T>
 181     Fault read(Addr addr, T &data, unsigned flags);
 182
 183     template <class T>
 184     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 185
 186     // These functions are only used in CPU models that split
 187     // effective address computation from the actual memory access.
 188     void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
 189     Addr getEA()        { panic("SimpleCPU::getEA() not implemented\n"); }
 190
 191     void prefetch(Addr addr, unsigned flags)
 192     {
 193         // need to do this...
 194     }
 195
 196     void writeHint(Addr addr, int size, unsigned flags)
 197     {
 198         // need to do this...
 199     }
 200
 201     Fault copySrcTranslate(Addr src);
 202
 203     Fault copy(Addr dest);
 204
 205     // The register accessor methods provide the index of the
 206     // instruction's operand (e.g., 0 or 1), not the architectural
 207     // register index, to simplify the implementation of register
 208     // renaming.  We find the architectural register index by indexing
 209     // into the instruction's own operand index table.  Note that a
 210     // raw pointer to the StaticInst is provided instead of a
 211     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 212     // long as these methods don't copy the pointer into any long-term
 213     // storage (which is pretty hard to imagine they would have reason
 214     // to do).
 215
 216     uint64_t readIntReg(const StaticInst *si, int idx)
 217     {
 218         return thread->readIntReg(si->srcRegIdx(idx));
 219     }
 220
 221     FloatReg readFloatReg(const StaticInst *si, int idx, int width)
 222     {
 223         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 224         return thread->readFloatReg(reg_idx, width);
 225     }
 226
 227     FloatReg readFloatReg(const StaticInst *si, int idx)
 228     {
 229         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 230         return thread->readFloatReg(reg_idx);
 231     }
 232
 233     FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
 234     {
 235         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 236         return thread->readFloatRegBits(reg_idx, width);
 237     }
 238
 239     FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
 240     {
 241         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 242         return thread->readFloatRegBits(reg_idx);
 243     }
 244
 245     void setIntReg(const StaticInst *si, int idx, uint64_t val)
 246     {
 247         thread->setIntReg(si->destRegIdx(idx), val);
 248         result.integer = val;
 249     }
 250
 251     void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
 252     {
 253         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 254         thread->setFloatReg(reg_idx, val, width);
 255         switch(width) {
 256           case 32:
 257             result.dbl = (double)val;
 258             break;
 259           case 64:
 260             result.dbl = val;
 261             break;
 262         };
 263     }
 264
 265     void setFloatReg(const StaticInst *si, int idx, FloatReg val)
 266     {
 267         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 268         thread->setFloatReg(reg_idx, val);
 269         result.dbl = (double)val;
 270     }
 271
 272     void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
 273                          int width)
 274     {
 275         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 276         thread->setFloatRegBits(reg_idx, val, width);
 277         result.integer = val;
 278     }
 279
 280     void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
 281     {
 282         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 283         thread->setFloatRegBits(reg_idx, val);
 284         result.integer = val;
 285     }
 286
 287     uint64_t readPC() { return thread->readPC(); }
 288
 289     uint64_t readNextPC() { return thread->readNextPC(); }
 290
 291     void setNextPC(uint64_t val) {
 292         thread->setNextPC(val);
 293     }
 294
 295     MiscReg readMiscReg(int misc_reg)
 296     {
 297         return thread->readMiscReg(misc_reg);
 298     }
 299
 300     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
 301     {
 302         return thread->readMiscRegWithEffect(misc_reg, fault);
 303     }
 304
 305     Fault setMiscReg(int misc_reg, const MiscReg &val)
 306     {
 307         result.integer = val;
 308         miscRegIdxs.push(misc_reg);
 309         return thread->setMiscReg(misc_reg, val);
 310     }
 311
 312     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 313     {
 314         miscRegIdxs.push(misc_reg);
 315         return thread->setMiscRegWithEffect(misc_reg, val);
 316     }
 317
 318     void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
 319     void recordNextPCChange(uint64_t val) { changedNextPC = true; }
 320
 321     bool translateInstReq(Request *req);
 322     void translateDataWriteReq(Request *req);
 323     void translateDataReadReq(Request *req);
 324
 325 #if FULL_SYSTEM
 326     Fault hwrei() { return thread->hwrei(); }
 327     int readIntrFlag() { return thread->readIntrFlag(); }
 328     void setIntrFlag(int val) { thread->setIntrFlag(val); }
 329     bool inPalMode() { return thread->inPalMode(); }
 330     void ev5_trap(Fault fault) { fault->invoke(tc); }
 331     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
 332 #else
 333     // Assume that the normal CPU's call to syscall was successful.
 334     // The checker's state would have already been updated by the syscall.
 335     void syscall(uint64_t callnum) { }
 336 #endif
 337
 338     void handleError()
 339     {
 340         if (exitOnError)
 341             dumpAndExit();
 342     }
 343
 344     bool checkFlags(Request *req);
 345
 346     void dumpAndExit();
 347
 348     ThreadContext *tcBase() { return tc; }
 349     SimpleThread *threadBase() { return thread; }
 350
 351     Result unverifiedResult;
 352     Request *unverifiedReq;
 353     uint8_t *unverifiedMemData;
 354
 355     bool changedPC;
 356     bool willChangePC;
 357     uint64_t newPC;
 358     bool changedNextPC;
 359     bool exitOnError;
 360     bool updateOnError;
 361     bool warnOnlyOnLoadError;
 362
 363     InstSeqNum youngestSN;
 364 };
 365
 366 /**
 367  * Templated Checker class.  This Checker class is templated on the
 368  * DynInstPtr of the instruction type that will be verified.  Proper
 369  * template instantiations of the Checker must be placed at the bottom
 370  * of checker/cpu.cc.
 371  */
 372 template <class DynInstPtr>
 373 class Checker : public CheckerCPU
 374 {
 375   public:
 376     Checker(Params *p)
 377         : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
 378     { }
 379
 380     void switchOut();
 381     void takeOverFrom(BaseCPU *oldCPU);
 382
 383     void verify(DynInstPtr &inst);
 384
 385     void validateInst(DynInstPtr &inst);
 386     void validateExecution(DynInstPtr &inst);
 387     void validateState();
 388
 389     void copyResult(DynInstPtr &inst);
 390
 391   private:
 392     void handleError(DynInstPtr &inst)
 393     {
 394         if (exitOnError) {
 395             dumpAndExit(inst);
 396         } else if (updateOnError) {
 397             updateThisCycle = true;
 398         }
 399     }
 400
 401     void dumpAndExit(DynInstPtr &inst);
 402
 403     bool updateThisCycle;
 404
 405     DynInstPtr unverifiedInst;
 406
 407     std::list<DynInstPtr> instList;
 408     typedef typename std::list<DynInstPtr>::iterator InstListIt;
 409     void dumpInsts();
 410 };
 411
 412 #endif // __CPU_CHECKER_CPU_HH__