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31 #ifndef __CPU_CHECKER_CPU_HH__
32 #define __CPU_CHECKER_CPU_HH__
38 #include "arch/types.hh"
39 #include "base/statistics.hh"
40 #include "config/full_system.hh"
41 #include "cpu/base.hh"
42 #include "cpu/base_dyn_inst.hh"
43 #include "cpu/simple_thread.hh"
44 #include "cpu/pc_event.hh"
45 #include "cpu/static_inst.hh"
46 #include "sim/eventq.hh"
48 // forward declarations
74 * CheckerCPU class. Dynamically verifies instructions as they are
75 * completed by making sure that the instruction and its results match
76 * the independent execution of the benchmark inside the checker. The
77 * checker verifies instructions in order, regardless of the order in
78 * which instructions complete. There are certain results that can
79 * not be verified, specifically the result of a store conditional or
80 * the values of uncached accesses. In these cases, and with
81 * instructions marked as "IsUnverifiable", the checker assumes that
82 * the value from the main CPU's execution is correct and simply
83 * copies that value. It provides a CheckerThreadContext (see
84 * checker/thread_context.hh) that provides hooks for updating the
85 * Checker's state through any ThreadContext accesses. This allows the
86 * checker to be able to correctly verify instructions, even with
87 * external accesses to the ThreadContext that change state.
89 class CheckerCPU : public BaseCPU
92 typedef TheISA::MachInst MachInst;
93 typedef TheISA::FloatReg FloatReg;
94 typedef TheISA::FloatRegBits FloatRegBits;
95 typedef TheISA::MiscReg MiscReg;
99 struct Params : public BaseCPU::Params
109 bool warnOnlyOnLoadError;
113 CheckerCPU(Params *p);
114 virtual ~CheckerCPU();
118 void setSystem(System *system);
122 void setIcachePort(Port *icache_port);
126 void setDcachePort(Port *dcache_port);
130 virtual Port *getPort(const std::string &name, int idx)
132 panic("Not supported on checker!");
137 // Primary thread being run.
138 SimpleThread *thread;
146 Addr dbg_vtophys(Addr addr);
157 // current instruction
160 // Pointer to the one memory request.
163 StaticInstPtr curStaticInst;
165 // number of simulated instructions
167 Counter startNumInst;
169 std::queue<int> miscRegIdxs;
171 virtual Counter totalInstructions() const
176 // number of simulated loads
178 Counter startNumLoad;
180 virtual void serialize(std::ostream &os);
181 virtual void unserialize(Checkpoint *cp, const std::string §ion);
184 Fault read(Addr addr, T &data, unsigned flags);
187 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
189 // These functions are only used in CPU models that split
190 // effective address computation from the actual memory access.
191 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
192 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
194 void prefetch(Addr addr, unsigned flags)
196 // need to do this...
199 void writeHint(Addr addr, int size, unsigned flags)
201 // need to do this...
204 Fault copySrcTranslate(Addr src);
206 Fault copy(Addr dest);
208 // The register accessor methods provide the index of the
209 // instruction's operand (e.g., 0 or 1), not the architectural
210 // register index, to simplify the implementation of register
211 // renaming. We find the architectural register index by indexing
212 // into the instruction's own operand index table. Note that a
213 // raw pointer to the StaticInst is provided instead of a
214 // ref-counted StaticInstPtr to redice overhead. This is fine as
215 // long as these methods don't copy the pointer into any long-term
216 // storage (which is pretty hard to imagine they would have reason
219 uint64_t readIntRegOperand(const StaticInst *si, int idx)
221 return thread->readIntReg(si->srcRegIdx(idx));
224 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
226 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
227 return thread->readFloatReg(reg_idx, width);
230 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
232 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
233 return thread->readFloatReg(reg_idx);
236 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
239 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
240 return thread->readFloatRegBits(reg_idx, width);
243 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
245 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
246 return thread->readFloatRegBits(reg_idx);
249 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
251 thread->setIntReg(si->destRegIdx(idx), val);
252 result.integer = val;
255 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
258 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
259 thread->setFloatReg(reg_idx, val, width);
262 result.dbl = (double)val;
270 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
272 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
273 thread->setFloatReg(reg_idx, val);
274 result.dbl = (double)val;
277 void setFloatRegOperandBits(const StaticInst *si, int idx,
278 FloatRegBits val, int width)
280 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
281 thread->setFloatRegBits(reg_idx, val, width);
282 result.integer = val;
285 void setFloatRegOperandBits(const StaticInst *si, int idx,
288 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
289 thread->setFloatRegBits(reg_idx, val);
290 result.integer = val;
293 uint64_t readPC() { return thread->readPC(); }
295 uint64_t readNextPC() { return thread->readNextPC(); }
297 void setNextPC(uint64_t val) {
298 thread->setNextPC(val);
301 MiscReg readMiscReg(int misc_reg)
303 return thread->readMiscReg(misc_reg);
306 MiscReg readMiscRegWithEffect(int misc_reg)
308 return thread->readMiscRegWithEffect(misc_reg);
311 void setMiscReg(int misc_reg, const MiscReg &val)
313 result.integer = val;
314 miscRegIdxs.push(misc_reg);
315 return thread->setMiscReg(misc_reg, val);
318 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
320 miscRegIdxs.push(misc_reg);
321 return thread->setMiscRegWithEffect(misc_reg, val);
324 void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
325 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
327 bool translateInstReq(Request *req);
328 void translateDataWriteReq(Request *req);
329 void translateDataReadReq(Request *req);
332 Fault hwrei() { return thread->hwrei(); }
333 void ev5_trap(Fault fault) { fault->invoke(tc); }
334 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
336 // Assume that the normal CPU's call to syscall was successful.
337 // The checker's state would have already been updated by the syscall.
338 void syscall(uint64_t callnum) { }
347 bool checkFlags(Request *req);
351 ThreadContext *tcBase() { return tc; }
352 SimpleThread *threadBase() { return thread; }
354 Result unverifiedResult;
355 Request *unverifiedReq;
356 uint8_t *unverifiedMemData;
364 bool warnOnlyOnLoadError;
366 InstSeqNum youngestSN;
370 * Templated Checker class. This Checker class is templated on the
371 * DynInstPtr of the instruction type that will be verified. Proper
372 * template instantiations of the Checker must be placed at the bottom
375 template <class DynInstPtr>
376 class Checker : public CheckerCPU
380 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
384 void takeOverFrom(BaseCPU *oldCPU);
386 void verify(DynInstPtr &inst);
388 void validateInst(DynInstPtr &inst);
389 void validateExecution(DynInstPtr &inst);
390 void validateState();
392 void copyResult(DynInstPtr &inst);
395 void handleError(DynInstPtr &inst)
399 } else if (updateOnError) {
400 updateThisCycle = true;
404 void dumpAndExit(DynInstPtr &inst);
406 bool updateThisCycle;
408 DynInstPtr unverifiedInst;
410 std::list<DynInstPtr> instList;
411 typedef typename std::list<DynInstPtr>::iterator InstListIt;
415 #endif // __CPU_CHECKER_CPU_HH__