src/cpu/checker/cpu_impl.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Geoffrey Blake
  42  */
  43
  44 #include <list>
  45 #include <string>
  46
  47 #include "arch/isa_traits.hh"
  48 #include "arch/vtophys.hh"
  49 #include "base/refcnt.hh"
  50 #include "config/the_isa.hh"
  51 #include "cpu/base_dyn_inst.hh"
  52 #include "cpu/exetrace.hh"
  53 #include "cpu/simple_thread.hh"
  54 #include "cpu/static_inst.hh"
  55 #include "cpu/thread_context.hh"
  56 #include "cpu/checker/cpu.hh"
  57 #include "debug/Checker.hh"
  58 #include "sim/full_system.hh"
  59 #include "sim/sim_object.hh"
  60 #include "sim/stats.hh"
  61
  62 using namespace std;
  63 using namespace TheISA;
  64
  65 template <class Impl>
  66 void
  67 Checker<Impl>::advancePC(Fault fault)
  68 {
  69     if (fault != NoFault) {
  70         curMacroStaticInst = StaticInst::nullStaticInstPtr;
  71         fault->invoke(tc, curStaticInst);
  72         predecoder.reset();
  73     } else {
  74         if (curStaticInst) {
  75             if (curStaticInst->isLastMicroop())
  76                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
  77             TheISA::PCState pcState = thread->pcState();
  78             TheISA::advancePC(pcState, curStaticInst);
  79             thread->pcState(pcState);
  80             DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
  81         }
  82     }
  83 }
  84 //////////////////////////////////////////////////
  85
  86 template <class Impl>
  87 void
  88 Checker<Impl>::handlePendingInt()
  89 {
  90     DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
  91                      thread->pcState(), instList.size());
  92     DynInstPtr boundaryInst = NULL;
  93     if (!instList.empty()) {
  94         // Set the instructions as completed and verify as much as possible.
  95         DynInstPtr inst;
  96         typename std::list<DynInstPtr>::iterator itr;
  97
  98         for (itr = instList.begin(); itr != instList.end(); itr++) {
  99             (*itr)->setCompleted();
 100         }
 101
 102         inst = instList.front();
 103         boundaryInst = instList.back();
 104         verify(inst); // verify the instructions
 105         inst = NULL;
 106     }
 107     if ((!boundaryInst && curMacroStaticInst &&
 108           curStaticInst->isDelayedCommit() &&
 109           !curStaticInst->isLastMicroop()) ||
 110         (boundaryInst && boundaryInst->isDelayedCommit() &&
 111          !boundaryInst->isLastMicroop())) {
 112         panic("%lli: Trying to take an interrupt in middle of "
 113               "a non-interuptable instruction!", curTick());
 114     }
 115     boundaryInst = NULL;
 116     predecoder.reset();
 117     curMacroStaticInst = StaticInst::nullStaticInstPtr;
 118 }
 119
 120 template <class Impl>
 121 void
 122 Checker<Impl>::verify(DynInstPtr &completed_inst)
 123 {
 124     DynInstPtr inst;
 125
 126     // Make sure serializing instructions are actually
 127     // seen as serializing to commit. instList should be
 128     // empty in these cases.
 129     if ((completed_inst->isSerializing() ||
 130         completed_inst->isSerializeBefore()) &&
 131         (!instList.empty() ?
 132          (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
 133         panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
 134               " entering instList with other instructions\n", curTick(),
 135               completed_inst->seqNum, completed_inst->pcState());
 136     }
 137
 138     // Either check this instruction, or add it to a list of
 139     // instructions waiting to be checked.  Instructions must be
 140     // checked in program order, so if a store has committed yet not
 141     // completed, there may be some instructions that are waiting
 142     // behind it that have completed and must be checked.
 143     if (!instList.empty()) {
 144         if (youngestSN < completed_inst->seqNum) {
 145             DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
 146                     completed_inst->seqNum, completed_inst->pcState());
 147             instList.push_back(completed_inst);
 148             youngestSN = completed_inst->seqNum;
 149         }
 150
 151         if (!instList.front()->isCompleted()) {
 152             return;
 153         } else {
 154             inst = instList.front();
 155             instList.pop_front();
 156         }
 157     } else {
 158         if (!completed_inst->isCompleted()) {
 159             if (youngestSN < completed_inst->seqNum) {
 160                 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
 161                         completed_inst->seqNum, completed_inst->pcState());
 162                 instList.push_back(completed_inst);
 163                 youngestSN = completed_inst->seqNum;
 164             }
 165             return;
 166         } else {
 167             if (youngestSN < completed_inst->seqNum) {
 168                 inst = completed_inst;
 169                 youngestSN = completed_inst->seqNum;
 170             } else {
 171                 return;
 172             }
 173         }
 174     }
 175
 176     // Make sure a serializing instruction is actually seen as
 177     // serializing. instList should be empty here
 178     if (inst->isSerializeAfter() && !instList.empty()) {
 179         panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
 180              " exiting instList with other instructions\n", curTick(),
 181              completed_inst->seqNum, completed_inst->pcState());
 182     }
 183     unverifiedInst = inst;
 184     inst = NULL;
 185
 186     // Try to check all instructions that are completed, ending if we
 187     // run out of instructions to check or if an instruction is not
 188     // yet completed.
 189     while (1) {
 190         DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
 191                 unverifiedInst->seqNum, unverifiedInst->pcState());
 192         unverifiedReq = NULL;
 193         unverifiedReq = unverifiedInst->reqToVerify;
 194         unverifiedMemData = unverifiedInst->memData;
 195         // Make sure results queue is empty
 196         while (!result.empty()) {
 197             result.pop();
 198         }
 199         numCycles++;
 200
 201         Fault fault = NoFault;
 202
 203         // maintain $r0 semantics
 204         thread->setIntReg(ZeroReg, 0);
 205 #if THE_ISA == ALPHA_ISA
 206         thread->setFloatReg(ZeroReg, 0.0);
 207 #endif
 208
 209         // Check if any recent PC changes match up with anything we
 210         // expect to happen.  This is mostly to check if traps or
 211         // PC-based events have occurred in both the checker and CPU.
 212         if (changedPC) {
 213             DPRINTF(Checker, "Changed PC recently to %s\n",
 214                     thread->pcState());
 215             if (willChangePC) {
 216                 if (newPCState == thread->pcState()) {
 217                     DPRINTF(Checker, "Changed PC matches expected PC\n");
 218                 } else {
 219                     warn("%lli: Changed PC does not match expected PC, "
 220                          "changed: %s, expected: %s",
 221                          curTick(), thread->pcState(), newPCState);
 222                     CheckerCPU::handleError();
 223                 }
 224                 willChangePC = false;
 225             }
 226             changedPC = false;
 227         }
 228         if (changedNextPC) {
 229             DPRINTF(Checker, "Changed NextPC recently to %#x\n",
 230                     thread->nextInstAddr());
 231             changedNextPC = false;
 232         }
 233
 234         // Try to fetch the instruction
 235         uint64_t fetchOffset = 0;
 236         bool fetchDone = false;
 237
 238         while (!fetchDone) {
 239             Addr fetch_PC = thread->instAddr();
 240             fetch_PC = (fetch_PC & PCMask) + fetchOffset;
 241
 242             // If not in the middle of a macro instruction
 243             if (!curMacroStaticInst) {
 244                 // set up memory request for instruction fetch
 245                 memReq = new Request(unverifiedInst->threadNumber, fetch_PC,
 246                                      sizeof(MachInst),
 247                                      0,
 248                                      masterId,
 249                                      fetch_PC, thread->contextId(),
 250                                      unverifiedInst->threadNumber);
 251                 memReq->setVirt(0, fetch_PC, sizeof(MachInst),
 252                                 Request::INST_FETCH, masterId, thread->instAddr());
 253
 254
 255                 fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute);
 256
 257                 if (fault != NoFault) {
 258                     if (unverifiedInst->getFault() == NoFault) {
 259                         // In this case the instruction was not a dummy
 260                         // instruction carrying an ITB fault.  In the single
 261                         // threaded case the ITB should still be able to
 262                         // translate this instruction; in the SMT case it's
 263                         // possible that its ITB entry was kicked out.
 264                         warn("%lli: Instruction PC %s was not found in the "
 265                              "ITB!", curTick(), thread->pcState());
 266                         handleError(unverifiedInst);
 267
 268                         // go to the next instruction
 269                         advancePC(NoFault);
 270
 271                         // Give up on an ITB fault..
 272                         delete memReq;
 273                         unverifiedInst = NULL;
 274                         return;
 275                     } else {
 276                         // The instruction is carrying an ITB fault.  Handle
 277                         // the fault and see if our results match the CPU on
 278                         // the next tick().
 279                         fault = unverifiedInst->getFault();
 280                         delete memReq;
 281                         break;
 282                     }
 283                 } else {
 284                     PacketPtr pkt = new Packet(memReq,
 285                                                MemCmd::ReadReq,
 286                                                Packet::Broadcast);
 287
 288                     pkt->dataStatic(&machInst);
 289                     icachePort->sendFunctional(pkt);
 290                     machInst = gtoh(machInst);
 291
 292                     delete memReq;
 293                     delete pkt;
 294                 }
 295             }
 296
 297             if (fault == NoFault) {
 298                 TheISA::PCState pcState = thread->pcState();
 299
 300                 if (isRomMicroPC(pcState.microPC())) {
 301                     fetchDone = true;
 302                     curStaticInst =
 303                         microcodeRom.fetchMicroop(pcState.microPC(), NULL);
 304                 } else if (!curMacroStaticInst) {
 305                     //We're not in the middle of a macro instruction
 306                     StaticInstPtr instPtr = NULL;
 307
 308                     //Predecode, ie bundle up an ExtMachInst
 309                     predecoder.setTC(thread->getTC());
 310                     //If more fetch data is needed, pass it in.
 311                     Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
 312                     predecoder.moreBytes(pcState, fetchPC, machInst);
 313
 314                     //If an instruction is ready, decode it.
 315                     //Otherwise, we'll have to fetch beyond the
 316                     //MachInst at the current pc.
 317                     if (predecoder.extMachInstReady()) {
 318                         fetchDone = true;
 319                         ExtMachInst newMachInst =
 320                             predecoder.getExtMachInst(pcState);
 321                         thread->pcState(pcState);
 322                         instPtr = thread->decoder.decode(newMachInst,
 323                                                          pcState.instAddr());
 324 #if THE_ISA != X86_ISA
 325                             machInst = newMachInst;
 326 #endif
 327                     } else {
 328                         fetchDone = false;
 329                         fetchOffset += sizeof(TheISA::MachInst);
 330                     }
 331
 332                     //If we decoded an instruction and it's microcoded,
 333                     //start pulling out micro ops
 334                     if (instPtr && instPtr->isMacroop()) {
 335                         curMacroStaticInst = instPtr;
 336                         curStaticInst =
 337                             instPtr->fetchMicroop(pcState.microPC());
 338                     } else {
 339                         curStaticInst = instPtr;
 340                     }
 341                 } else {
 342                     // Read the next micro op from the macro-op
 343                     curStaticInst =
 344                         curMacroStaticInst->fetchMicroop(pcState.microPC());
 345                     fetchDone = true;
 346                 }
 347             }
 348         }
 349         // reset predecoder on Checker
 350         predecoder.reset();
 351
 352         // Check Checker and CPU get same instruction, and record
 353         // any faults the CPU may have had.
 354         Fault unverifiedFault;
 355         if (fault == NoFault) {
 356             unverifiedFault = unverifiedInst->getFault();
 357
 358             // Checks that the instruction matches what we expected it to be.
 359             // Checks both the machine instruction and the PC.
 360             validateInst(unverifiedInst);
 361         }
 362
 363         // keep an instruction count
 364         numInst++;
 365
 366
 367         // Either the instruction was a fault and we should process the fault,
 368         // or we should just go ahead execute the instruction.  This assumes
 369         // that the instruction is properly marked as a fault.
 370         if (fault == NoFault) {
 371             // Execute Checker instruction and trace
 372             if (!unverifiedInst->isUnverifiable()) {
 373                 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
 374                                                            tc,
 375                                                            curStaticInst,
 376                                                            pcState(),
 377                                                            curMacroStaticInst);
 378                 fault = curStaticInst->execute(this, traceData);
 379                 if (traceData) {
 380                     traceData->dump();
 381                     delete traceData;
 382                 }
 383             }
 384
 385             if (fault == NoFault && unverifiedFault == NoFault) {
 386                 thread->funcExeInst++;
 387                 // Checks to make sure instrution results are correct.
 388                 validateExecution(unverifiedInst);
 389
 390                 if (curStaticInst->isLoad()) {
 391                     ++numLoad;
 392                 }
 393             } else if (fault != NoFault && unverifiedFault == NoFault) {
 394                 panic("%lli: sn: %lli at PC: %s took a fault in checker "
 395                       "but not in driver CPU\n", curTick(),
 396                       unverifiedInst->seqNum, unverifiedInst->pcState());
 397             } else if (fault == NoFault && unverifiedFault != NoFault) {
 398                 panic("%lli: sn: %lli at PC: %s took a fault in driver "
 399                       "CPU but not in checker\n", curTick(),
 400                       unverifiedInst->seqNum, unverifiedInst->pcState());
 401             }
 402         }
 403
 404         // Take any faults here
 405         if (fault != NoFault) {
 406             if (FullSystem) {
 407                 fault->invoke(tc, curStaticInst);
 408                 willChangePC = true;
 409                 newPCState = thread->pcState();
 410                 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
 411                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
 412             }
 413         } else {
 414            advancePC(fault);
 415         }
 416
 417         if (FullSystem) {
 418             // @todo: Determine if these should happen only if the
 419             // instruction hasn't faulted.  In the SimpleCPU case this may
 420             // not be true, but in the O3 or Ozone case this may be true.
 421             Addr oldpc;
 422             int count = 0;
 423             do {
 424                 oldpc = thread->instAddr();
 425                 system->pcEventQueue.service(tc);
 426                 count++;
 427             } while (oldpc != thread->instAddr());
 428             if (count > 1) {
 429                 willChangePC = true;
 430                 newPCState = thread->pcState();
 431                 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
 432             }
 433         }
 434
 435         // @todo:  Optionally can check all registers. (Or just those
 436         // that have been modified).
 437         validateState();
 438
 439         // Continue verifying instructions if there's another completed
 440         // instruction waiting to be verified.
 441         if (instList.empty()) {
 442             break;
 443         } else if (instList.front()->isCompleted()) {
 444             unverifiedInst = NULL;
 445             unverifiedInst = instList.front();
 446             instList.pop_front();
 447         } else {
 448             break;
 449         }
 450     }
 451     unverifiedInst = NULL;
 452 }
 453
 454 template <class Impl>
 455 void
 456 Checker<Impl>::switchOut()
 457 {
 458     instList.clear();
 459 }
 460
 461 template <class Impl>
 462 void
 463 Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
 464 {
 465 }
 466
 467 template <class Impl>
 468 void
 469 Checker<Impl>::validateInst(DynInstPtr &inst)
 470 {
 471     if (inst->instAddr() != thread->instAddr()) {
 472         warn("%lli: PCs do not match! Inst: %s, checker: %s",
 473              curTick(), inst->pcState(), thread->pcState());
 474         if (changedPC) {
 475             warn("%lli: Changed PCs recently, may not be an error",
 476                  curTick());
 477         } else {
 478             handleError(inst);
 479         }
 480     }
 481
 482
 483     MachInst mi;
 484 #if THE_ISA != X86_ISA
 485     mi = static_cast<MachInst>(inst->staticInst->machInst);
 486 #endif
 487
 488     if (mi != machInst) {
 489         panic("%lli: Binary instructions do not match! Inst: %#x, "
 490              "checker: %#x",
 491              curTick(), mi, machInst);
 492         handleError(inst);
 493     }
 494 }
 495
 496 template <class Impl>
 497 void
 498 Checker<Impl>::validateExecution(DynInstPtr &inst)
 499 {
 500     uint64_t checker_val;
 501     uint64_t inst_val;
 502     int idx = -1;
 503     bool result_mismatch = false;
 504
 505     if (inst->isUnverifiable()) {
 506         // Unverifiable instructions assume they were executed
 507         // properly by the CPU. Grab the result from the
 508         // instruction and write it to the register.
 509         copyResult(inst, 0, idx);
 510     } else if (inst->numDestRegs() > 0 && !result.empty()) {
 511         DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
 512                          inst->numDestRegs(), result.size());
 513         for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
 514             result.front().get(checker_val);
 515             result.pop();
 516             inst_val = 0;
 517             inst->template popResult<uint64_t>(inst_val);
 518             if (checker_val != inst_val) {
 519                 result_mismatch = true;
 520                 idx = i;
 521                 break;
 522             }
 523         }
 524     } // Checker CPU checks all the saved results in the dyninst passed by
 525       // the cpu model being checked against the saved results present in
 526       // the static inst executed in the Checker.  Sometimes the number
 527       // of saved results differs between the dyninst and static inst, but
 528       // this is ok and not a bug.  May be worthwhile to try and correct this.
 529
 530     if (result_mismatch) {
 531         warn("%lli: Instruction results do not match! (Values may not "
 532              "actually be integers) Inst: %#x, checker: %#x",
 533              curTick(), inst_val, checker_val);
 534
 535         // It's useful to verify load values from memory, but in MP
 536         // systems the value obtained at execute may be different than
 537         // the value obtained at completion.  Similarly DMA can
 538         // present the same problem on even UP systems.  Thus there is
 539         // the option to only warn on loads having a result error.
 540         // The load/store queue in Detailed CPU can also cause problems
 541         // if load/store forwarding is allowed.
 542         if (inst->isLoad() && warnOnlyOnLoadError) {
 543             copyResult(inst, inst_val, idx);
 544         } else {
 545             handleError(inst);
 546         }
 547     }
 548
 549     if (inst->nextInstAddr() != thread->nextInstAddr()) {
 550         warn("%lli: Instruction next PCs do not match! Inst: %#x, "
 551              "checker: %#x",
 552              curTick(), inst->nextInstAddr(), thread->nextInstAddr());
 553         handleError(inst);
 554     }
 555
 556     // Checking side effect registers can be difficult if they are not
 557     // checked simultaneously with the execution of the instruction.
 558     // This is because other valid instructions may have modified
 559     // these registers in the meantime, and their values are not
 560     // stored within the DynInst.
 561     while (!miscRegIdxs.empty()) {
 562         int misc_reg_idx = miscRegIdxs.front();
 563         miscRegIdxs.pop();
 564
 565         if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
 566             thread->readMiscRegNoEffect(misc_reg_idx)) {
 567             warn("%lli: Misc reg idx %i (side effect) does not match! "
 568                  "Inst: %#x, checker: %#x",
 569                  curTick(), misc_reg_idx,
 570                  inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
 571                  thread->readMiscRegNoEffect(misc_reg_idx));
 572             handleError(inst);
 573         }
 574     }
 575 }
 576
 577
 578 // This function is weird, if it is called it means the Checker and
 579 // O3 have diverged, so panic is called for now.  It may be useful
 580 // to resynch states and continue if the divergence is a false positive
 581 template <class Impl>
 582 void
 583 Checker<Impl>::validateState()
 584 {
 585     if (updateThisCycle) {
 586         // Change this back to warn if divergences end up being false positives
 587         panic("%lli: Instruction PC %#x results didn't match up, copying all "
 588              "registers from main CPU", curTick(), unverifiedInst->instAddr());
 589
 590         // Terribly convoluted way to make sure O3 model does not implode
 591         bool inSyscall = unverifiedInst->thread->inSyscall;
 592         unverifiedInst->thread->inSyscall = true;
 593
 594         // Heavy-weight copying of all registers
 595         thread->copyArchRegs(unverifiedInst->tcBase());
 596         unverifiedInst->thread->inSyscall = inSyscall;
 597
 598         // Set curStaticInst to unverifiedInst->staticInst
 599         curStaticInst = unverifiedInst->staticInst;
 600         // Also advance the PC.  Hopefully no PC-based events happened.
 601         advancePC(NoFault);
 602         updateThisCycle = false;
 603     }
 604 }
 605
 606 template <class Impl>
 607 void
 608 Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
 609                           int start_idx)
 610 {
 611     // We've already popped one dest off the queue,
 612     // so do the fix-up then start with the next dest reg;
 613     if (start_idx >= 0) {
 614         RegIndex idx = inst->destRegIdx(start_idx);
 615         if (idx < TheISA::FP_Base_DepTag) {
 616             thread->setIntReg(idx, mismatch_val);
 617         } else if (idx < TheISA::Ctrl_Base_DepTag) {
 618             thread->setFloatRegBits(idx, mismatch_val);
 619         } else if (idx < TheISA::Max_DepTag) {
 620             thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag,
 621                                mismatch_val);
 622         }
 623     }
 624     start_idx++;
 625     uint64_t res = 0;
 626     for (int i = start_idx; i < inst->numDestRegs(); i++) {
 627         RegIndex idx = inst->destRegIdx(i);
 628         inst->template popResult<uint64_t>(res);
 629         if (idx < TheISA::FP_Base_DepTag) {
 630             thread->setIntReg(idx, res);
 631         } else if (idx < TheISA::Ctrl_Base_DepTag) {
 632             thread->setFloatRegBits(idx, res);
 633         } else if (idx < TheISA::Max_DepTag) {
 634             // Try to get the proper misc register index for ARM here...
 635             thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, res);
 636         } // else Register is out of range...
 637     }
 638 }
 639
 640 template <class Impl>
 641 void
 642 Checker<Impl>::dumpAndExit(DynInstPtr &inst)
 643 {
 644     cprintf("Error detected, instruction information:\n");
 645     cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
 646             "Completed:%i\n",
 647             inst->pcState(),
 648             inst->nextInstAddr(),
 649             inst->seqNum,
 650             inst->threadNumber,
 651             inst->isCompleted());
 652     inst->dump();
 653     CheckerCPU::dumpAndExit();
 654 }
 655
 656 template <class Impl>
 657 void
 658 Checker<Impl>::dumpInsts()
 659 {
 660     int num = 0;
 661
 662     InstListIt inst_list_it = --(instList.end());
 663
 664     cprintf("Inst list size: %i\n", instList.size());
 665
 666     while (inst_list_it != instList.end())
 667     {
 668         cprintf("Instruction:%i\n",
 669                 num);
 670
 671         cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
 672                 "Completed:%i\n",
 673                 (*inst_list_it)->pcState(),
 674                 (*inst_list_it)->seqNum,
 675                 (*inst_list_it)->threadNumber,
 676                 (*inst_list_it)->isCompleted());
 677
 678         cprintf("\n");
 679
 680         inst_list_it--;
 681         ++num;
 682     }
 683
 684 }