src/cpu/checker/cpu_impl.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  *          Geoffrey Blake
  43  */
  44
  45 #ifndef __CPU_CHECKER_CPU_IMPL_HH__
  46 #define __CPU_CHECKER_CPU_IMPL_HH__
  47
  48 #include <list>
  49 #include <string>
  50
  51 #include "arch/isa_traits.hh"
  52 #include "arch/vtophys.hh"
  53 #include "base/refcnt.hh"
  54 #include "config/the_isa.hh"
  55 #include "cpu/base_dyn_inst.hh"
  56 #include "cpu/exetrace.hh"
  57 #include "cpu/reg_class.hh"
  58 #include "cpu/simple_thread.hh"
  59 #include "cpu/static_inst.hh"
  60 #include "cpu/thread_context.hh"
  61 #include "cpu/checker/cpu.hh"
  62 #include "debug/Checker.hh"
  63 #include "sim/full_system.hh"
  64 #include "sim/sim_object.hh"
  65 #include "sim/stats.hh"
  66
  67 using namespace std;
  68 using namespace TheISA;
  69
  70 template <class Impl>
  71 void
  72 Checker<Impl>::advancePC(Fault fault)
  73 {
  74     if (fault != NoFault) {
  75         curMacroStaticInst = StaticInst::nullStaticInstPtr;
  76         fault->invoke(tc, curStaticInst);
  77         thread->decoder.reset();
  78     } else {
  79         if (curStaticInst) {
  80             if (curStaticInst->isLastMicroop())
  81                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
  82             TheISA::PCState pcState = thread->pcState();
  83             TheISA::advancePC(pcState, curStaticInst);
  84             thread->pcState(pcState);
  85             DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
  86         }
  87     }
  88 }
  89 //////////////////////////////////////////////////
  90
  91 template <class Impl>
  92 void
  93 Checker<Impl>::handlePendingInt()
  94 {
  95     DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
  96                      thread->pcState(), instList.size());
  97     DynInstPtr boundaryInst = NULL;
  98     if (!instList.empty()) {
  99         // Set the instructions as completed and verify as much as possible.
 100         DynInstPtr inst;
 101         typename std::list<DynInstPtr>::iterator itr;
 102
 103         for (itr = instList.begin(); itr != instList.end(); itr++) {
 104             (*itr)->setCompleted();
 105         }
 106
 107         inst = instList.front();
 108         boundaryInst = instList.back();
 109         verify(inst); // verify the instructions
 110         inst = NULL;
 111     }
 112     if ((!boundaryInst && curMacroStaticInst &&
 113           curStaticInst->isDelayedCommit() &&
 114           !curStaticInst->isLastMicroop()) ||
 115         (boundaryInst && boundaryInst->isDelayedCommit() &&
 116          !boundaryInst->isLastMicroop())) {
 117         panic("%lli: Trying to take an interrupt in middle of "
 118               "a non-interuptable instruction!", curTick());
 119     }
 120     boundaryInst = NULL;
 121     thread->decoder.reset();
 122     curMacroStaticInst = StaticInst::nullStaticInstPtr;
 123 }
 124
 125 template <class Impl>
 126 void
 127 Checker<Impl>::verify(DynInstPtr &completed_inst)
 128 {
 129     DynInstPtr inst;
 130
 131     // Make sure serializing instructions are actually
 132     // seen as serializing to commit. instList should be
 133     // empty in these cases.
 134     if ((completed_inst->isSerializing() ||
 135         completed_inst->isSerializeBefore()) &&
 136         (!instList.empty() ?
 137          (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
 138         panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
 139               " entering instList with other instructions\n", curTick(),
 140               completed_inst->seqNum, completed_inst->pcState());
 141     }
 142
 143     // Either check this instruction, or add it to a list of
 144     // instructions waiting to be checked.  Instructions must be
 145     // checked in program order, so if a store has committed yet not
 146     // completed, there may be some instructions that are waiting
 147     // behind it that have completed and must be checked.
 148     if (!instList.empty()) {
 149         if (youngestSN < completed_inst->seqNum) {
 150             DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
 151                     completed_inst->seqNum, completed_inst->pcState());
 152             instList.push_back(completed_inst);
 153             youngestSN = completed_inst->seqNum;
 154         }
 155
 156         if (!instList.front()->isCompleted()) {
 157             return;
 158         } else {
 159             inst = instList.front();
 160             instList.pop_front();
 161         }
 162     } else {
 163         if (!completed_inst->isCompleted()) {
 164             if (youngestSN < completed_inst->seqNum) {
 165                 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
 166                         completed_inst->seqNum, completed_inst->pcState());
 167                 instList.push_back(completed_inst);
 168                 youngestSN = completed_inst->seqNum;
 169             }
 170             return;
 171         } else {
 172             if (youngestSN < completed_inst->seqNum) {
 173                 inst = completed_inst;
 174                 youngestSN = completed_inst->seqNum;
 175             } else {
 176                 return;
 177             }
 178         }
 179     }
 180
 181     // Make sure a serializing instruction is actually seen as
 182     // serializing. instList should be empty here
 183     if (inst->isSerializeAfter() && !instList.empty()) {
 184         panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
 185              " exiting instList with other instructions\n", curTick(),
 186              completed_inst->seqNum, completed_inst->pcState());
 187     }
 188     unverifiedInst = inst;
 189     inst = NULL;
 190
 191     // Try to check all instructions that are completed, ending if we
 192     // run out of instructions to check or if an instruction is not
 193     // yet completed.
 194     while (1) {
 195         DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
 196                 unverifiedInst->seqNum, unverifiedInst->pcState());
 197         unverifiedReq = NULL;
 198         unverifiedReq = unverifiedInst->reqToVerify;
 199         unverifiedMemData = unverifiedInst->memData;
 200         // Make sure results queue is empty
 201         while (!result.empty()) {
 202             result.pop();
 203         }
 204         numCycles++;
 205
 206         Fault fault = NoFault;
 207
 208         // maintain $r0 semantics
 209         thread->setIntReg(ZeroReg, 0);
 210 #if THE_ISA == ALPHA_ISA
 211         thread->setFloatReg(ZeroReg, 0.0);
 212 #endif
 213
 214         // Check if any recent PC changes match up with anything we
 215         // expect to happen.  This is mostly to check if traps or
 216         // PC-based events have occurred in both the checker and CPU.
 217         if (changedPC) {
 218             DPRINTF(Checker, "Changed PC recently to %s\n",
 219                     thread->pcState());
 220             if (willChangePC) {
 221                 if (newPCState == thread->pcState()) {
 222                     DPRINTF(Checker, "Changed PC matches expected PC\n");
 223                 } else {
 224                     warn("%lli: Changed PC does not match expected PC, "
 225                          "changed: %s, expected: %s",
 226                          curTick(), thread->pcState(), newPCState);
 227                     CheckerCPU::handleError();
 228                 }
 229                 willChangePC = false;
 230             }
 231             changedPC = false;
 232         }
 233         if (changedNextPC) {
 234             DPRINTF(Checker, "Changed NextPC recently to %#x\n",
 235                     thread->nextInstAddr());
 236             changedNextPC = false;
 237         }
 238
 239         // Try to fetch the instruction
 240         uint64_t fetchOffset = 0;
 241         bool fetchDone = false;
 242
 243         while (!fetchDone) {
 244             Addr fetch_PC = thread->instAddr();
 245             fetch_PC = (fetch_PC & PCMask) + fetchOffset;
 246
 247             MachInst machInst;
 248
 249             // If not in the middle of a macro instruction
 250             if (!curMacroStaticInst) {
 251                 // set up memory request for instruction fetch
 252                 memReq = new Request(unverifiedInst->threadNumber, fetch_PC,
 253                                      sizeof(MachInst),
 254                                      0,
 255                                      masterId,
 256                                      fetch_PC, thread->contextId(),
 257                                      unverifiedInst->threadNumber);
 258                 memReq->setVirt(0, fetch_PC, sizeof(MachInst),
 259                                 Request::INST_FETCH, masterId, thread->instAddr());
 260
 261
 262                 fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute);
 263
 264                 if (fault != NoFault) {
 265                     if (unverifiedInst->getFault() == NoFault) {
 266                         // In this case the instruction was not a dummy
 267                         // instruction carrying an ITB fault.  In the single
 268                         // threaded case the ITB should still be able to
 269                         // translate this instruction; in the SMT case it's
 270                         // possible that its ITB entry was kicked out.
 271                         warn("%lli: Instruction PC %s was not found in the "
 272                              "ITB!", curTick(), thread->pcState());
 273                         handleError(unverifiedInst);
 274
 275                         // go to the next instruction
 276                         advancePC(NoFault);
 277
 278                         // Give up on an ITB fault..
 279                         delete memReq;
 280                         unverifiedInst = NULL;
 281                         return;
 282                     } else {
 283                         // The instruction is carrying an ITB fault.  Handle
 284                         // the fault and see if our results match the CPU on
 285                         // the next tick().
 286                         fault = unverifiedInst->getFault();
 287                         delete memReq;
 288                         break;
 289                     }
 290                 } else {
 291                     PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq);
 292
 293                     pkt->dataStatic(&machInst);
 294                     icachePort->sendFunctional(pkt);
 295                     machInst = gtoh(machInst);
 296
 297                     delete memReq;
 298                     delete pkt;
 299                 }
 300             }
 301
 302             if (fault == NoFault) {
 303                 TheISA::PCState pcState = thread->pcState();
 304
 305                 if (isRomMicroPC(pcState.microPC())) {
 306                     fetchDone = true;
 307                     curStaticInst =
 308                         microcodeRom.fetchMicroop(pcState.microPC(), NULL);
 309                 } else if (!curMacroStaticInst) {
 310                     //We're not in the middle of a macro instruction
 311                     StaticInstPtr instPtr = NULL;
 312
 313                     //Predecode, ie bundle up an ExtMachInst
 314                     //If more fetch data is needed, pass it in.
 315                     Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
 316                     thread->decoder.moreBytes(pcState, fetchPC, machInst);
 317
 318                     //If an instruction is ready, decode it.
 319                     //Otherwise, we'll have to fetch beyond the
 320                     //MachInst at the current pc.
 321                     if (thread->decoder.instReady()) {
 322                         fetchDone = true;
 323                         instPtr = thread->decoder.decode(pcState);
 324                         thread->pcState(pcState);
 325                     } else {
 326                         fetchDone = false;
 327                         fetchOffset += sizeof(TheISA::MachInst);
 328                     }
 329
 330                     //If we decoded an instruction and it's microcoded,
 331                     //start pulling out micro ops
 332                     if (instPtr && instPtr->isMacroop()) {
 333                         curMacroStaticInst = instPtr;
 334                         curStaticInst =
 335                             instPtr->fetchMicroop(pcState.microPC());
 336                     } else {
 337                         curStaticInst = instPtr;
 338                     }
 339                 } else {
 340                     // Read the next micro op from the macro-op
 341                     curStaticInst =
 342                         curMacroStaticInst->fetchMicroop(pcState.microPC());
 343                     fetchDone = true;
 344                 }
 345             }
 346         }
 347         // reset decoder on Checker
 348         thread->decoder.reset();
 349
 350         // Check Checker and CPU get same instruction, and record
 351         // any faults the CPU may have had.
 352         Fault unverifiedFault;
 353         if (fault == NoFault) {
 354             unverifiedFault = unverifiedInst->getFault();
 355
 356             // Checks that the instruction matches what we expected it to be.
 357             // Checks both the machine instruction and the PC.
 358             validateInst(unverifiedInst);
 359         }
 360
 361         // keep an instruction count
 362         numInst++;
 363
 364
 365         // Either the instruction was a fault and we should process the fault,
 366         // or we should just go ahead execute the instruction.  This assumes
 367         // that the instruction is properly marked as a fault.
 368         if (fault == NoFault) {
 369             // Execute Checker instruction and trace
 370             if (!unverifiedInst->isUnverifiable()) {
 371                 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
 372                                                            tc,
 373                                                            curStaticInst,
 374                                                            pcState(),
 375                                                            curMacroStaticInst);
 376                 fault = curStaticInst->execute(this, traceData);
 377                 if (traceData) {
 378                     traceData->dump();
 379                     delete traceData;
 380                 }
 381             }
 382
 383             if (fault == NoFault && unverifiedFault == NoFault) {
 384                 thread->funcExeInst++;
 385                 // Checks to make sure instrution results are correct.
 386                 validateExecution(unverifiedInst);
 387
 388                 if (curStaticInst->isLoad()) {
 389                     ++numLoad;
 390                 }
 391             } else if (fault != NoFault && unverifiedFault == NoFault) {
 392                 panic("%lli: sn: %lli at PC: %s took a fault in checker "
 393                       "but not in driver CPU\n", curTick(),
 394                       unverifiedInst->seqNum, unverifiedInst->pcState());
 395             } else if (fault == NoFault && unverifiedFault != NoFault) {
 396                 panic("%lli: sn: %lli at PC: %s took a fault in driver "
 397                       "CPU but not in checker\n", curTick(),
 398                       unverifiedInst->seqNum, unverifiedInst->pcState());
 399             }
 400         }
 401
 402         // Take any faults here
 403         if (fault != NoFault) {
 404             if (FullSystem) {
 405                 fault->invoke(tc, curStaticInst);
 406                 willChangePC = true;
 407                 newPCState = thread->pcState();
 408                 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
 409                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
 410             }
 411         } else {
 412            advancePC(fault);
 413         }
 414
 415         if (FullSystem) {
 416             // @todo: Determine if these should happen only if the
 417             // instruction hasn't faulted.  In the SimpleCPU case this may
 418             // not be true, but in the O3 or Ozone case this may be true.
 419             Addr oldpc;
 420             int count = 0;
 421             do {
 422                 oldpc = thread->instAddr();
 423                 system->pcEventQueue.service(tc);
 424                 count++;
 425             } while (oldpc != thread->instAddr());
 426             if (count > 1) {
 427                 willChangePC = true;
 428                 newPCState = thread->pcState();
 429                 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
 430             }
 431         }
 432
 433         // @todo:  Optionally can check all registers. (Or just those
 434         // that have been modified).
 435         validateState();
 436
 437         // Continue verifying instructions if there's another completed
 438         // instruction waiting to be verified.
 439         if (instList.empty()) {
 440             break;
 441         } else if (instList.front()->isCompleted()) {
 442             unverifiedInst = NULL;
 443             unverifiedInst = instList.front();
 444             instList.pop_front();
 445         } else {
 446             break;
 447         }
 448     }
 449     unverifiedInst = NULL;
 450 }
 451
 452 template <class Impl>
 453 void
 454 Checker<Impl>::switchOut()
 455 {
 456     instList.clear();
 457 }
 458
 459 template <class Impl>
 460 void
 461 Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
 462 {
 463 }
 464
 465 template <class Impl>
 466 void
 467 Checker<Impl>::validateInst(DynInstPtr &inst)
 468 {
 469     if (inst->instAddr() != thread->instAddr()) {
 470         warn("%lli: PCs do not match! Inst: %s, checker: %s",
 471              curTick(), inst->pcState(), thread->pcState());
 472         if (changedPC) {
 473             warn("%lli: Changed PCs recently, may not be an error",
 474                  curTick());
 475         } else {
 476             handleError(inst);
 477         }
 478     }
 479
 480     if (curStaticInst != inst->staticInst) {
 481         warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
 482                 curStaticInst->getName(), inst->staticInst->getName());
 483     }
 484 }
 485
 486 template <class Impl>
 487 void
 488 Checker<Impl>::validateExecution(DynInstPtr &inst)
 489 {
 490     uint64_t checker_val;
 491     uint64_t inst_val;
 492     int idx = -1;
 493     bool result_mismatch = false;
 494
 495     if (inst->isUnverifiable()) {
 496         // Unverifiable instructions assume they were executed
 497         // properly by the CPU. Grab the result from the
 498         // instruction and write it to the register.
 499         copyResult(inst, 0, idx);
 500     } else if (inst->numDestRegs() > 0 && !result.empty()) {
 501         DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
 502                          inst->numDestRegs(), result.size());
 503         for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
 504             result.front().get(checker_val);
 505             result.pop();
 506             inst_val = 0;
 507             inst->template popResult<uint64_t>(inst_val);
 508             if (checker_val != inst_val) {
 509                 result_mismatch = true;
 510                 idx = i;
 511                 break;
 512             }
 513         }
 514     } // Checker CPU checks all the saved results in the dyninst passed by
 515       // the cpu model being checked against the saved results present in
 516       // the static inst executed in the Checker.  Sometimes the number
 517       // of saved results differs between the dyninst and static inst, but
 518       // this is ok and not a bug.  May be worthwhile to try and correct this.
 519
 520     if (result_mismatch) {
 521         warn("%lli: Instruction results do not match! (Values may not "
 522              "actually be integers) Inst: %#x, checker: %#x",
 523              curTick(), inst_val, checker_val);
 524
 525         // It's useful to verify load values from memory, but in MP
 526         // systems the value obtained at execute may be different than
 527         // the value obtained at completion.  Similarly DMA can
 528         // present the same problem on even UP systems.  Thus there is
 529         // the option to only warn on loads having a result error.
 530         // The load/store queue in Detailed CPU can also cause problems
 531         // if load/store forwarding is allowed.
 532         if (inst->isLoad() && warnOnlyOnLoadError) {
 533             copyResult(inst, inst_val, idx);
 534         } else {
 535             handleError(inst);
 536         }
 537     }
 538
 539     if (inst->nextInstAddr() != thread->nextInstAddr()) {
 540         warn("%lli: Instruction next PCs do not match! Inst: %#x, "
 541              "checker: %#x",
 542              curTick(), inst->nextInstAddr(), thread->nextInstAddr());
 543         handleError(inst);
 544     }
 545
 546     // Checking side effect registers can be difficult if they are not
 547     // checked simultaneously with the execution of the instruction.
 548     // This is because other valid instructions may have modified
 549     // these registers in the meantime, and their values are not
 550     // stored within the DynInst.
 551     while (!miscRegIdxs.empty()) {
 552         int misc_reg_idx = miscRegIdxs.front();
 553         miscRegIdxs.pop();
 554
 555         if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
 556             thread->readMiscRegNoEffect(misc_reg_idx)) {
 557             warn("%lli: Misc reg idx %i (side effect) does not match! "
 558                  "Inst: %#x, checker: %#x",
 559                  curTick(), misc_reg_idx,
 560                  inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
 561                  thread->readMiscRegNoEffect(misc_reg_idx));
 562             handleError(inst);
 563         }
 564     }
 565 }
 566
 567
 568 // This function is weird, if it is called it means the Checker and
 569 // O3 have diverged, so panic is called for now.  It may be useful
 570 // to resynch states and continue if the divergence is a false positive
 571 template <class Impl>
 572 void
 573 Checker<Impl>::validateState()
 574 {
 575     if (updateThisCycle) {
 576         // Change this back to warn if divergences end up being false positives
 577         panic("%lli: Instruction PC %#x results didn't match up, copying all "
 578              "registers from main CPU", curTick(), unverifiedInst->instAddr());
 579
 580         // Terribly convoluted way to make sure O3 model does not implode
 581         bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
 582         unverifiedInst->thread->noSquashFromTC = true;
 583
 584         // Heavy-weight copying of all registers
 585         thread->copyArchRegs(unverifiedInst->tcBase());
 586         unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
 587
 588         // Set curStaticInst to unverifiedInst->staticInst
 589         curStaticInst = unverifiedInst->staticInst;
 590         // Also advance the PC.  Hopefully no PC-based events happened.
 591         advancePC(NoFault);
 592         updateThisCycle = false;
 593     }
 594 }
 595
 596 template <class Impl>
 597 void
 598 Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
 599                           int start_idx)
 600 {
 601     // We've already popped one dest off the queue,
 602     // so do the fix-up then start with the next dest reg;
 603     if (start_idx >= 0) {
 604         RegIndex idx = inst->destRegIdx(start_idx);
 605         switch (regIdxToClass(idx)) {
 606           case IntRegClass:
 607             thread->setIntReg(idx, mismatch_val);
 608             break;
 609           case FloatRegClass:
 610             thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, mismatch_val);
 611             break;
 612           case CCRegClass:
 613             thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val);
 614             break;
 615           case MiscRegClass:
 616             thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
 617                                mismatch_val);
 618             break;
 619         }
 620     }
 621     start_idx++;
 622     uint64_t res = 0;
 623     for (int i = start_idx; i < inst->numDestRegs(); i++) {
 624         RegIndex idx = inst->destRegIdx(i);
 625         inst->template popResult<uint64_t>(res);
 626         switch (regIdxToClass(idx)) {
 627           case IntRegClass:
 628             thread->setIntReg(idx, res);
 629             break;
 630           case FloatRegClass:
 631             thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res);
 632             break;
 633           case CCRegClass:
 634             thread->setCCReg(idx - TheISA::CC_Reg_Base, res);
 635             break;
 636           case MiscRegClass:
 637             // Try to get the proper misc register index for ARM here...
 638             thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
 639             break;
 640             // else Register is out of range...
 641         }
 642     }
 643 }
 644
 645 template <class Impl>
 646 void
 647 Checker<Impl>::dumpAndExit(DynInstPtr &inst)
 648 {
 649     cprintf("Error detected, instruction information:\n");
 650     cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
 651             "Completed:%i\n",
 652             inst->pcState(),
 653             inst->nextInstAddr(),
 654             inst->seqNum,
 655             inst->threadNumber,
 656             inst->isCompleted());
 657     inst->dump();
 658     CheckerCPU::dumpAndExit();
 659 }
 660
 661 template <class Impl>
 662 void
 663 Checker<Impl>::dumpInsts()
 664 {
 665     int num = 0;
 666
 667     InstListIt inst_list_it = --(instList.end());
 668
 669     cprintf("Inst list size: %i\n", instList.size());
 670
 671     while (inst_list_it != instList.end())
 672     {
 673         cprintf("Instruction:%i\n",
 674                 num);
 675
 676         cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
 677                 "Completed:%i\n",
 678                 (*inst_list_it)->pcState(),
 679                 (*inst_list_it)->seqNum,
 680                 (*inst_list_it)->threadNumber,
 681                 (*inst_list_it)->isCompleted());
 682
 683         cprintf("\n");
 684
 685         inst_list_it--;
 686         ++num;
 687     }
 688
 689 }
 690
 691 #endif//__CPU_CHECKER_CPU_IMPL_HH__