src/cpu/checker/cpu_impl.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Geoffrey Blake
  42  */
  43
  44 #include <list>
  45 #include <string>
  46
  47 #include "arch/isa_traits.hh"
  48 #include "arch/vtophys.hh"
  49 #include "base/refcnt.hh"
  50 #include "config/the_isa.hh"
  51 #include "cpu/base_dyn_inst.hh"
  52 #include "cpu/exetrace.hh"
  53 #include "cpu/simple_thread.hh"
  54 #include "cpu/static_inst.hh"
  55 #include "cpu/thread_context.hh"
  56 #include "cpu/checker/cpu.hh"
  57 #include "debug/Checker.hh"
  58 #include "sim/full_system.hh"
  59 #include "sim/sim_object.hh"
  60 #include "sim/stats.hh"
  61
  62 using namespace std;
  63 using namespace TheISA;
  64
  65 template <class Impl>
  66 void
  67 Checker<Impl>::advancePC(Fault fault)
  68 {
  69     if (fault != NoFault) {
  70         curMacroStaticInst = StaticInst::nullStaticInstPtr;
  71         fault->invoke(tc, curStaticInst);
  72         thread->decoder.reset();
  73     } else {
  74         if (curStaticInst) {
  75             if (curStaticInst->isLastMicroop())
  76                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
  77             TheISA::PCState pcState = thread->pcState();
  78             TheISA::advancePC(pcState, curStaticInst);
  79             thread->pcState(pcState);
  80             DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
  81         }
  82     }
  83 }
  84 //////////////////////////////////////////////////
  85
  86 template <class Impl>
  87 void
  88 Checker<Impl>::handlePendingInt()
  89 {
  90     DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
  91                      thread->pcState(), instList.size());
  92     DynInstPtr boundaryInst = NULL;
  93     if (!instList.empty()) {
  94         // Set the instructions as completed and verify as much as possible.
  95         DynInstPtr inst;
  96         typename std::list<DynInstPtr>::iterator itr;
  97
  98         for (itr = instList.begin(); itr != instList.end(); itr++) {
  99             (*itr)->setCompleted();
 100         }
 101
 102         inst = instList.front();
 103         boundaryInst = instList.back();
 104         verify(inst); // verify the instructions
 105         inst = NULL;
 106     }
 107     if ((!boundaryInst && curMacroStaticInst &&
 108           curStaticInst->isDelayedCommit() &&
 109           !curStaticInst->isLastMicroop()) ||
 110         (boundaryInst && boundaryInst->isDelayedCommit() &&
 111          !boundaryInst->isLastMicroop())) {
 112         panic("%lli: Trying to take an interrupt in middle of "
 113               "a non-interuptable instruction!", curTick());
 114     }
 115     boundaryInst = NULL;
 116     thread->decoder.reset();
 117     curMacroStaticInst = StaticInst::nullStaticInstPtr;
 118 }
 119
 120 template <class Impl>
 121 void
 122 Checker<Impl>::verify(DynInstPtr &completed_inst)
 123 {
 124     DynInstPtr inst;
 125
 126     // Make sure serializing instructions are actually
 127     // seen as serializing to commit. instList should be
 128     // empty in these cases.
 129     if ((completed_inst->isSerializing() ||
 130         completed_inst->isSerializeBefore()) &&
 131         (!instList.empty() ?
 132          (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
 133         panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
 134               " entering instList with other instructions\n", curTick(),
 135               completed_inst->seqNum, completed_inst->pcState());
 136     }
 137
 138     // Either check this instruction, or add it to a list of
 139     // instructions waiting to be checked.  Instructions must be
 140     // checked in program order, so if a store has committed yet not
 141     // completed, there may be some instructions that are waiting
 142     // behind it that have completed and must be checked.
 143     if (!instList.empty()) {
 144         if (youngestSN < completed_inst->seqNum) {
 145             DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
 146                     completed_inst->seqNum, completed_inst->pcState());
 147             instList.push_back(completed_inst);
 148             youngestSN = completed_inst->seqNum;
 149         }
 150
 151         if (!instList.front()->isCompleted()) {
 152             return;
 153         } else {
 154             inst = instList.front();
 155             instList.pop_front();
 156         }
 157     } else {
 158         if (!completed_inst->isCompleted()) {
 159             if (youngestSN < completed_inst->seqNum) {
 160                 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
 161                         completed_inst->seqNum, completed_inst->pcState());
 162                 instList.push_back(completed_inst);
 163                 youngestSN = completed_inst->seqNum;
 164             }
 165             return;
 166         } else {
 167             if (youngestSN < completed_inst->seqNum) {
 168                 inst = completed_inst;
 169                 youngestSN = completed_inst->seqNum;
 170             } else {
 171                 return;
 172             }
 173         }
 174     }
 175
 176     // Make sure a serializing instruction is actually seen as
 177     // serializing. instList should be empty here
 178     if (inst->isSerializeAfter() && !instList.empty()) {
 179         panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
 180              " exiting instList with other instructions\n", curTick(),
 181              completed_inst->seqNum, completed_inst->pcState());
 182     }
 183     unverifiedInst = inst;
 184     inst = NULL;
 185
 186     // Try to check all instructions that are completed, ending if we
 187     // run out of instructions to check or if an instruction is not
 188     // yet completed.
 189     while (1) {
 190         DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
 191                 unverifiedInst->seqNum, unverifiedInst->pcState());
 192         unverifiedReq = NULL;
 193         unverifiedReq = unverifiedInst->reqToVerify;
 194         unverifiedMemData = unverifiedInst->memData;
 195         // Make sure results queue is empty
 196         while (!result.empty()) {
 197             result.pop();
 198         }
 199         numCycles++;
 200
 201         Fault fault = NoFault;
 202
 203         // maintain $r0 semantics
 204         thread->setIntReg(ZeroReg, 0);
 205 #if THE_ISA == ALPHA_ISA
 206         thread->setFloatReg(ZeroReg, 0.0);
 207 #endif
 208
 209         // Check if any recent PC changes match up with anything we
 210         // expect to happen.  This is mostly to check if traps or
 211         // PC-based events have occurred in both the checker and CPU.
 212         if (changedPC) {
 213             DPRINTF(Checker, "Changed PC recently to %s\n",
 214                     thread->pcState());
 215             if (willChangePC) {
 216                 if (newPCState == thread->pcState()) {
 217                     DPRINTF(Checker, "Changed PC matches expected PC\n");
 218                 } else {
 219                     warn("%lli: Changed PC does not match expected PC, "
 220                          "changed: %s, expected: %s",
 221                          curTick(), thread->pcState(), newPCState);
 222                     CheckerCPU::handleError();
 223                 }
 224                 willChangePC = false;
 225             }
 226             changedPC = false;
 227         }
 228         if (changedNextPC) {
 229             DPRINTF(Checker, "Changed NextPC recently to %#x\n",
 230                     thread->nextInstAddr());
 231             changedNextPC = false;
 232         }
 233
 234         // Try to fetch the instruction
 235         uint64_t fetchOffset = 0;
 236         bool fetchDone = false;
 237
 238         while (!fetchDone) {
 239             Addr fetch_PC = thread->instAddr();
 240             fetch_PC = (fetch_PC & PCMask) + fetchOffset;
 241
 242             MachInst machInst;
 243
 244             // If not in the middle of a macro instruction
 245             if (!curMacroStaticInst) {
 246                 // set up memory request for instruction fetch
 247                 memReq = new Request(unverifiedInst->threadNumber, fetch_PC,
 248                                      sizeof(MachInst),
 249                                      0,
 250                                      masterId,
 251                                      fetch_PC, thread->contextId(),
 252                                      unverifiedInst->threadNumber);
 253                 memReq->setVirt(0, fetch_PC, sizeof(MachInst),
 254                                 Request::INST_FETCH, masterId, thread->instAddr());
 255
 256
 257                 fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute);
 258
 259                 if (fault != NoFault) {
 260                     if (unverifiedInst->getFault() == NoFault) {
 261                         // In this case the instruction was not a dummy
 262                         // instruction carrying an ITB fault.  In the single
 263                         // threaded case the ITB should still be able to
 264                         // translate this instruction; in the SMT case it's
 265                         // possible that its ITB entry was kicked out.
 266                         warn("%lli: Instruction PC %s was not found in the "
 267                              "ITB!", curTick(), thread->pcState());
 268                         handleError(unverifiedInst);
 269
 270                         // go to the next instruction
 271                         advancePC(NoFault);
 272
 273                         // Give up on an ITB fault..
 274                         delete memReq;
 275                         unverifiedInst = NULL;
 276                         return;
 277                     } else {
 278                         // The instruction is carrying an ITB fault.  Handle
 279                         // the fault and see if our results match the CPU on
 280                         // the next tick().
 281                         fault = unverifiedInst->getFault();
 282                         delete memReq;
 283                         break;
 284                     }
 285                 } else {
 286                     PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq);
 287
 288                     pkt->dataStatic(&machInst);
 289                     icachePort->sendFunctional(pkt);
 290                     machInst = gtoh(machInst);
 291
 292                     delete memReq;
 293                     delete pkt;
 294                 }
 295             }
 296
 297             if (fault == NoFault) {
 298                 TheISA::PCState pcState = thread->pcState();
 299
 300                 if (isRomMicroPC(pcState.microPC())) {
 301                     fetchDone = true;
 302                     curStaticInst =
 303                         microcodeRom.fetchMicroop(pcState.microPC(), NULL);
 304                 } else if (!curMacroStaticInst) {
 305                     //We're not in the middle of a macro instruction
 306                     StaticInstPtr instPtr = NULL;
 307
 308                     //Predecode, ie bundle up an ExtMachInst
 309                     thread->decoder.setTC(thread->getTC());
 310                     //If more fetch data is needed, pass it in.
 311                     Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
 312                     thread->decoder.moreBytes(pcState, fetchPC, machInst);
 313
 314                     //If an instruction is ready, decode it.
 315                     //Otherwise, we'll have to fetch beyond the
 316                     //MachInst at the current pc.
 317                     if (thread->decoder.instReady()) {
 318                         fetchDone = true;
 319                         instPtr = thread->decoder.decode(pcState);
 320                         thread->pcState(pcState);
 321                     } else {
 322                         fetchDone = false;
 323                         fetchOffset += sizeof(TheISA::MachInst);
 324                     }
 325
 326                     //If we decoded an instruction and it's microcoded,
 327                     //start pulling out micro ops
 328                     if (instPtr && instPtr->isMacroop()) {
 329                         curMacroStaticInst = instPtr;
 330                         curStaticInst =
 331                             instPtr->fetchMicroop(pcState.microPC());
 332                     } else {
 333                         curStaticInst = instPtr;
 334                     }
 335                 } else {
 336                     // Read the next micro op from the macro-op
 337                     curStaticInst =
 338                         curMacroStaticInst->fetchMicroop(pcState.microPC());
 339                     fetchDone = true;
 340                 }
 341             }
 342         }
 343         // reset decoder on Checker
 344         thread->decoder.reset();
 345
 346         // Check Checker and CPU get same instruction, and record
 347         // any faults the CPU may have had.
 348         Fault unverifiedFault;
 349         if (fault == NoFault) {
 350             unverifiedFault = unverifiedInst->getFault();
 351
 352             // Checks that the instruction matches what we expected it to be.
 353             // Checks both the machine instruction and the PC.
 354             validateInst(unverifiedInst);
 355         }
 356
 357         // keep an instruction count
 358         numInst++;
 359
 360
 361         // Either the instruction was a fault and we should process the fault,
 362         // or we should just go ahead execute the instruction.  This assumes
 363         // that the instruction is properly marked as a fault.
 364         if (fault == NoFault) {
 365             // Execute Checker instruction and trace
 366             if (!unverifiedInst->isUnverifiable()) {
 367                 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
 368                                                            tc,
 369                                                            curStaticInst,
 370                                                            pcState(),
 371                                                            curMacroStaticInst);
 372                 fault = curStaticInst->execute(this, traceData);
 373                 if (traceData) {
 374                     traceData->dump();
 375                     delete traceData;
 376                 }
 377             }
 378
 379             if (fault == NoFault && unverifiedFault == NoFault) {
 380                 thread->funcExeInst++;
 381                 // Checks to make sure instrution results are correct.
 382                 validateExecution(unverifiedInst);
 383
 384                 if (curStaticInst->isLoad()) {
 385                     ++numLoad;
 386                 }
 387             } else if (fault != NoFault && unverifiedFault == NoFault) {
 388                 panic("%lli: sn: %lli at PC: %s took a fault in checker "
 389                       "but not in driver CPU\n", curTick(),
 390                       unverifiedInst->seqNum, unverifiedInst->pcState());
 391             } else if (fault == NoFault && unverifiedFault != NoFault) {
 392                 panic("%lli: sn: %lli at PC: %s took a fault in driver "
 393                       "CPU but not in checker\n", curTick(),
 394                       unverifiedInst->seqNum, unverifiedInst->pcState());
 395             }
 396         }
 397
 398         // Take any faults here
 399         if (fault != NoFault) {
 400             if (FullSystem) {
 401                 fault->invoke(tc, curStaticInst);
 402                 willChangePC = true;
 403                 newPCState = thread->pcState();
 404                 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
 405                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
 406             }
 407         } else {
 408            advancePC(fault);
 409         }
 410
 411         if (FullSystem) {
 412             // @todo: Determine if these should happen only if the
 413             // instruction hasn't faulted.  In the SimpleCPU case this may
 414             // not be true, but in the O3 or Ozone case this may be true.
 415             Addr oldpc;
 416             int count = 0;
 417             do {
 418                 oldpc = thread->instAddr();
 419                 system->pcEventQueue.service(tc);
 420                 count++;
 421             } while (oldpc != thread->instAddr());
 422             if (count > 1) {
 423                 willChangePC = true;
 424                 newPCState = thread->pcState();
 425                 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
 426             }
 427         }
 428
 429         // @todo:  Optionally can check all registers. (Or just those
 430         // that have been modified).
 431         validateState();
 432
 433         // Continue verifying instructions if there's another completed
 434         // instruction waiting to be verified.
 435         if (instList.empty()) {
 436             break;
 437         } else if (instList.front()->isCompleted()) {
 438             unverifiedInst = NULL;
 439             unverifiedInst = instList.front();
 440             instList.pop_front();
 441         } else {
 442             break;
 443         }
 444     }
 445     unverifiedInst = NULL;
 446 }
 447
 448 template <class Impl>
 449 void
 450 Checker<Impl>::switchOut()
 451 {
 452     instList.clear();
 453 }
 454
 455 template <class Impl>
 456 void
 457 Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
 458 {
 459 }
 460
 461 template <class Impl>
 462 void
 463 Checker<Impl>::validateInst(DynInstPtr &inst)
 464 {
 465     if (inst->instAddr() != thread->instAddr()) {
 466         warn("%lli: PCs do not match! Inst: %s, checker: %s",
 467              curTick(), inst->pcState(), thread->pcState());
 468         if (changedPC) {
 469             warn("%lli: Changed PCs recently, may not be an error",
 470                  curTick());
 471         } else {
 472             handleError(inst);
 473         }
 474     }
 475
 476     if (curStaticInst != inst->staticInst) {
 477         warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
 478                 curStaticInst->getName(), inst->staticInst->getName());
 479     }
 480 }
 481
 482 template <class Impl>
 483 void
 484 Checker<Impl>::validateExecution(DynInstPtr &inst)
 485 {
 486     uint64_t checker_val;
 487     uint64_t inst_val;
 488     int idx = -1;
 489     bool result_mismatch = false;
 490
 491     if (inst->isUnverifiable()) {
 492         // Unverifiable instructions assume they were executed
 493         // properly by the CPU. Grab the result from the
 494         // instruction and write it to the register.
 495         copyResult(inst, 0, idx);
 496     } else if (inst->numDestRegs() > 0 && !result.empty()) {
 497         DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
 498                          inst->numDestRegs(), result.size());
 499         for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
 500             result.front().get(checker_val);
 501             result.pop();
 502             inst_val = 0;
 503             inst->template popResult<uint64_t>(inst_val);
 504             if (checker_val != inst_val) {
 505                 result_mismatch = true;
 506                 idx = i;
 507                 break;
 508             }
 509         }
 510     } // Checker CPU checks all the saved results in the dyninst passed by
 511       // the cpu model being checked against the saved results present in
 512       // the static inst executed in the Checker.  Sometimes the number
 513       // of saved results differs between the dyninst and static inst, but
 514       // this is ok and not a bug.  May be worthwhile to try and correct this.
 515
 516     if (result_mismatch) {
 517         warn("%lli: Instruction results do not match! (Values may not "
 518              "actually be integers) Inst: %#x, checker: %#x",
 519              curTick(), inst_val, checker_val);
 520
 521         // It's useful to verify load values from memory, but in MP
 522         // systems the value obtained at execute may be different than
 523         // the value obtained at completion.  Similarly DMA can
 524         // present the same problem on even UP systems.  Thus there is
 525         // the option to only warn on loads having a result error.
 526         // The load/store queue in Detailed CPU can also cause problems
 527         // if load/store forwarding is allowed.
 528         if (inst->isLoad() && warnOnlyOnLoadError) {
 529             copyResult(inst, inst_val, idx);
 530         } else {
 531             handleError(inst);
 532         }
 533     }
 534
 535     if (inst->nextInstAddr() != thread->nextInstAddr()) {
 536         warn("%lli: Instruction next PCs do not match! Inst: %#x, "
 537              "checker: %#x",
 538              curTick(), inst->nextInstAddr(), thread->nextInstAddr());
 539         handleError(inst);
 540     }
 541
 542     // Checking side effect registers can be difficult if they are not
 543     // checked simultaneously with the execution of the instruction.
 544     // This is because other valid instructions may have modified
 545     // these registers in the meantime, and their values are not
 546     // stored within the DynInst.
 547     while (!miscRegIdxs.empty()) {
 548         int misc_reg_idx = miscRegIdxs.front();
 549         miscRegIdxs.pop();
 550
 551         if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
 552             thread->readMiscRegNoEffect(misc_reg_idx)) {
 553             warn("%lli: Misc reg idx %i (side effect) does not match! "
 554                  "Inst: %#x, checker: %#x",
 555                  curTick(), misc_reg_idx,
 556                  inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
 557                  thread->readMiscRegNoEffect(misc_reg_idx));
 558             handleError(inst);
 559         }
 560     }
 561 }
 562
 563
 564 // This function is weird, if it is called it means the Checker and
 565 // O3 have diverged, so panic is called for now.  It may be useful
 566 // to resynch states and continue if the divergence is a false positive
 567 template <class Impl>
 568 void
 569 Checker<Impl>::validateState()
 570 {
 571     if (updateThisCycle) {
 572         // Change this back to warn if divergences end up being false positives
 573         panic("%lli: Instruction PC %#x results didn't match up, copying all "
 574              "registers from main CPU", curTick(), unverifiedInst->instAddr());
 575
 576         // Terribly convoluted way to make sure O3 model does not implode
 577         bool inSyscall = unverifiedInst->thread->inSyscall;
 578         unverifiedInst->thread->inSyscall = true;
 579
 580         // Heavy-weight copying of all registers
 581         thread->copyArchRegs(unverifiedInst->tcBase());
 582         unverifiedInst->thread->inSyscall = inSyscall;
 583
 584         // Set curStaticInst to unverifiedInst->staticInst
 585         curStaticInst = unverifiedInst->staticInst;
 586         // Also advance the PC.  Hopefully no PC-based events happened.
 587         advancePC(NoFault);
 588         updateThisCycle = false;
 589     }
 590 }
 591
 592 template <class Impl>
 593 void
 594 Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
 595                           int start_idx)
 596 {
 597     // We've already popped one dest off the queue,
 598     // so do the fix-up then start with the next dest reg;
 599     if (start_idx >= 0) {
 600         RegIndex idx = inst->destRegIdx(start_idx);
 601         if (idx < TheISA::FP_Base_DepTag) {
 602             thread->setIntReg(idx, mismatch_val);
 603         } else if (idx < TheISA::Ctrl_Base_DepTag) {
 604             thread->setFloatRegBits(idx, mismatch_val);
 605         } else if (idx < TheISA::Max_DepTag) {
 606             thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag,
 607                                mismatch_val);
 608         }
 609     }
 610     start_idx++;
 611     uint64_t res = 0;
 612     for (int i = start_idx; i < inst->numDestRegs(); i++) {
 613         RegIndex idx = inst->destRegIdx(i);
 614         inst->template popResult<uint64_t>(res);
 615         if (idx < TheISA::FP_Base_DepTag) {
 616             thread->setIntReg(idx, res);
 617         } else if (idx < TheISA::Ctrl_Base_DepTag) {
 618             thread->setFloatRegBits(idx, res);
 619         } else if (idx < TheISA::Max_DepTag) {
 620             // Try to get the proper misc register index for ARM here...
 621             thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, res);
 622         } // else Register is out of range...
 623     }
 624 }
 625
 626 template <class Impl>
 627 void
 628 Checker<Impl>::dumpAndExit(DynInstPtr &inst)
 629 {
 630     cprintf("Error detected, instruction information:\n");
 631     cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
 632             "Completed:%i\n",
 633             inst->pcState(),
 634             inst->nextInstAddr(),
 635             inst->seqNum,
 636             inst->threadNumber,
 637             inst->isCompleted());
 638     inst->dump();
 639     CheckerCPU::dumpAndExit();
 640 }
 641
 642 template <class Impl>
 643 void
 644 Checker<Impl>::dumpInsts()
 645 {
 646     int num = 0;
 647
 648     InstListIt inst_list_it = --(instList.end());
 649
 650     cprintf("Inst list size: %i\n", instList.size());
 651
 652     while (inst_list_it != instList.end())
 653     {
 654         cprintf("Instruction:%i\n",
 655                 num);
 656
 657         cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
 658                 "Completed:%i\n",
 659                 (*inst_list_it)->pcState(),
 660                 (*inst_list_it)->seqNum,
 661                 (*inst_list_it)->threadNumber,
 662                 (*inst_list_it)->isCompleted());
 663
 664         cprintf("\n");
 665
 666         inst_list_it--;
 667         ++num;
 668     }
 669
 670 }