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34 #include "base/refcnt.hh"
35 #include "cpu/base_dyn_inst.hh"
36 #include "cpu/checker/cpu.hh"
37 #include "cpu/simple_thread.hh"
38 #include "cpu/thread_context.hh"
39 #include "cpu/static_inst.hh"
40 #include "mem/packet_impl.hh"
41 #include "sim/byteswap.hh"
42 #include "sim/sim_object.hh"
43 #include "sim/stats.hh"
46 #include "arch/vtophys.hh"
50 //The CheckerCPU does alpha only
51 using namespace AlphaISA;
53 template <class DynInstPtr>
55 Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
59 // Either check this instruction, or add it to a list of
60 // instructions waiting to be checked. Instructions must be
61 // checked in program order, so if a store has committed yet not
62 // completed, there may be some instructions that are waiting
63 // behind it that have completed and must be checked.
64 if (!instList.empty()) {
65 if (youngestSN < completed_inst->seqNum) {
66 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
67 completed_inst->seqNum, completed_inst->readPC());
68 instList.push_back(completed_inst);
69 youngestSN = completed_inst->seqNum;
72 if (!instList.front()->isCompleted()) {
75 inst = instList.front();
79 if (!completed_inst->isCompleted()) {
80 if (youngestSN < completed_inst->seqNum) {
81 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
82 completed_inst->seqNum, completed_inst->readPC());
83 instList.push_back(completed_inst);
84 youngestSN = completed_inst->seqNum;
88 if (youngestSN < completed_inst->seqNum) {
89 inst = completed_inst;
90 youngestSN = completed_inst->seqNum;
97 // Try to check all instructions that are completed, ending if we
98 // run out of instructions to check or if an instruction is not
101 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
102 inst->seqNum, inst->readPC());
103 unverifiedResult.integer = inst->readIntResult();
104 unverifiedReq = inst->req;
105 unverifiedMemData = inst->memData;
108 Fault fault = NoFault;
110 // maintain $r0 semantics
111 thread->setIntReg(ZeroReg, 0);
113 thread->setFloatRegDouble(ZeroReg, 0.0);
114 #endif // TARGET_ALPHA
116 // Check if any recent PC changes match up with anything we
117 // expect to happen. This is mostly to check if traps or
118 // PC-based events have occurred in both the checker and CPU.
120 DPRINTF(Checker, "Changed PC recently to %#x\n",
123 if (newPC == thread->readPC()) {
124 DPRINTF(Checker, "Changed PC matches expected PC\n");
126 warn("%lli: Changed PC does not match expected PC, "
127 "changed: %#x, expected: %#x",
128 curTick, thread->readPC(), newPC);
129 CheckerCPU::handleError();
131 willChangePC = false;
136 DPRINTF(Checker, "Changed NextPC recently to %#x\n",
137 thread->readNextPC());
138 changedNextPC = false;
141 // Try to fetch the instruction
144 #define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
146 #define IFETCH_FLAGS(pc) 0
149 uint64_t fetch_PC = thread->readPC() & ~3;
151 // set up memory request for instruction fetch
152 memReq = new Request(inst->threadNumber, fetch_PC,
154 IFETCH_FLAGS(thread->readPC()),
155 fetch_PC, thread->readCpuId(), inst->threadNumber);
157 bool succeeded = translateInstReq(memReq);
160 if (inst->getFault() == NoFault) {
161 // In this case the instruction was not a dummy
162 // instruction carrying an ITB fault. In the single
163 // threaded case the ITB should still be able to
164 // translate this instruction; in the SMT case it's
165 // possible that its ITB entry was kicked out.
166 warn("%lli: Instruction PC %#x was not found in the ITB!",
167 curTick, thread->readPC());
170 // go to the next instruction
171 thread->setPC(thread->readNextPC());
172 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
176 // The instruction is carrying an ITB fault. Handle
177 // the fault and see if our results match the CPU on
179 fault = inst->getFault();
183 if (fault == NoFault) {
184 Packet *pkt = new Packet(memReq, Packet::ReadReq,
187 pkt->dataStatic(&machInst);
189 icachePort->sendFunctional(pkt);
193 // keep an instruction count
196 // decode the instruction
197 machInst = gtoh(machInst);
198 // Checks that the instruction matches what we expected it to be.
199 // Checks both the machine instruction and the PC.
202 curStaticInst = StaticInst::decode(makeExtMI(machInst,
206 thread->setInst(machInst);
207 #endif // FULL_SYSTEM
209 fault = inst->getFault();
212 // Discard fetch's memReq.
216 // Either the instruction was a fault and we should process the fault,
217 // or we should just go ahead execute the instruction. This assumes
218 // that the instruction is properly marked as a fault.
219 if (fault == NoFault) {
221 thread->funcExeInst++;
223 fault = curStaticInst->execute(this, NULL);
225 // Checks to make sure instrution results are correct.
226 validateExecution(inst);
228 if (curStaticInst->isLoad()) {
233 if (fault != NoFault) {
237 newPC = thread->readPC();
238 DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
241 #if THE_ISA != MIPS_ISA
242 // go to the next instruction
243 thread->setPC(thread->readNextPC());
244 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
246 // go to the next instruction
247 thread->setPC(thread->readNextPC());
248 thread->setNextPC(thread->readNextNPC());
249 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
255 // @todo: Determine if these should happen only if the
256 // instruction hasn't faulted. In the SimpleCPU case this may
257 // not be true, but in the O3 or Ozone case this may be true.
261 oldpc = thread->readPC();
262 system->pcEventQueue.service(tc);
264 } while (oldpc != thread->readPC());
267 newPC = thread->readPC();
268 DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
272 // @todo: Optionally can check all registers. (Or just those
273 // that have been modified).
281 // Continue verifying instructions if there's another completed
282 // instruction waiting to be verified.
283 if (instList.empty()) {
285 } else if (instList.front()->isCompleted()) {
286 inst = instList.front();
287 instList.pop_front();
294 template <class DynInstPtr>
296 Checker<DynInstPtr>::switchOut(Sampler *s)
301 template <class DynInstPtr>
303 Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
307 template <class DynInstPtr>
309 Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
311 if (inst->readPC() != thread->readPC()) {
312 warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
313 curTick, inst->readPC(), thread->readPC());
315 warn("%lli: Changed PCs recently, may not be an error",
322 MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
324 if (mi != machInst) {
325 warn("%lli: Binary instructions do not match! Inst: %#x, "
327 curTick, mi, machInst);
332 template <class DynInstPtr>
334 Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
336 bool result_mismatch = false;
337 if (inst->numDestRegs()) {
338 // @todo: Support more destination registers.
339 if (inst->isUnverifiable()) {
340 // Unverifiable instructions assume they were executed
341 // properly by the CPU. Grab the result from the
342 // instruction and write it to the register.
344 } else if (result.integer != inst->readIntResult()) {
345 result_mismatch = true;
349 if (result_mismatch) {
350 warn("%lli: Instruction results do not match! (Values may not "
351 "actually be integers) Inst: %#x, checker: %#x",
352 curTick, inst->readIntResult(), result.integer);
354 // It's useful to verify load values from memory, but in MP
355 // systems the value obtained at execute may be different than
356 // the value obtained at completion. Similarly DMA can
357 // present the same problem on even UP systems. Thus there is
358 // the option to only warn on loads having a result error.
359 if (inst->isLoad() && warnOnlyOnLoadError) {
366 if (inst->readNextPC() != thread->readNextPC()) {
367 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
369 curTick, inst->readNextPC(), thread->readNextPC());
373 // Checking side effect registers can be difficult if they are not
374 // checked simultaneously with the execution of the instruction.
375 // This is because other valid instructions may have modified
376 // these registers in the meantime, and their values are not
377 // stored within the DynInst.
378 while (!miscRegIdxs.empty()) {
379 int misc_reg_idx = miscRegIdxs.front();
382 if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
383 thread->readMiscReg(misc_reg_idx)) {
384 warn("%lli: Misc reg idx %i (side effect) does not match! "
385 "Inst: %#x, checker: %#x",
386 curTick, misc_reg_idx,
387 inst->tcBase()->readMiscReg(misc_reg_idx),
388 thread->readMiscReg(misc_reg_idx));
394 template <class DynInstPtr>
396 Checker<DynInstPtr>::validateState()
400 template <class DynInstPtr>
402 Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
404 RegIndex idx = inst->destRegIdx(0);
405 if (idx < TheISA::FP_Base_DepTag) {
406 thread->setIntReg(idx, inst->readIntResult());
407 } else if (idx < TheISA::Fpcr_DepTag) {
408 thread->setFloatRegBits(idx, inst->readIntResult());
410 thread->setMiscReg(idx, inst->readIntResult());
414 template <class DynInstPtr>
416 Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
418 cprintf("Error detected, instruction information:\n");
419 cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
425 inst->isCompleted());
427 CheckerCPU::dumpAndExit();
430 template <class DynInstPtr>
432 Checker<DynInstPtr>::dumpInsts()
436 InstListIt inst_list_it = --(instList.end());
438 cprintf("Inst list size: %i\n", instList.size());
440 while (inst_list_it != instList.end())
442 cprintf("Instruction:%i\n",
445 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
447 (*inst_list_it)->readPC(),
448 (*inst_list_it)->seqNum,
449 (*inst_list_it)->threadNumber,
450 (*inst_list_it)->isCompleted());