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34 #include "base/refcnt.hh"
35 #include "config/the_isa.hh"
36 #include "cpu/base_dyn_inst.hh"
37 #include "cpu/checker/cpu.hh"
38 #include "cpu/simple_thread.hh"
39 #include "cpu/thread_context.hh"
40 #include "cpu/static_inst.hh"
41 #include "sim/sim_object.hh"
42 #include "sim/stats.hh"
45 #include "arch/vtophys.hh"
49 //The CheckerCPU does alpha only
50 using namespace AlphaISA;
52 template <class DynInstPtr>
54 Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
58 // Either check this instruction, or add it to a list of
59 // instructions waiting to be checked. Instructions must be
60 // checked in program order, so if a store has committed yet not
61 // completed, there may be some instructions that are waiting
62 // behind it that have completed and must be checked.
63 if (!instList.empty()) {
64 if (youngestSN < completed_inst->seqNum) {
65 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
66 completed_inst->seqNum, completed_inst->readPC());
67 instList.push_back(completed_inst);
68 youngestSN = completed_inst->seqNum;
71 if (!instList.front()->isCompleted()) {
74 inst = instList.front();
78 if (!completed_inst->isCompleted()) {
79 if (youngestSN < completed_inst->seqNum) {
80 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
81 completed_inst->seqNum, completed_inst->readPC());
82 instList.push_back(completed_inst);
83 youngestSN = completed_inst->seqNum;
87 if (youngestSN < completed_inst->seqNum) {
88 inst = completed_inst;
89 youngestSN = completed_inst->seqNum;
96 unverifiedInst = inst;
98 // Try to check all instructions that are completed, ending if we
99 // run out of instructions to check or if an instruction is not
102 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
103 inst->seqNum, inst->readPC());
104 unverifiedResult.integer = inst->readIntResult();
105 unverifiedReq = inst->req;
106 unverifiedMemData = inst->memData;
109 Fault fault = NoFault;
111 // maintain $r0 semantics
112 thread->setIntReg(ZeroReg, 0);
114 thread->setFloatRegDouble(ZeroReg, 0.0);
115 #endif // TARGET_ALPHA
117 // Check if any recent PC changes match up with anything we
118 // expect to happen. This is mostly to check if traps or
119 // PC-based events have occurred in both the checker and CPU.
121 DPRINTF(Checker, "Changed PC recently to %#x\n",
124 if (newPC == thread->readPC()) {
125 DPRINTF(Checker, "Changed PC matches expected PC\n");
127 warn("%lli: Changed PC does not match expected PC, "
128 "changed: %#x, expected: %#x",
129 curTick, thread->readPC(), newPC);
130 CheckerCPU::handleError();
132 willChangePC = false;
137 DPRINTF(Checker, "Changed NextPC recently to %#x\n",
138 thread->readNextPC());
139 changedNextPC = false;
142 // Try to fetch the instruction
145 #define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
147 #define IFETCH_FLAGS(pc) 0
150 uint64_t fetch_PC = thread->readPC() & ~3;
152 // set up memory request for instruction fetch
153 memReq = new Request(inst->threadNumber, fetch_PC,
155 IFETCH_FLAGS(thread->readPC()),
156 fetch_PC, thread->contextId(),
159 bool succeeded = itb->translateAtomic(memReq, thread);
162 if (inst->getFault() == NoFault) {
163 // In this case the instruction was not a dummy
164 // instruction carrying an ITB fault. In the single
165 // threaded case the ITB should still be able to
166 // translate this instruction; in the SMT case it's
167 // possible that its ITB entry was kicked out.
168 warn("%lli: Instruction PC %#x was not found in the ITB!",
169 curTick, thread->readPC());
172 // go to the next instruction
173 thread->setPC(thread->readNextPC());
174 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
178 // The instruction is carrying an ITB fault. Handle
179 // the fault and see if our results match the CPU on
181 fault = inst->getFault();
185 if (fault == NoFault) {
186 PacketPtr pkt = new Packet(memReq, Packet::ReadReq,
189 pkt->dataStatic(&machInst);
191 icachePort->sendFunctional(pkt);
195 // keep an instruction count
198 // decode the instruction
199 machInst = gtoh(machInst);
200 // Checks that the instruction matches what we expected it to be.
201 // Checks both the machine instruction and the PC.
204 #if THE_ISA == ALPHA_ISA
205 curStaticInst = StaticInst::decode(makeExtMI(machInst,
207 #elif THE_ISA == SPARC_ISA
208 curStaticInst = StaticInst::decode(makeExtMI(machInst,
213 thread->setInst(machInst);
214 #endif // FULL_SYSTEM
216 fault = inst->getFault();
219 // Discard fetch's memReq.
223 // Either the instruction was a fault and we should process the fault,
224 // or we should just go ahead execute the instruction. This assumes
225 // that the instruction is properly marked as a fault.
226 if (fault == NoFault) {
228 thread->funcExeInst++;
230 if (!inst->isUnverifiable())
231 fault = curStaticInst->execute(this, NULL);
233 // Checks to make sure instrution results are correct.
234 validateExecution(inst);
236 if (curStaticInst->isLoad()) {
241 if (fault != NoFault) {
245 newPC = thread->readPC();
246 DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
249 #if THE_ISA != MIPS_ISA
250 // go to the next instruction
251 thread->setPC(thread->readNextPC());
252 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
254 // go to the next instruction
255 thread->setPC(thread->readNextPC());
256 thread->setNextPC(thread->readNextNPC());
257 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
263 // @todo: Determine if these should happen only if the
264 // instruction hasn't faulted. In the SimpleCPU case this may
265 // not be true, but in the O3 or Ozone case this may be true.
269 oldpc = thread->readPC();
270 system->pcEventQueue.service(tc);
272 } while (oldpc != thread->readPC());
275 newPC = thread->readPC();
276 DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
280 // @todo: Optionally can check all registers. (Or just those
281 // that have been modified).
289 // Continue verifying instructions if there's another completed
290 // instruction waiting to be verified.
291 if (instList.empty()) {
293 } else if (instList.front()->isCompleted()) {
294 inst = instList.front();
295 instList.pop_front();
300 unverifiedInst = NULL;
303 template <class DynInstPtr>
305 Checker<DynInstPtr>::switchOut()
310 template <class DynInstPtr>
312 Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
316 template <class DynInstPtr>
318 Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
320 if (inst->readPC() != thread->readPC()) {
321 warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
322 curTick, inst->readPC(), thread->readPC());
324 warn("%lli: Changed PCs recently, may not be an error",
331 MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
333 if (mi != machInst) {
334 warn("%lli: Binary instructions do not match! Inst: %#x, "
336 curTick, mi, machInst);
341 template <class DynInstPtr>
343 Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
345 bool result_mismatch = false;
346 if (inst->numDestRegs()) {
347 // @todo: Support more destination registers.
348 if (inst->isUnverifiable()) {
349 // Unverifiable instructions assume they were executed
350 // properly by the CPU. Grab the result from the
351 // instruction and write it to the register.
353 } else if (result.integer != inst->readIntResult()) {
354 result_mismatch = true;
358 if (result_mismatch) {
359 warn("%lli: Instruction results do not match! (Values may not "
360 "actually be integers) Inst: %#x, checker: %#x",
361 curTick, inst->readIntResult(), result.integer);
363 // It's useful to verify load values from memory, but in MP
364 // systems the value obtained at execute may be different than
365 // the value obtained at completion. Similarly DMA can
366 // present the same problem on even UP systems. Thus there is
367 // the option to only warn on loads having a result error.
368 if (inst->isLoad() && warnOnlyOnLoadError) {
375 if (inst->readNextPC() != thread->readNextPC()) {
376 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
378 curTick, inst->readNextPC(), thread->readNextPC());
382 // Checking side effect registers can be difficult if they are not
383 // checked simultaneously with the execution of the instruction.
384 // This is because other valid instructions may have modified
385 // these registers in the meantime, and their values are not
386 // stored within the DynInst.
387 while (!miscRegIdxs.empty()) {
388 int misc_reg_idx = miscRegIdxs.front();
391 if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
392 thread->readMiscRegNoEffect(misc_reg_idx)) {
393 warn("%lli: Misc reg idx %i (side effect) does not match! "
394 "Inst: %#x, checker: %#x",
395 curTick, misc_reg_idx,
396 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
397 thread->readMiscRegNoEffect(misc_reg_idx));
403 template <class DynInstPtr>
405 Checker<DynInstPtr>::validateState()
407 if (updateThisCycle) {
408 warn("%lli: Instruction PC %#x results didn't match up, copying all "
409 "registers from main CPU", curTick, unverifiedInst->readPC());
410 // Heavy-weight copying of all registers
411 thread->copyArchRegs(unverifiedInst->tcBase());
412 // Also advance the PC. Hopefully no PC-based events happened.
413 #if THE_ISA != MIPS_ISA
414 // go to the next instruction
415 thread->setPC(thread->readNextPC());
416 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
418 // go to the next instruction
419 thread->setPC(thread->readNextPC());
420 thread->setNextPC(thread->readNextNPC());
421 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
423 updateThisCycle = false;
427 template <class DynInstPtr>
429 Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
431 RegIndex idx = inst->destRegIdx(0);
432 if (idx < TheISA::FP_Base_DepTag) {
433 thread->setIntReg(idx, inst->readIntResult());
434 } else if (idx < TheISA::Fpcr_DepTag) {
435 thread->setFloatRegBits(idx, inst->readIntResult());
437 thread->setMiscRegNoEffect(idx, inst->readIntResult());
441 template <class DynInstPtr>
443 Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
445 cprintf("Error detected, instruction information:\n");
446 cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
452 inst->isCompleted());
454 CheckerCPU::dumpAndExit();
457 template <class DynInstPtr>
459 Checker<DynInstPtr>::dumpInsts()
463 InstListIt inst_list_it = --(instList.end());
465 cprintf("Inst list size: %i\n", instList.size());
467 while (inst_list_it != instList.end())
469 cprintf("Instruction:%i\n",
472 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
474 (*inst_list_it)->readPC(),
475 (*inst_list_it)->seqNum,
476 (*inst_list_it)->threadNumber,
477 (*inst_list_it)->isCompleted());