src/cpu/checker/cpu_impl.hh

   1 /*
   2  * Copyright (c) 2011, 2016 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  *          Geoffrey Blake
  43  */
  44
  45 #ifndef __CPU_CHECKER_CPU_IMPL_HH__
  46 #define __CPU_CHECKER_CPU_IMPL_HH__
  47
  48 #include <list>
  49 #include <string>
  50
  51 #include "arch/isa_traits.hh"
  52 #include "arch/vtophys.hh"
  53 #include "base/refcnt.hh"
  54 #include "config/the_isa.hh"
  55 #include "cpu/base_dyn_inst.hh"
  56 #include "cpu/exetrace.hh"
  57 #include "cpu/reg_class.hh"
  58 #include "cpu/simple_thread.hh"
  59 #include "cpu/static_inst.hh"
  60 #include "cpu/thread_context.hh"
  61 #include "cpu/checker/cpu.hh"
  62 #include "debug/Checker.hh"
  63 #include "sim/full_system.hh"
  64 #include "sim/sim_object.hh"
  65 #include "sim/stats.hh"
  66
  67 using namespace std;
  68 using namespace TheISA;
  69
  70 template <class Impl>
  71 void
  72 Checker<Impl>::advancePC(const Fault &fault)
  73 {
  74     if (fault != NoFault) {
  75         curMacroStaticInst = StaticInst::nullStaticInstPtr;
  76         fault->invoke(tc, curStaticInst);
  77         thread->decoder.reset();
  78     } else {
  79         if (curStaticInst) {
  80             if (curStaticInst->isLastMicroop())
  81                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
  82             TheISA::PCState pcState = thread->pcState();
  83             TheISA::advancePC(pcState, curStaticInst);
  84             thread->pcState(pcState);
  85             DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
  86         }
  87     }
  88 }
  89 //////////////////////////////////////////////////
  90
  91 template <class Impl>
  92 void
  93 Checker<Impl>::handlePendingInt()
  94 {
  95     DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
  96                      thread->pcState(), instList.size());
  97     DynInstPtr boundaryInst = NULL;
  98     if (!instList.empty()) {
  99         // Set the instructions as completed and verify as much as possible.
 100         DynInstPtr inst;
 101         typename std::list<DynInstPtr>::iterator itr;
 102
 103         for (itr = instList.begin(); itr != instList.end(); itr++) {
 104             (*itr)->setCompleted();
 105         }
 106
 107         inst = instList.front();
 108         boundaryInst = instList.back();
 109         verify(inst); // verify the instructions
 110         inst = NULL;
 111     }
 112     if ((!boundaryInst && curMacroStaticInst &&
 113           curStaticInst->isDelayedCommit() &&
 114           !curStaticInst->isLastMicroop()) ||
 115         (boundaryInst && boundaryInst->isDelayedCommit() &&
 116          !boundaryInst->isLastMicroop())) {
 117         panic("%lli: Trying to take an interrupt in middle of "
 118               "a non-interuptable instruction!", curTick());
 119     }
 120     boundaryInst = NULL;
 121     thread->decoder.reset();
 122     curMacroStaticInst = StaticInst::nullStaticInstPtr;
 123 }
 124
 125 template <class Impl>
 126 void
 127 Checker<Impl>::verify(const DynInstPtr &completed_inst)
 128 {
 129     DynInstPtr inst;
 130
 131     // Make sure serializing instructions are actually
 132     // seen as serializing to commit. instList should be
 133     // empty in these cases.
 134     if ((completed_inst->isSerializing() ||
 135         completed_inst->isSerializeBefore()) &&
 136         (!instList.empty() ?
 137          (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
 138         panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
 139               " entering instList with other instructions\n", curTick(),
 140               completed_inst->seqNum, completed_inst->pcState());
 141     }
 142
 143     // Either check this instruction, or add it to a list of
 144     // instructions waiting to be checked.  Instructions must be
 145     // checked in program order, so if a store has committed yet not
 146     // completed, there may be some instructions that are waiting
 147     // behind it that have completed and must be checked.
 148     if (!instList.empty()) {
 149         if (youngestSN < completed_inst->seqNum) {
 150             DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
 151                     completed_inst->seqNum, completed_inst->pcState());
 152             instList.push_back(completed_inst);
 153             youngestSN = completed_inst->seqNum;
 154         }
 155
 156         if (!instList.front()->isCompleted()) {
 157             return;
 158         } else {
 159             inst = instList.front();
 160             instList.pop_front();
 161         }
 162     } else {
 163         if (!completed_inst->isCompleted()) {
 164             if (youngestSN < completed_inst->seqNum) {
 165                 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
 166                         completed_inst->seqNum, completed_inst->pcState());
 167                 instList.push_back(completed_inst);
 168                 youngestSN = completed_inst->seqNum;
 169             }
 170             return;
 171         } else {
 172             if (youngestSN < completed_inst->seqNum) {
 173                 inst = completed_inst;
 174                 youngestSN = completed_inst->seqNum;
 175             } else {
 176                 return;
 177             }
 178         }
 179     }
 180
 181     // Make sure a serializing instruction is actually seen as
 182     // serializing. instList should be empty here
 183     if (inst->isSerializeAfter() && !instList.empty()) {
 184         panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
 185              " exiting instList with other instructions\n", curTick(),
 186              completed_inst->seqNum, completed_inst->pcState());
 187     }
 188     unverifiedInst = inst;
 189     inst = NULL;
 190
 191     // Try to check all instructions that are completed, ending if we
 192     // run out of instructions to check or if an instruction is not
 193     // yet completed.
 194     while (1) {
 195         DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
 196                 unverifiedInst->seqNum, unverifiedInst->pcState());
 197         unverifiedReq = NULL;
 198         unverifiedReq = unverifiedInst->reqToVerify;
 199         unverifiedMemData = unverifiedInst->memData;
 200         // Make sure results queue is empty
 201         while (!result.empty()) {
 202             result.pop();
 203         }
 204         numCycles++;
 205
 206         Fault fault = NoFault;
 207
 208         // maintain $r0 semantics
 209         thread->setIntReg(ZeroReg, 0);
 210 #if THE_ISA == ALPHA_ISA
 211         thread->setFloatReg(ZeroReg, 0);
 212 #endif
 213
 214         // Check if any recent PC changes match up with anything we
 215         // expect to happen.  This is mostly to check if traps or
 216         // PC-based events have occurred in both the checker and CPU.
 217         if (changedPC) {
 218             DPRINTF(Checker, "Changed PC recently to %s\n",
 219                     thread->pcState());
 220             if (willChangePC) {
 221                 if (newPCState == thread->pcState()) {
 222                     DPRINTF(Checker, "Changed PC matches expected PC\n");
 223                 } else {
 224                     warn("%lli: Changed PC does not match expected PC, "
 225                          "changed: %s, expected: %s",
 226                          curTick(), thread->pcState(), newPCState);
 227                     CheckerCPU::handleError();
 228                 }
 229                 willChangePC = false;
 230             }
 231             changedPC = false;
 232         }
 233
 234         // Try to fetch the instruction
 235         uint64_t fetchOffset = 0;
 236         bool fetchDone = false;
 237
 238         while (!fetchDone) {
 239             Addr fetch_PC = thread->instAddr();
 240             fetch_PC = (fetch_PC & PCMask) + fetchOffset;
 241
 242             MachInst machInst;
 243
 244             // If not in the middle of a macro instruction
 245             if (!curMacroStaticInst) {
 246                 // set up memory request for instruction fetch
 247                 auto mem_req = std::make_shared<Request>(
 248                     unverifiedInst->threadNumber, fetch_PC,
 249                     sizeof(MachInst), 0, masterId, fetch_PC,
 250                     thread->contextId());
 251
 252                 mem_req->setVirt(0, fetch_PC, sizeof(MachInst),
 253                                  Request::INST_FETCH, masterId,
 254                                  thread->instAddr());
 255
 256                 fault = itb->translateFunctional(
 257                     mem_req, tc, BaseTLB::Execute);
 258
 259                 if (fault != NoFault) {
 260                     if (unverifiedInst->getFault() == NoFault) {
 261                         // In this case the instruction was not a dummy
 262                         // instruction carrying an ITB fault.  In the single
 263                         // threaded case the ITB should still be able to
 264                         // translate this instruction; in the SMT case it's
 265                         // possible that its ITB entry was kicked out.
 266                         warn("%lli: Instruction PC %s was not found in the "
 267                              "ITB!", curTick(), thread->pcState());
 268                         handleError(unverifiedInst);
 269
 270                         // go to the next instruction
 271                         advancePC(NoFault);
 272
 273                         // Give up on an ITB fault..
 274                         unverifiedInst = NULL;
 275                         return;
 276                     } else {
 277                         // The instruction is carrying an ITB fault.  Handle
 278                         // the fault and see if our results match the CPU on
 279                         // the next tick().
 280                         fault = unverifiedInst->getFault();
 281                         break;
 282                     }
 283                 } else {
 284                     PacketPtr pkt = new Packet(mem_req, MemCmd::ReadReq);
 285
 286                     pkt->dataStatic(&machInst);
 287                     icachePort->sendFunctional(pkt);
 288                     machInst = gtoh(machInst);
 289
 290                     delete pkt;
 291                 }
 292             }
 293
 294             if (fault == NoFault) {
 295                 TheISA::PCState pcState = thread->pcState();
 296
 297                 if (isRomMicroPC(pcState.microPC())) {
 298                     fetchDone = true;
 299                     curStaticInst =
 300                         microcodeRom.fetchMicroop(pcState.microPC(), NULL);
 301                 } else if (!curMacroStaticInst) {
 302                     //We're not in the middle of a macro instruction
 303                     StaticInstPtr instPtr = nullptr;
 304
 305                     //Predecode, ie bundle up an ExtMachInst
 306                     //If more fetch data is needed, pass it in.
 307                     Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
 308                     thread->decoder.moreBytes(pcState, fetchPC, machInst);
 309
 310                     //If an instruction is ready, decode it.
 311                     //Otherwise, we'll have to fetch beyond the
 312                     //MachInst at the current pc.
 313                     if (thread->decoder.instReady()) {
 314                         fetchDone = true;
 315                         instPtr = thread->decoder.decode(pcState);
 316                         thread->pcState(pcState);
 317                     } else {
 318                         fetchDone = false;
 319                         fetchOffset += sizeof(TheISA::MachInst);
 320                     }
 321
 322                     //If we decoded an instruction and it's microcoded,
 323                     //start pulling out micro ops
 324                     if (instPtr && instPtr->isMacroop()) {
 325                         curMacroStaticInst = instPtr;
 326                         curStaticInst =
 327                             instPtr->fetchMicroop(pcState.microPC());
 328                     } else {
 329                         curStaticInst = instPtr;
 330                     }
 331                 } else {
 332                     // Read the next micro op from the macro-op
 333                     curStaticInst =
 334                         curMacroStaticInst->fetchMicroop(pcState.microPC());
 335                     fetchDone = true;
 336                 }
 337             }
 338         }
 339         // reset decoder on Checker
 340         thread->decoder.reset();
 341
 342         // Check Checker and CPU get same instruction, and record
 343         // any faults the CPU may have had.
 344         Fault unverifiedFault;
 345         if (fault == NoFault) {
 346             unverifiedFault = unverifiedInst->getFault();
 347
 348             // Checks that the instruction matches what we expected it to be.
 349             // Checks both the machine instruction and the PC.
 350             validateInst(unverifiedInst);
 351         }
 352
 353         // keep an instruction count
 354         numInst++;
 355
 356
 357         // Either the instruction was a fault and we should process the fault,
 358         // or we should just go ahead execute the instruction.  This assumes
 359         // that the instruction is properly marked as a fault.
 360         if (fault == NoFault) {
 361             // Execute Checker instruction and trace
 362             if (!unverifiedInst->isUnverifiable()) {
 363                 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
 364                                                            tc,
 365                                                            curStaticInst,
 366                                                            pcState(),
 367                                                            curMacroStaticInst);
 368                 fault = curStaticInst->execute(this, traceData);
 369                 if (traceData) {
 370                     traceData->dump();
 371                     delete traceData;
 372                 }
 373             }
 374
 375             if (fault == NoFault && unverifiedFault == NoFault) {
 376                 thread->funcExeInst++;
 377                 // Checks to make sure instrution results are correct.
 378                 validateExecution(unverifiedInst);
 379
 380                 if (curStaticInst->isLoad()) {
 381                     ++numLoad;
 382                 }
 383             } else if (fault != NoFault && unverifiedFault == NoFault) {
 384                 panic("%lli: sn: %lli at PC: %s took a fault in checker "
 385                       "but not in driver CPU\n", curTick(),
 386                       unverifiedInst->seqNum, unverifiedInst->pcState());
 387             } else if (fault == NoFault && unverifiedFault != NoFault) {
 388                 panic("%lli: sn: %lli at PC: %s took a fault in driver "
 389                       "CPU but not in checker\n", curTick(),
 390                       unverifiedInst->seqNum, unverifiedInst->pcState());
 391             }
 392         }
 393
 394         // Take any faults here
 395         if (fault != NoFault) {
 396             if (FullSystem) {
 397                 fault->invoke(tc, curStaticInst);
 398                 willChangePC = true;
 399                 newPCState = thread->pcState();
 400                 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
 401                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
 402             }
 403         } else {
 404            advancePC(fault);
 405         }
 406
 407         if (FullSystem) {
 408             // @todo: Determine if these should happen only if the
 409             // instruction hasn't faulted.  In the SimpleCPU case this may
 410             // not be true, but in the O3 case this may be true.
 411             Addr oldpc;
 412             int count = 0;
 413             do {
 414                 oldpc = thread->instAddr();
 415                 system->pcEventQueue.service(tc);
 416                 count++;
 417             } while (oldpc != thread->instAddr());
 418             if (count > 1) {
 419                 willChangePC = true;
 420                 newPCState = thread->pcState();
 421                 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
 422             }
 423         }
 424
 425         // @todo:  Optionally can check all registers. (Or just those
 426         // that have been modified).
 427         validateState();
 428
 429         // Continue verifying instructions if there's another completed
 430         // instruction waiting to be verified.
 431         if (instList.empty()) {
 432             break;
 433         } else if (instList.front()->isCompleted()) {
 434             unverifiedInst = NULL;
 435             unverifiedInst = instList.front();
 436             instList.pop_front();
 437         } else {
 438             break;
 439         }
 440     }
 441     unverifiedInst = NULL;
 442 }
 443
 444 template <class Impl>
 445 void
 446 Checker<Impl>::switchOut()
 447 {
 448     instList.clear();
 449 }
 450
 451 template <class Impl>
 452 void
 453 Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
 454 {
 455 }
 456
 457 template <class Impl>
 458 void
 459 Checker<Impl>::validateInst(const DynInstPtr &inst)
 460 {
 461     if (inst->instAddr() != thread->instAddr()) {
 462         warn("%lli: PCs do not match! Inst: %s, checker: %s",
 463              curTick(), inst->pcState(), thread->pcState());
 464         if (changedPC) {
 465             warn("%lli: Changed PCs recently, may not be an error",
 466                  curTick());
 467         } else {
 468             handleError(inst);
 469         }
 470     }
 471
 472     if (curStaticInst != inst->staticInst) {
 473         warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
 474                 curStaticInst->getName(), inst->staticInst->getName());
 475     }
 476 }
 477
 478 template <class Impl>
 479 void
 480 Checker<Impl>::validateExecution(const DynInstPtr &inst)
 481 {
 482     InstResult checker_val;
 483     InstResult inst_val;
 484     int idx = -1;
 485     bool result_mismatch = false;
 486     bool scalar_mismatch = false;
 487     bool vector_mismatch = false;
 488
 489     if (inst->isUnverifiable()) {
 490         // Unverifiable instructions assume they were executed
 491         // properly by the CPU. Grab the result from the
 492         // instruction and write it to the register.
 493         copyResult(inst, InstResult(0ul, InstResult::ResultType::Scalar), idx);
 494     } else if (inst->numDestRegs() > 0 && !result.empty()) {
 495         DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
 496                          inst->numDestRegs(), result.size());
 497         for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
 498             checker_val = result.front();
 499             result.pop();
 500             inst_val = inst->popResult(
 501                     InstResult(0ul, InstResult::ResultType::Scalar));
 502             if (checker_val != inst_val) {
 503                 result_mismatch = true;
 504                 idx = i;
 505                 scalar_mismatch = checker_val.isScalar();
 506                 vector_mismatch = checker_val.isVector();
 507                 panic_if(!(scalar_mismatch || vector_mismatch),
 508                         "Unknown type of result\n");
 509             }
 510         }
 511     } // Checker CPU checks all the saved results in the dyninst passed by
 512       // the cpu model being checked against the saved results present in
 513       // the static inst executed in the Checker.  Sometimes the number
 514       // of saved results differs between the dyninst and static inst, but
 515       // this is ok and not a bug.  May be worthwhile to try and correct this.
 516
 517     if (result_mismatch) {
 518         if (scalar_mismatch) {
 519             warn("%lli: Instruction results (%i) do not match! (Values may"
 520                  " not actually be integers) Inst: %#x, checker: %#x",
 521                  curTick(), idx, inst_val.asIntegerNoAssert(),
 522                  checker_val.asInteger());
 523         }
 524
 525         // It's useful to verify load values from memory, but in MP
 526         // systems the value obtained at execute may be different than
 527         // the value obtained at completion.  Similarly DMA can
 528         // present the same problem on even UP systems.  Thus there is
 529         // the option to only warn on loads having a result error.
 530         // The load/store queue in Detailed CPU can also cause problems
 531         // if load/store forwarding is allowed.
 532         if (inst->isLoad() && warnOnlyOnLoadError) {
 533             copyResult(inst, inst_val, idx);
 534         } else {
 535             handleError(inst);
 536         }
 537     }
 538
 539     if (inst->nextInstAddr() != thread->nextInstAddr()) {
 540         warn("%lli: Instruction next PCs do not match! Inst: %#x, "
 541              "checker: %#x",
 542              curTick(), inst->nextInstAddr(), thread->nextInstAddr());
 543         handleError(inst);
 544     }
 545
 546     // Checking side effect registers can be difficult if they are not
 547     // checked simultaneously with the execution of the instruction.
 548     // This is because other valid instructions may have modified
 549     // these registers in the meantime, and their values are not
 550     // stored within the DynInst.
 551     while (!miscRegIdxs.empty()) {
 552         int misc_reg_idx = miscRegIdxs.front();
 553         miscRegIdxs.pop();
 554
 555         if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
 556             thread->readMiscRegNoEffect(misc_reg_idx)) {
 557             warn("%lli: Misc reg idx %i (side effect) does not match! "
 558                  "Inst: %#x, checker: %#x",
 559                  curTick(), misc_reg_idx,
 560                  inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
 561                  thread->readMiscRegNoEffect(misc_reg_idx));
 562             handleError(inst);
 563         }
 564     }
 565 }
 566
 567
 568 // This function is weird, if it is called it means the Checker and
 569 // O3 have diverged, so panic is called for now.  It may be useful
 570 // to resynch states and continue if the divergence is a false positive
 571 template <class Impl>
 572 void
 573 Checker<Impl>::validateState()
 574 {
 575     if (updateThisCycle) {
 576         // Change this back to warn if divergences end up being false positives
 577         panic("%lli: Instruction PC %#x results didn't match up, copying all "
 578              "registers from main CPU", curTick(), unverifiedInst->instAddr());
 579
 580         // Terribly convoluted way to make sure O3 model does not implode
 581         bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
 582         unverifiedInst->thread->noSquashFromTC = true;
 583
 584         // Heavy-weight copying of all registers
 585         thread->copyArchRegs(unverifiedInst->tcBase());
 586         unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
 587
 588         // Set curStaticInst to unverifiedInst->staticInst
 589         curStaticInst = unverifiedInst->staticInst;
 590         // Also advance the PC.  Hopefully no PC-based events happened.
 591         advancePC(NoFault);
 592         updateThisCycle = false;
 593     }
 594 }
 595
 596 template <class Impl>
 597 void
 598 Checker<Impl>::copyResult(const DynInstPtr &inst,
 599                           const InstResult& mismatch_val, int start_idx)
 600 {
 601     // We've already popped one dest off the queue,
 602     // so do the fix-up then start with the next dest reg;
 603     if (start_idx >= 0) {
 604         const RegId& idx = inst->destRegIdx(start_idx);
 605         switch (idx.classValue()) {
 606           case IntRegClass:
 607             panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
 608             thread->setIntReg(idx.index(), mismatch_val.asInteger());
 609             break;
 610           case FloatRegClass:
 611             panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
 612             thread->setFloatReg(idx.index(), mismatch_val.asInteger());
 613             break;
 614           case VecRegClass:
 615             panic_if(!mismatch_val.isVector(), "Unexpected type of result");
 616             thread->setVecReg(idx, mismatch_val.asVector());
 617             break;
 618           case VecElemClass:
 619             panic_if(!mismatch_val.isVecElem(),
 620                      "Unexpected type of result");
 621             thread->setVecElem(idx, mismatch_val.asVectorElem());
 622             break;
 623           case CCRegClass:
 624             panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
 625             thread->setCCReg(idx.index(), mismatch_val.asInteger());
 626             break;
 627           case MiscRegClass:
 628             panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
 629             thread->setMiscReg(idx.index(), mismatch_val.asInteger());
 630             break;
 631           default:
 632             panic("Unknown register class: %d", (int)idx.classValue());
 633         }
 634     }
 635     start_idx++;
 636     InstResult res;
 637     for (int i = start_idx; i < inst->numDestRegs(); i++) {
 638         const RegId& idx = inst->destRegIdx(i);
 639         res = inst->popResult();
 640         switch (idx.classValue()) {
 641           case IntRegClass:
 642             panic_if(!res.isScalar(), "Unexpected type of result");
 643             thread->setIntReg(idx.index(), res.asInteger());
 644             break;
 645           case FloatRegClass:
 646             panic_if(!res.isScalar(), "Unexpected type of result");
 647             thread->setFloatReg(idx.index(), res.asInteger());
 648             break;
 649           case VecRegClass:
 650             panic_if(!res.isVector(), "Unexpected type of result");
 651             thread->setVecReg(idx, res.asVector());
 652             break;
 653           case VecElemClass:
 654             panic_if(!res.isVecElem(), "Unexpected type of result");
 655             thread->setVecElem(idx, res.asVectorElem());
 656             break;
 657           case CCRegClass:
 658             panic_if(!res.isScalar(), "Unexpected type of result");
 659             thread->setCCReg(idx.index(), res.asInteger());
 660             break;
 661           case MiscRegClass:
 662             panic_if(res.isValid(), "MiscReg expecting invalid result");
 663             // Try to get the proper misc register index for ARM here...
 664             thread->setMiscReg(idx.index(), 0);
 665             break;
 666             // else Register is out of range...
 667           default:
 668             panic("Unknown register class: %d", (int)idx.classValue());
 669         }
 670     }
 671 }
 672
 673 template <class Impl>
 674 void
 675 Checker<Impl>::dumpAndExit(const DynInstPtr &inst)
 676 {
 677     cprintf("Error detected, instruction information:\n");
 678     cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
 679             "Completed:%i\n",
 680             inst->pcState(),
 681             inst->nextInstAddr(),
 682             inst->seqNum,
 683             inst->threadNumber,
 684             inst->isCompleted());
 685     inst->dump();
 686     CheckerCPU::dumpAndExit();
 687 }
 688
 689 template <class Impl>
 690 void
 691 Checker<Impl>::dumpInsts()
 692 {
 693     int num = 0;
 694
 695     InstListIt inst_list_it = --(instList.end());
 696
 697     cprintf("Inst list size: %i\n", instList.size());
 698
 699     while (inst_list_it != instList.end())
 700     {
 701         cprintf("Instruction:%i\n",
 702                 num);
 703
 704         cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
 705                 "Completed:%i\n",
 706                 (*inst_list_it)->pcState(),
 707                 (*inst_list_it)->seqNum,
 708                 (*inst_list_it)->threadNumber,
 709                 (*inst_list_it)->isCompleted());
 710
 711         cprintf("\n");
 712
 713         inst_list_it--;
 714         ++num;
 715     }
 716
 717 }
 718
 719 #endif//__CPU_CHECKER_CPU_IMPL_HH__