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34 #include "base/refcnt.hh"
35 #include "cpu/base_dyn_inst.hh"
36 #include "cpu/checker/cpu.hh"
37 #include "cpu/simple_thread.hh"
38 #include "cpu/thread_context.hh"
39 #include "cpu/static_inst.hh"
40 #include "mem/packet_impl.hh"
41 #include "sim/byteswap.hh"
42 #include "sim/sim_object.hh"
43 #include "sim/stats.hh"
46 #include "arch/vtophys.hh"
50 //The CheckerCPU does alpha only
51 using namespace AlphaISA;
53 template <class DynInstPtr>
55 Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
59 // Either check this instruction, or add it to a list of
60 // instructions waiting to be checked. Instructions must be
61 // checked in program order, so if a store has committed yet not
62 // completed, there may be some instructions that are waiting
63 // behind it that have completed and must be checked.
64 if (!instList.empty()) {
65 if (youngestSN < completed_inst->seqNum) {
66 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
67 completed_inst->seqNum, completed_inst->readPC());
68 instList.push_back(completed_inst);
69 youngestSN = completed_inst->seqNum;
72 if (!instList.front()->isCompleted()) {
75 inst = instList.front();
79 if (!completed_inst->isCompleted()) {
80 if (youngestSN < completed_inst->seqNum) {
81 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
82 completed_inst->seqNum, completed_inst->readPC());
83 instList.push_back(completed_inst);
84 youngestSN = completed_inst->seqNum;
88 if (youngestSN < completed_inst->seqNum) {
89 inst = completed_inst;
90 youngestSN = completed_inst->seqNum;
97 unverifiedInst = inst;
99 // Try to check all instructions that are completed, ending if we
100 // run out of instructions to check or if an instruction is not
103 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
104 inst->seqNum, inst->readPC());
105 unverifiedResult.integer = inst->readIntResult();
106 unverifiedReq = inst->req;
107 unverifiedMemData = inst->memData;
110 Fault fault = NoFault;
112 // maintain $r0 semantics
113 thread->setIntReg(ZeroReg, 0);
115 thread->setFloatRegDouble(ZeroReg, 0.0);
116 #endif // TARGET_ALPHA
118 // Check if any recent PC changes match up with anything we
119 // expect to happen. This is mostly to check if traps or
120 // PC-based events have occurred in both the checker and CPU.
122 DPRINTF(Checker, "Changed PC recently to %#x\n",
125 if (newPC == thread->readPC()) {
126 DPRINTF(Checker, "Changed PC matches expected PC\n");
128 warn("%lli: Changed PC does not match expected PC, "
129 "changed: %#x, expected: %#x",
130 curTick, thread->readPC(), newPC);
131 CheckerCPU::handleError();
133 willChangePC = false;
138 DPRINTF(Checker, "Changed NextPC recently to %#x\n",
139 thread->readNextPC());
140 changedNextPC = false;
143 // Try to fetch the instruction
146 #define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
148 #define IFETCH_FLAGS(pc) 0
151 uint64_t fetch_PC = thread->readPC() & ~3;
153 // set up memory request for instruction fetch
154 memReq = new Request(inst->threadNumber, fetch_PC,
156 IFETCH_FLAGS(thread->readPC()),
157 fetch_PC, thread->readCpuId(), inst->threadNumber);
159 bool succeeded = translateInstReq(memReq);
162 if (inst->getFault() == NoFault) {
163 // In this case the instruction was not a dummy
164 // instruction carrying an ITB fault. In the single
165 // threaded case the ITB should still be able to
166 // translate this instruction; in the SMT case it's
167 // possible that its ITB entry was kicked out.
168 warn("%lli: Instruction PC %#x was not found in the ITB!",
169 curTick, thread->readPC());
172 // go to the next instruction
173 thread->setPC(thread->readNextPC());
174 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
178 // The instruction is carrying an ITB fault. Handle
179 // the fault and see if our results match the CPU on
181 fault = inst->getFault();
185 if (fault == NoFault) {
186 Packet *pkt = new Packet(memReq, Packet::ReadReq,
189 pkt->dataStatic(&machInst);
191 icachePort->sendFunctional(pkt);
195 // keep an instruction count
198 // decode the instruction
199 machInst = gtoh(machInst);
200 // Checks that the instruction matches what we expected it to be.
201 // Checks both the machine instruction and the PC.
204 curStaticInst = StaticInst::decode(makeExtMI(machInst,
208 thread->setInst(machInst);
209 #endif // FULL_SYSTEM
211 fault = inst->getFault();
214 // Discard fetch's memReq.
218 // Either the instruction was a fault and we should process the fault,
219 // or we should just go ahead execute the instruction. This assumes
220 // that the instruction is properly marked as a fault.
221 if (fault == NoFault) {
223 thread->funcExeInst++;
225 if (!inst->isUnverifiable())
226 fault = curStaticInst->execute(this, NULL);
228 // Checks to make sure instrution results are correct.
229 validateExecution(inst);
231 if (curStaticInst->isLoad()) {
236 if (fault != NoFault) {
240 newPC = thread->readPC();
241 DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
244 #if THE_ISA != MIPS_ISA
245 // go to the next instruction
246 thread->setPC(thread->readNextPC());
247 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
249 // go to the next instruction
250 thread->setPC(thread->readNextPC());
251 thread->setNextPC(thread->readNextNPC());
252 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
258 // @todo: Determine if these should happen only if the
259 // instruction hasn't faulted. In the SimpleCPU case this may
260 // not be true, but in the O3 or Ozone case this may be true.
264 oldpc = thread->readPC();
265 system->pcEventQueue.service(tc);
267 } while (oldpc != thread->readPC());
270 newPC = thread->readPC();
271 DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
275 // @todo: Optionally can check all registers. (Or just those
276 // that have been modified).
284 // Continue verifying instructions if there's another completed
285 // instruction waiting to be verified.
286 if (instList.empty()) {
288 } else if (instList.front()->isCompleted()) {
289 inst = instList.front();
290 instList.pop_front();
295 unverifiedInst = NULL;
298 template <class DynInstPtr>
300 Checker<DynInstPtr>::switchOut()
305 template <class DynInstPtr>
307 Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
311 template <class DynInstPtr>
313 Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
315 if (inst->readPC() != thread->readPC()) {
316 warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
317 curTick, inst->readPC(), thread->readPC());
319 warn("%lli: Changed PCs recently, may not be an error",
326 MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
328 if (mi != machInst) {
329 warn("%lli: Binary instructions do not match! Inst: %#x, "
331 curTick, mi, machInst);
336 template <class DynInstPtr>
338 Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
340 bool result_mismatch = false;
341 if (inst->numDestRegs()) {
342 // @todo: Support more destination registers.
343 if (inst->isUnverifiable()) {
344 // Unverifiable instructions assume they were executed
345 // properly by the CPU. Grab the result from the
346 // instruction and write it to the register.
348 } else if (result.integer != inst->readIntResult()) {
349 result_mismatch = true;
353 if (result_mismatch) {
354 warn("%lli: Instruction results do not match! (Values may not "
355 "actually be integers) Inst: %#x, checker: %#x",
356 curTick, inst->readIntResult(), result.integer);
358 // It's useful to verify load values from memory, but in MP
359 // systems the value obtained at execute may be different than
360 // the value obtained at completion. Similarly DMA can
361 // present the same problem on even UP systems. Thus there is
362 // the option to only warn on loads having a result error.
363 if (inst->isLoad() && warnOnlyOnLoadError) {
370 if (inst->readNextPC() != thread->readNextPC()) {
371 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
373 curTick, inst->readNextPC(), thread->readNextPC());
377 // Checking side effect registers can be difficult if they are not
378 // checked simultaneously with the execution of the instruction.
379 // This is because other valid instructions may have modified
380 // these registers in the meantime, and their values are not
381 // stored within the DynInst.
382 while (!miscRegIdxs.empty()) {
383 int misc_reg_idx = miscRegIdxs.front();
386 if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
387 thread->readMiscReg(misc_reg_idx)) {
388 warn("%lli: Misc reg idx %i (side effect) does not match! "
389 "Inst: %#x, checker: %#x",
390 curTick, misc_reg_idx,
391 inst->tcBase()->readMiscReg(misc_reg_idx),
392 thread->readMiscReg(misc_reg_idx));
398 template <class DynInstPtr>
400 Checker<DynInstPtr>::validateState()
402 if (updateThisCycle) {
403 warn("%lli: Instruction PC %#x results didn't match up, copying all "
404 "registers from main CPU", curTick, unverifiedInst->readPC());
405 // Heavy-weight copying of all registers
406 thread->copyArchRegs(unverifiedInst->tcBase());
407 // Also advance the PC. Hopefully no PC-based events happened.
408 #if THE_ISA != MIPS_ISA
409 // go to the next instruction
410 thread->setPC(thread->readNextPC());
411 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
413 // go to the next instruction
414 thread->setPC(thread->readNextPC());
415 thread->setNextPC(thread->readNextNPC());
416 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
418 updateThisCycle = false;
422 template <class DynInstPtr>
424 Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
426 RegIndex idx = inst->destRegIdx(0);
427 if (idx < TheISA::FP_Base_DepTag) {
428 thread->setIntReg(idx, inst->readIntResult());
429 } else if (idx < TheISA::Fpcr_DepTag) {
430 thread->setFloatRegBits(idx, inst->readIntResult());
432 thread->setMiscReg(idx, inst->readIntResult());
436 template <class DynInstPtr>
438 Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
440 cprintf("Error detected, instruction information:\n");
441 cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
447 inst->isCompleted());
449 CheckerCPU::dumpAndExit();
452 template <class DynInstPtr>
454 Checker<DynInstPtr>::dumpInsts()
458 InstListIt inst_list_it = --(instList.end());
460 cprintf("Inst list size: %i\n", instList.size());
462 while (inst_list_it != instList.end())
464 cprintf("Instruction:%i\n",
467 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
469 (*inst_list_it)->readPC(),
470 (*inst_list_it)->seqNum,
471 (*inst_list_it)->threadNumber,
472 (*inst_list_it)->isCompleted());