f4b43b2986ce3442bbe80a6fdfd969f1187ba684
[gem5.git] / src / cpu / checker / cpu_impl.hh
1 /*
2 * Copyright (c) 2011, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Geoffrey Blake
43 */
44
45 #ifndef __CPU_CHECKER_CPU_IMPL_HH__
46 #define __CPU_CHECKER_CPU_IMPL_HH__
47
48 #include <list>
49 #include <string>
50
51 #include "arch/isa_traits.hh"
52 #include "arch/vtophys.hh"
53 #include "base/refcnt.hh"
54 #include "config/the_isa.hh"
55 #include "cpu/base_dyn_inst.hh"
56 #include "cpu/exetrace.hh"
57 #include "cpu/reg_class.hh"
58 #include "cpu/simple_thread.hh"
59 #include "cpu/static_inst.hh"
60 #include "cpu/thread_context.hh"
61 #include "cpu/checker/cpu.hh"
62 #include "debug/Checker.hh"
63 #include "sim/full_system.hh"
64 #include "sim/sim_object.hh"
65 #include "sim/stats.hh"
66
67 using namespace std;
68 using namespace TheISA;
69
70 template <class Impl>
71 void
72 Checker<Impl>::advancePC(const Fault &fault)
73 {
74 if (fault != NoFault) {
75 curMacroStaticInst = StaticInst::nullStaticInstPtr;
76 fault->invoke(tc, curStaticInst);
77 thread->decoder.reset();
78 } else {
79 if (curStaticInst) {
80 if (curStaticInst->isLastMicroop())
81 curMacroStaticInst = StaticInst::nullStaticInstPtr;
82 TheISA::PCState pcState = thread->pcState();
83 TheISA::advancePC(pcState, curStaticInst);
84 thread->pcState(pcState);
85 DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
86 }
87 }
88 }
89 //////////////////////////////////////////////////
90
91 template <class Impl>
92 void
93 Checker<Impl>::handlePendingInt()
94 {
95 DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
96 thread->pcState(), instList.size());
97 DynInstPtr boundaryInst = NULL;
98 if (!instList.empty()) {
99 // Set the instructions as completed and verify as much as possible.
100 DynInstPtr inst;
101 typename std::list<DynInstPtr>::iterator itr;
102
103 for (itr = instList.begin(); itr != instList.end(); itr++) {
104 (*itr)->setCompleted();
105 }
106
107 inst = instList.front();
108 boundaryInst = instList.back();
109 verify(inst); // verify the instructions
110 inst = NULL;
111 }
112 if ((!boundaryInst && curMacroStaticInst &&
113 curStaticInst->isDelayedCommit() &&
114 !curStaticInst->isLastMicroop()) ||
115 (boundaryInst && boundaryInst->isDelayedCommit() &&
116 !boundaryInst->isLastMicroop())) {
117 panic("%lli: Trying to take an interrupt in middle of "
118 "a non-interuptable instruction!", curTick());
119 }
120 boundaryInst = NULL;
121 thread->decoder.reset();
122 curMacroStaticInst = StaticInst::nullStaticInstPtr;
123 }
124
125 template <class Impl>
126 void
127 Checker<Impl>::verify(const DynInstPtr &completed_inst)
128 {
129 DynInstPtr inst;
130
131 // Make sure serializing instructions are actually
132 // seen as serializing to commit. instList should be
133 // empty in these cases.
134 if ((completed_inst->isSerializing() ||
135 completed_inst->isSerializeBefore()) &&
136 (!instList.empty() ?
137 (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
138 panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
139 " entering instList with other instructions\n", curTick(),
140 completed_inst->seqNum, completed_inst->pcState());
141 }
142
143 // Either check this instruction, or add it to a list of
144 // instructions waiting to be checked. Instructions must be
145 // checked in program order, so if a store has committed yet not
146 // completed, there may be some instructions that are waiting
147 // behind it that have completed and must be checked.
148 if (!instList.empty()) {
149 if (youngestSN < completed_inst->seqNum) {
150 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
151 completed_inst->seqNum, completed_inst->pcState());
152 instList.push_back(completed_inst);
153 youngestSN = completed_inst->seqNum;
154 }
155
156 if (!instList.front()->isCompleted()) {
157 return;
158 } else {
159 inst = instList.front();
160 instList.pop_front();
161 }
162 } else {
163 if (!completed_inst->isCompleted()) {
164 if (youngestSN < completed_inst->seqNum) {
165 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
166 completed_inst->seqNum, completed_inst->pcState());
167 instList.push_back(completed_inst);
168 youngestSN = completed_inst->seqNum;
169 }
170 return;
171 } else {
172 if (youngestSN < completed_inst->seqNum) {
173 inst = completed_inst;
174 youngestSN = completed_inst->seqNum;
175 } else {
176 return;
177 }
178 }
179 }
180
181 // Make sure a serializing instruction is actually seen as
182 // serializing. instList should be empty here
183 if (inst->isSerializeAfter() && !instList.empty()) {
184 panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
185 " exiting instList with other instructions\n", curTick(),
186 completed_inst->seqNum, completed_inst->pcState());
187 }
188 unverifiedInst = inst;
189 inst = NULL;
190
191 // Try to check all instructions that are completed, ending if we
192 // run out of instructions to check or if an instruction is not
193 // yet completed.
194 while (1) {
195 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
196 unverifiedInst->seqNum, unverifiedInst->pcState());
197 unverifiedReq = NULL;
198 unverifiedReq = unverifiedInst->reqToVerify;
199 unverifiedMemData = unverifiedInst->memData;
200 // Make sure results queue is empty
201 while (!result.empty()) {
202 result.pop();
203 }
204 numCycles++;
205
206 Fault fault = NoFault;
207
208 // maintain $r0 semantics
209 thread->setIntReg(ZeroReg, 0);
210
211 // Check if any recent PC changes match up with anything we
212 // expect to happen. This is mostly to check if traps or
213 // PC-based events have occurred in both the checker and CPU.
214 if (changedPC) {
215 DPRINTF(Checker, "Changed PC recently to %s\n",
216 thread->pcState());
217 if (willChangePC) {
218 if (newPCState == thread->pcState()) {
219 DPRINTF(Checker, "Changed PC matches expected PC\n");
220 } else {
221 warn("%lli: Changed PC does not match expected PC, "
222 "changed: %s, expected: %s",
223 curTick(), thread->pcState(), newPCState);
224 CheckerCPU::handleError();
225 }
226 willChangePC = false;
227 }
228 changedPC = false;
229 }
230
231 // Try to fetch the instruction
232 uint64_t fetchOffset = 0;
233 bool fetchDone = false;
234
235 while (!fetchDone) {
236 Addr fetch_PC = thread->instAddr();
237 fetch_PC = (fetch_PC & PCMask) + fetchOffset;
238
239 MachInst machInst;
240
241 // If not in the middle of a macro instruction
242 if (!curMacroStaticInst) {
243 // set up memory request for instruction fetch
244 auto mem_req = std::make_shared<Request>(
245 unverifiedInst->threadNumber, fetch_PC,
246 sizeof(MachInst), 0, masterId, fetch_PC,
247 thread->contextId());
248
249 mem_req->setVirt(0, fetch_PC, sizeof(MachInst),
250 Request::INST_FETCH, masterId,
251 thread->instAddr());
252
253 fault = itb->translateFunctional(
254 mem_req, tc, BaseTLB::Execute);
255
256 if (fault != NoFault) {
257 if (unverifiedInst->getFault() == NoFault) {
258 // In this case the instruction was not a dummy
259 // instruction carrying an ITB fault. In the single
260 // threaded case the ITB should still be able to
261 // translate this instruction; in the SMT case it's
262 // possible that its ITB entry was kicked out.
263 warn("%lli: Instruction PC %s was not found in the "
264 "ITB!", curTick(), thread->pcState());
265 handleError(unverifiedInst);
266
267 // go to the next instruction
268 advancePC(NoFault);
269
270 // Give up on an ITB fault..
271 unverifiedInst = NULL;
272 return;
273 } else {
274 // The instruction is carrying an ITB fault. Handle
275 // the fault and see if our results match the CPU on
276 // the next tick().
277 fault = unverifiedInst->getFault();
278 break;
279 }
280 } else {
281 PacketPtr pkt = new Packet(mem_req, MemCmd::ReadReq);
282
283 pkt->dataStatic(&machInst);
284 icachePort->sendFunctional(pkt);
285
286 delete pkt;
287 }
288 }
289
290 if (fault == NoFault) {
291 TheISA::PCState pcState = thread->pcState();
292
293 if (isRomMicroPC(pcState.microPC())) {
294 fetchDone = true;
295 curStaticInst =
296 microcodeRom.fetchMicroop(pcState.microPC(), NULL);
297 } else if (!curMacroStaticInst) {
298 //We're not in the middle of a macro instruction
299 StaticInstPtr instPtr = nullptr;
300
301 //Predecode, ie bundle up an ExtMachInst
302 //If more fetch data is needed, pass it in.
303 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
304 thread->decoder.moreBytes(pcState, fetchPC, machInst);
305
306 //If an instruction is ready, decode it.
307 //Otherwise, we'll have to fetch beyond the
308 //MachInst at the current pc.
309 if (thread->decoder.instReady()) {
310 fetchDone = true;
311 instPtr = thread->decoder.decode(pcState);
312 thread->pcState(pcState);
313 } else {
314 fetchDone = false;
315 fetchOffset += sizeof(TheISA::MachInst);
316 }
317
318 //If we decoded an instruction and it's microcoded,
319 //start pulling out micro ops
320 if (instPtr && instPtr->isMacroop()) {
321 curMacroStaticInst = instPtr;
322 curStaticInst =
323 instPtr->fetchMicroop(pcState.microPC());
324 } else {
325 curStaticInst = instPtr;
326 }
327 } else {
328 // Read the next micro op from the macro-op
329 curStaticInst =
330 curMacroStaticInst->fetchMicroop(pcState.microPC());
331 fetchDone = true;
332 }
333 }
334 }
335 // reset decoder on Checker
336 thread->decoder.reset();
337
338 // Check Checker and CPU get same instruction, and record
339 // any faults the CPU may have had.
340 Fault unverifiedFault;
341 if (fault == NoFault) {
342 unverifiedFault = unverifiedInst->getFault();
343
344 // Checks that the instruction matches what we expected it to be.
345 // Checks both the machine instruction and the PC.
346 validateInst(unverifiedInst);
347 }
348
349 // keep an instruction count
350 numInst++;
351
352
353 // Either the instruction was a fault and we should process the fault,
354 // or we should just go ahead execute the instruction. This assumes
355 // that the instruction is properly marked as a fault.
356 if (fault == NoFault) {
357 // Execute Checker instruction and trace
358 if (!unverifiedInst->isUnverifiable()) {
359 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
360 tc,
361 curStaticInst,
362 pcState(),
363 curMacroStaticInst);
364 fault = curStaticInst->execute(this, traceData);
365 if (traceData) {
366 traceData->dump();
367 delete traceData;
368 }
369 }
370
371 if (fault == NoFault && unverifiedFault == NoFault) {
372 thread->funcExeInst++;
373 // Checks to make sure instrution results are correct.
374 validateExecution(unverifiedInst);
375
376 if (curStaticInst->isLoad()) {
377 ++numLoad;
378 }
379 } else if (fault != NoFault && unverifiedFault == NoFault) {
380 panic("%lli: sn: %lli at PC: %s took a fault in checker "
381 "but not in driver CPU\n", curTick(),
382 unverifiedInst->seqNum, unverifiedInst->pcState());
383 } else if (fault == NoFault && unverifiedFault != NoFault) {
384 panic("%lli: sn: %lli at PC: %s took a fault in driver "
385 "CPU but not in checker\n", curTick(),
386 unverifiedInst->seqNum, unverifiedInst->pcState());
387 }
388 }
389
390 // Take any faults here
391 if (fault != NoFault) {
392 if (FullSystem) {
393 fault->invoke(tc, curStaticInst);
394 willChangePC = true;
395 newPCState = thread->pcState();
396 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
397 curMacroStaticInst = StaticInst::nullStaticInstPtr;
398 }
399 } else {
400 advancePC(fault);
401 }
402
403 if (FullSystem) {
404 // @todo: Determine if these should happen only if the
405 // instruction hasn't faulted. In the SimpleCPU case this may
406 // not be true, but in the O3 case this may be true.
407 Addr oldpc;
408 int count = 0;
409 do {
410 oldpc = thread->instAddr();
411 thread->pcEventQueue.service(oldpc, tc);
412 count++;
413 } while (oldpc != thread->instAddr());
414 if (count > 1) {
415 willChangePC = true;
416 newPCState = thread->pcState();
417 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
418 }
419 }
420
421 // @todo: Optionally can check all registers. (Or just those
422 // that have been modified).
423 validateState();
424
425 // Continue verifying instructions if there's another completed
426 // instruction waiting to be verified.
427 if (instList.empty()) {
428 break;
429 } else if (instList.front()->isCompleted()) {
430 unverifiedInst = NULL;
431 unverifiedInst = instList.front();
432 instList.pop_front();
433 } else {
434 break;
435 }
436 }
437 unverifiedInst = NULL;
438 }
439
440 template <class Impl>
441 void
442 Checker<Impl>::switchOut()
443 {
444 instList.clear();
445 }
446
447 template <class Impl>
448 void
449 Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
450 {
451 }
452
453 template <class Impl>
454 void
455 Checker<Impl>::validateInst(const DynInstPtr &inst)
456 {
457 if (inst->instAddr() != thread->instAddr()) {
458 warn("%lli: PCs do not match! Inst: %s, checker: %s",
459 curTick(), inst->pcState(), thread->pcState());
460 if (changedPC) {
461 warn("%lli: Changed PCs recently, may not be an error",
462 curTick());
463 } else {
464 handleError(inst);
465 }
466 }
467
468 if (curStaticInst != inst->staticInst) {
469 warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
470 curStaticInst->getName(), inst->staticInst->getName());
471 }
472 }
473
474 template <class Impl>
475 void
476 Checker<Impl>::validateExecution(const DynInstPtr &inst)
477 {
478 InstResult checker_val;
479 InstResult inst_val;
480 int idx = -1;
481 bool result_mismatch = false;
482 bool scalar_mismatch = false;
483 bool vector_mismatch = false;
484
485 if (inst->isUnverifiable()) {
486 // Unverifiable instructions assume they were executed
487 // properly by the CPU. Grab the result from the
488 // instruction and write it to the register.
489 copyResult(inst, InstResult(0ul, InstResult::ResultType::Scalar), idx);
490 } else if (inst->numDestRegs() > 0 && !result.empty()) {
491 DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
492 inst->numDestRegs(), result.size());
493 for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
494 checker_val = result.front();
495 result.pop();
496 inst_val = inst->popResult(
497 InstResult(0ul, InstResult::ResultType::Scalar));
498 if (checker_val != inst_val) {
499 result_mismatch = true;
500 idx = i;
501 scalar_mismatch = checker_val.isScalar();
502 vector_mismatch = checker_val.isVector();
503 panic_if(!(scalar_mismatch || vector_mismatch),
504 "Unknown type of result\n");
505 }
506 }
507 } // Checker CPU checks all the saved results in the dyninst passed by
508 // the cpu model being checked against the saved results present in
509 // the static inst executed in the Checker. Sometimes the number
510 // of saved results differs between the dyninst and static inst, but
511 // this is ok and not a bug. May be worthwhile to try and correct this.
512
513 if (result_mismatch) {
514 if (scalar_mismatch) {
515 warn("%lli: Instruction results (%i) do not match! (Values may"
516 " not actually be integers) Inst: %#x, checker: %#x",
517 curTick(), idx, inst_val.asIntegerNoAssert(),
518 checker_val.asInteger());
519 }
520
521 // It's useful to verify load values from memory, but in MP
522 // systems the value obtained at execute may be different than
523 // the value obtained at completion. Similarly DMA can
524 // present the same problem on even UP systems. Thus there is
525 // the option to only warn on loads having a result error.
526 // The load/store queue in Detailed CPU can also cause problems
527 // if load/store forwarding is allowed.
528 if (inst->isLoad() && warnOnlyOnLoadError) {
529 copyResult(inst, inst_val, idx);
530 } else {
531 handleError(inst);
532 }
533 }
534
535 if (inst->nextInstAddr() != thread->nextInstAddr()) {
536 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
537 "checker: %#x",
538 curTick(), inst->nextInstAddr(), thread->nextInstAddr());
539 handleError(inst);
540 }
541
542 // Checking side effect registers can be difficult if they are not
543 // checked simultaneously with the execution of the instruction.
544 // This is because other valid instructions may have modified
545 // these registers in the meantime, and their values are not
546 // stored within the DynInst.
547 while (!miscRegIdxs.empty()) {
548 int misc_reg_idx = miscRegIdxs.front();
549 miscRegIdxs.pop();
550
551 if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
552 thread->readMiscRegNoEffect(misc_reg_idx)) {
553 warn("%lli: Misc reg idx %i (side effect) does not match! "
554 "Inst: %#x, checker: %#x",
555 curTick(), misc_reg_idx,
556 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
557 thread->readMiscRegNoEffect(misc_reg_idx));
558 handleError(inst);
559 }
560 }
561 }
562
563
564 // This function is weird, if it is called it means the Checker and
565 // O3 have diverged, so panic is called for now. It may be useful
566 // to resynch states and continue if the divergence is a false positive
567 template <class Impl>
568 void
569 Checker<Impl>::validateState()
570 {
571 if (updateThisCycle) {
572 // Change this back to warn if divergences end up being false positives
573 panic("%lli: Instruction PC %#x results didn't match up, copying all "
574 "registers from main CPU", curTick(), unverifiedInst->instAddr());
575
576 // Terribly convoluted way to make sure O3 model does not implode
577 bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
578 unverifiedInst->thread->noSquashFromTC = true;
579
580 // Heavy-weight copying of all registers
581 thread->copyArchRegs(unverifiedInst->tcBase());
582 unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
583
584 // Set curStaticInst to unverifiedInst->staticInst
585 curStaticInst = unverifiedInst->staticInst;
586 // Also advance the PC. Hopefully no PC-based events happened.
587 advancePC(NoFault);
588 updateThisCycle = false;
589 }
590 }
591
592 template <class Impl>
593 void
594 Checker<Impl>::copyResult(const DynInstPtr &inst,
595 const InstResult& mismatch_val, int start_idx)
596 {
597 // We've already popped one dest off the queue,
598 // so do the fix-up then start with the next dest reg;
599 if (start_idx >= 0) {
600 const RegId& idx = inst->destRegIdx(start_idx);
601 switch (idx.classValue()) {
602 case IntRegClass:
603 panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
604 thread->setIntReg(idx.index(), mismatch_val.asInteger());
605 break;
606 case FloatRegClass:
607 panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
608 thread->setFloatReg(idx.index(), mismatch_val.asInteger());
609 break;
610 case VecRegClass:
611 panic_if(!mismatch_val.isVector(), "Unexpected type of result");
612 thread->setVecReg(idx, mismatch_val.asVector());
613 break;
614 case VecElemClass:
615 panic_if(!mismatch_val.isVecElem(),
616 "Unexpected type of result");
617 thread->setVecElem(idx, mismatch_val.asVectorElem());
618 break;
619 case CCRegClass:
620 panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
621 thread->setCCReg(idx.index(), mismatch_val.asInteger());
622 break;
623 case MiscRegClass:
624 panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
625 thread->setMiscReg(idx.index(), mismatch_val.asInteger());
626 break;
627 default:
628 panic("Unknown register class: %d", (int)idx.classValue());
629 }
630 }
631 start_idx++;
632 InstResult res;
633 for (int i = start_idx; i < inst->numDestRegs(); i++) {
634 const RegId& idx = inst->destRegIdx(i);
635 res = inst->popResult();
636 switch (idx.classValue()) {
637 case IntRegClass:
638 panic_if(!res.isScalar(), "Unexpected type of result");
639 thread->setIntReg(idx.index(), res.asInteger());
640 break;
641 case FloatRegClass:
642 panic_if(!res.isScalar(), "Unexpected type of result");
643 thread->setFloatReg(idx.index(), res.asInteger());
644 break;
645 case VecRegClass:
646 panic_if(!res.isVector(), "Unexpected type of result");
647 thread->setVecReg(idx, res.asVector());
648 break;
649 case VecElemClass:
650 panic_if(!res.isVecElem(), "Unexpected type of result");
651 thread->setVecElem(idx, res.asVectorElem());
652 break;
653 case CCRegClass:
654 panic_if(!res.isScalar(), "Unexpected type of result");
655 thread->setCCReg(idx.index(), res.asInteger());
656 break;
657 case MiscRegClass:
658 panic_if(res.isValid(), "MiscReg expecting invalid result");
659 // Try to get the proper misc register index for ARM here...
660 thread->setMiscReg(idx.index(), 0);
661 break;
662 // else Register is out of range...
663 default:
664 panic("Unknown register class: %d", (int)idx.classValue());
665 }
666 }
667 }
668
669 template <class Impl>
670 void
671 Checker<Impl>::dumpAndExit(const DynInstPtr &inst)
672 {
673 cprintf("Error detected, instruction information:\n");
674 cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
675 "Completed:%i\n",
676 inst->pcState(),
677 inst->nextInstAddr(),
678 inst->seqNum,
679 inst->threadNumber,
680 inst->isCompleted());
681 inst->dump();
682 CheckerCPU::dumpAndExit();
683 }
684
685 template <class Impl>
686 void
687 Checker<Impl>::dumpInsts()
688 {
689 int num = 0;
690
691 InstListIt inst_list_it = --(instList.end());
692
693 cprintf("Inst list size: %i\n", instList.size());
694
695 while (inst_list_it != instList.end())
696 {
697 cprintf("Instruction:%i\n",
698 num);
699
700 cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
701 "Completed:%i\n",
702 (*inst_list_it)->pcState(),
703 (*inst_list_it)->seqNum,
704 (*inst_list_it)->threadNumber,
705 (*inst_list_it)->isCompleted());
706
707 cprintf("\n");
708
709 inst_list_it--;
710 ++num;
711 }
712
713 }
714
715 #endif//__CPU_CHECKER_CPU_IMPL_HH__