src/cpu/checker/cpu_impl.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include <list>
  32 #include <string>
  33
  34 #include "base/refcnt.hh"
  35 #include "cpu/base_dyn_inst.hh"
  36 #include "cpu/checker/cpu.hh"
  37 #include "cpu/simple_thread.hh"
  38 #include "cpu/thread_context.hh"
  39 #include "cpu/static_inst.hh"
  40 #include "sim/sim_object.hh"
  41 #include "sim/stats.hh"
  42
  43 #if FULL_SYSTEM
  44 #include "arch/vtophys.hh"
  45 #endif // FULL_SYSTEM
  46
  47 using namespace std;
  48 //The CheckerCPU does alpha only
  49 using namespace AlphaISA;
  50
  51 template <class DynInstPtr>
  52 void
  53 Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
  54 {
  55     DynInstPtr inst;
  56
  57     // Either check this instruction, or add it to a list of
  58     // instructions waiting to be checked.  Instructions must be
  59     // checked in program order, so if a store has committed yet not
  60     // completed, there may be some instructions that are waiting
  61     // behind it that have completed and must be checked.
  62     if (!instList.empty()) {
  63         if (youngestSN < completed_inst->seqNum) {
  64             DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
  65                     completed_inst->seqNum, completed_inst->readPC());
  66             instList.push_back(completed_inst);
  67             youngestSN = completed_inst->seqNum;
  68         }
  69
  70         if (!instList.front()->isCompleted()) {
  71             return;
  72         } else {
  73             inst = instList.front();
  74             instList.pop_front();
  75         }
  76     } else {
  77         if (!completed_inst->isCompleted()) {
  78             if (youngestSN < completed_inst->seqNum) {
  79                 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
  80                         completed_inst->seqNum, completed_inst->readPC());
  81                 instList.push_back(completed_inst);
  82                 youngestSN = completed_inst->seqNum;
  83             }
  84             return;
  85         } else {
  86             if (youngestSN < completed_inst->seqNum) {
  87                 inst = completed_inst;
  88                 youngestSN = completed_inst->seqNum;
  89             } else {
  90                 return;
  91             }
  92         }
  93     }
  94
  95     unverifiedInst = inst;
  96
  97     // Try to check all instructions that are completed, ending if we
  98     // run out of instructions to check or if an instruction is not
  99     // yet completed.
 100     while (1) {
 101         DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
 102                 inst->seqNum, inst->readPC());
 103         unverifiedResult.integer = inst->readIntResult();
 104         unverifiedReq = inst->req;
 105         unverifiedMemData = inst->memData;
 106         numCycles++;
 107
 108         Fault fault = NoFault;
 109
 110         // maintain $r0 semantics
 111         thread->setIntReg(ZeroReg, 0);
 112 #ifdef TARGET_ALPHA
 113         thread->setFloatRegDouble(ZeroReg, 0.0);
 114 #endif // TARGET_ALPHA
 115
 116         // Check if any recent PC changes match up with anything we
 117         // expect to happen.  This is mostly to check if traps or
 118         // PC-based events have occurred in both the checker and CPU.
 119         if (changedPC) {
 120             DPRINTF(Checker, "Changed PC recently to %#x\n",
 121                     thread->readPC());
 122             if (willChangePC) {
 123                 if (newPC == thread->readPC()) {
 124                     DPRINTF(Checker, "Changed PC matches expected PC\n");
 125                 } else {
 126                     warn("%lli: Changed PC does not match expected PC, "
 127                          "changed: %#x, expected: %#x",
 128                          curTick, thread->readPC(), newPC);
 129                     CheckerCPU::handleError();
 130                 }
 131                 willChangePC = false;
 132             }
 133             changedPC = false;
 134         }
 135         if (changedNextPC) {
 136             DPRINTF(Checker, "Changed NextPC recently to %#x\n",
 137                     thread->readNextPC());
 138             changedNextPC = false;
 139         }
 140
 141         // Try to fetch the instruction
 142
 143 #if FULL_SYSTEM
 144 #define IFETCH_FLAGS(pc)        ((pc) & 1) ? PHYSICAL : 0
 145 #else
 146 #define IFETCH_FLAGS(pc)        0
 147 #endif
 148
 149         uint64_t fetch_PC = thread->readPC() & ~3;
 150
 151         // set up memory request for instruction fetch
 152         memReq = new Request(inst->threadNumber, fetch_PC,
 153                              sizeof(uint32_t),
 154                              IFETCH_FLAGS(thread->readPC()),
 155                              fetch_PC, thread->readCpuId(), inst->threadNumber);
 156
 157         bool succeeded = translateInstReq(memReq);
 158
 159         if (!succeeded) {
 160             if (inst->getFault() == NoFault) {
 161                 // In this case the instruction was not a dummy
 162                 // instruction carrying an ITB fault.  In the single
 163                 // threaded case the ITB should still be able to
 164                 // translate this instruction; in the SMT case it's
 165                 // possible that its ITB entry was kicked out.
 166                 warn("%lli: Instruction PC %#x was not found in the ITB!",
 167                      curTick, thread->readPC());
 168                 handleError(inst);
 169
 170                 // go to the next instruction
 171                 thread->setPC(thread->readNextPC());
 172                 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
 173
 174                 break;
 175             } else {
 176                 // The instruction is carrying an ITB fault.  Handle
 177                 // the fault and see if our results match the CPU on
 178                 // the next tick().
 179                 fault = inst->getFault();
 180             }
 181         }
 182
 183         if (fault == NoFault) {
 184             PacketPtr pkt = new Packet(memReq, Packet::ReadReq,
 185                                      Packet::Broadcast);
 186
 187             pkt->dataStatic(&machInst);
 188
 189             icachePort->sendFunctional(pkt);
 190
 191             delete pkt;
 192
 193             // keep an instruction count
 194             numInst++;
 195
 196             // decode the instruction
 197             machInst = gtoh(machInst);
 198             // Checks that the instruction matches what we expected it to be.
 199             // Checks both the machine instruction and the PC.
 200             validateInst(inst);
 201
 202 #if THE_ISA == ALPHA_ISA
 203             curStaticInst = StaticInst::decode(makeExtMI(machInst,
 204                                                          thread->readPC()));
 205 #elif THE_ISA == SPARC_ISA
 206             curStaticInst = StaticInst::decode(makeExtMI(machInst,
 207                                                          thread->getTC()));
 208 #endif
 209
 210 #if FULL_SYSTEM
 211             thread->setInst(machInst);
 212 #endif // FULL_SYSTEM
 213
 214             fault = inst->getFault();
 215         }
 216
 217         // Discard fetch's memReq.
 218         delete memReq;
 219         memReq = NULL;
 220
 221         // Either the instruction was a fault and we should process the fault,
 222         // or we should just go ahead execute the instruction.  This assumes
 223         // that the instruction is properly marked as a fault.
 224         if (fault == NoFault) {
 225
 226             thread->funcExeInst++;
 227
 228             if (!inst->isUnverifiable())
 229                 fault = curStaticInst->execute(this, NULL);
 230
 231             // Checks to make sure instrution results are correct.
 232             validateExecution(inst);
 233
 234             if (curStaticInst->isLoad()) {
 235                 ++numLoad;
 236             }
 237         }
 238
 239         if (fault != NoFault) {
 240 #if FULL_SYSTEM
 241             fault->invoke(tc);
 242             willChangePC = true;
 243             newPC = thread->readPC();
 244             DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
 245 #endif
 246         } else {
 247 #if THE_ISA != MIPS_ISA
 248             // go to the next instruction
 249             thread->setPC(thread->readNextPC());
 250             thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
 251 #else
 252             // go to the next instruction
 253             thread->setPC(thread->readNextPC());
 254             thread->setNextPC(thread->readNextNPC());
 255             thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
 256 #endif
 257
 258         }
 259
 260 #if FULL_SYSTEM
 261         // @todo: Determine if these should happen only if the
 262         // instruction hasn't faulted.  In the SimpleCPU case this may
 263         // not be true, but in the O3 or Ozone case this may be true.
 264         Addr oldpc;
 265         int count = 0;
 266         do {
 267             oldpc = thread->readPC();
 268             system->pcEventQueue.service(tc);
 269             count++;
 270         } while (oldpc != thread->readPC());
 271         if (count > 1) {
 272             willChangePC = true;
 273             newPC = thread->readPC();
 274             DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
 275         }
 276 #endif
 277
 278         // @todo:  Optionally can check all registers. (Or just those
 279         // that have been modified).
 280         validateState();
 281
 282         if (memReq) {
 283             delete memReq;
 284             memReq = NULL;
 285         }
 286
 287         // Continue verifying instructions if there's another completed
 288         // instruction waiting to be verified.
 289         if (instList.empty()) {
 290             break;
 291         } else if (instList.front()->isCompleted()) {
 292             inst = instList.front();
 293             instList.pop_front();
 294         } else {
 295             break;
 296         }
 297     }
 298     unverifiedInst = NULL;
 299 }
 300
 301 template <class DynInstPtr>
 302 void
 303 Checker<DynInstPtr>::switchOut()
 304 {
 305     instList.clear();
 306 }
 307
 308 template <class DynInstPtr>
 309 void
 310 Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
 311 {
 312 }
 313
 314 template <class DynInstPtr>
 315 void
 316 Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
 317 {
 318     if (inst->readPC() != thread->readPC()) {
 319         warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
 320              curTick, inst->readPC(), thread->readPC());
 321         if (changedPC) {
 322             warn("%lli: Changed PCs recently, may not be an error",
 323                  curTick);
 324         } else {
 325             handleError(inst);
 326         }
 327     }
 328
 329     MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
 330
 331     if (mi != machInst) {
 332         warn("%lli: Binary instructions do not match! Inst: %#x, "
 333              "checker: %#x",
 334              curTick, mi, machInst);
 335         handleError(inst);
 336     }
 337 }
 338
 339 template <class DynInstPtr>
 340 void
 341 Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
 342 {
 343     bool result_mismatch = false;
 344     if (inst->numDestRegs()) {
 345         // @todo: Support more destination registers.
 346         if (inst->isUnverifiable()) {
 347             // Unverifiable instructions assume they were executed
 348             // properly by the CPU. Grab the result from the
 349             // instruction and write it to the register.
 350             copyResult(inst);
 351         } else if (result.integer != inst->readIntResult()) {
 352             result_mismatch = true;
 353         }
 354     }
 355
 356     if (result_mismatch) {
 357         warn("%lli: Instruction results do not match! (Values may not "
 358              "actually be integers) Inst: %#x, checker: %#x",
 359              curTick, inst->readIntResult(), result.integer);
 360
 361         // It's useful to verify load values from memory, but in MP
 362         // systems the value obtained at execute may be different than
 363         // the value obtained at completion.  Similarly DMA can
 364         // present the same problem on even UP systems.  Thus there is
 365         // the option to only warn on loads having a result error.
 366         if (inst->isLoad() && warnOnlyOnLoadError) {
 367             copyResult(inst);
 368         } else {
 369             handleError(inst);
 370         }
 371     }
 372
 373     if (inst->readNextPC() != thread->readNextPC()) {
 374         warn("%lli: Instruction next PCs do not match! Inst: %#x, "
 375              "checker: %#x",
 376              curTick, inst->readNextPC(), thread->readNextPC());
 377         handleError(inst);
 378     }
 379
 380     // Checking side effect registers can be difficult if they are not
 381     // checked simultaneously with the execution of the instruction.
 382     // This is because other valid instructions may have modified
 383     // these registers in the meantime, and their values are not
 384     // stored within the DynInst.
 385     while (!miscRegIdxs.empty()) {
 386         int misc_reg_idx = miscRegIdxs.front();
 387         miscRegIdxs.pop();
 388
 389         if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
 390             thread->readMiscRegNoEffect(misc_reg_idx)) {
 391             warn("%lli: Misc reg idx %i (side effect) does not match! "
 392                  "Inst: %#x, checker: %#x",
 393                  curTick, misc_reg_idx,
 394                  inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
 395                  thread->readMiscRegNoEffect(misc_reg_idx));
 396             handleError(inst);
 397         }
 398     }
 399 }
 400
 401 template <class DynInstPtr>
 402 void
 403 Checker<DynInstPtr>::validateState()
 404 {
 405     if (updateThisCycle) {
 406         warn("%lli: Instruction PC %#x results didn't match up, copying all "
 407              "registers from main CPU", curTick, unverifiedInst->readPC());
 408         // Heavy-weight copying of all registers
 409         thread->copyArchRegs(unverifiedInst->tcBase());
 410         // Also advance the PC.  Hopefully no PC-based events happened.
 411 #if THE_ISA != MIPS_ISA
 412         // go to the next instruction
 413         thread->setPC(thread->readNextPC());
 414         thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
 415 #else
 416         // go to the next instruction
 417         thread->setPC(thread->readNextPC());
 418         thread->setNextPC(thread->readNextNPC());
 419         thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
 420 #endif
 421         updateThisCycle = false;
 422     }
 423 }
 424
 425 template <class DynInstPtr>
 426 void
 427 Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
 428 {
 429     RegIndex idx = inst->destRegIdx(0);
 430     if (idx < TheISA::FP_Base_DepTag) {
 431         thread->setIntReg(idx, inst->readIntResult());
 432     } else if (idx < TheISA::Fpcr_DepTag) {
 433         thread->setFloatRegBits(idx, inst->readIntResult());
 434     } else {
 435         thread->setMiscRegNoEffect(idx, inst->readIntResult());
 436     }
 437 }
 438
 439 template <class DynInstPtr>
 440 void
 441 Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
 442 {
 443     cprintf("Error detected, instruction information:\n");
 444     cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
 445             "Completed:%i\n",
 446             inst->readPC(),
 447             inst->readNextPC(),
 448             inst->seqNum,
 449             inst->threadNumber,
 450             inst->isCompleted());
 451     inst->dump();
 452     CheckerCPU::dumpAndExit();
 453 }
 454
 455 template <class DynInstPtr>
 456 void
 457 Checker<DynInstPtr>::dumpInsts()
 458 {
 459     int num = 0;
 460
 461     InstListIt inst_list_it = --(instList.end());
 462
 463     cprintf("Inst list size: %i\n", instList.size());
 464
 465     while (inst_list_it != instList.end())
 466     {
 467         cprintf("Instruction:%i\n",
 468                 num);
 469
 470         cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
 471                 "Completed:%i\n",
 472                 (*inst_list_it)->readPC(),
 473                 (*inst_list_it)->seqNum,
 474                 (*inst_list_it)->threadNumber,
 475                 (*inst_list_it)->isCompleted());
 476
 477         cprintf("\n");
 478
 479         inst_list_it--;
 480         ++num;
 481     }
 482
 483 }