src/cpu/checker/cpu_impl.hh

   1 /*
   2  * Copyright (c) 2011, 2016 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
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  21  * notice, this list of conditions and the following disclaimer;
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  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_CHECKER_CPU_IMPL_HH__
  43 #define __CPU_CHECKER_CPU_IMPL_HH__
  44
  45 #include <list>
  46 #include <string>
  47
  48 #include "arch/isa_traits.hh"
  49 #include "base/refcnt.hh"
  50 #include "config/the_isa.hh"
  51 #include "cpu/base_dyn_inst.hh"
  52 #include "cpu/exetrace.hh"
  53 #include "cpu/reg_class.hh"
  54 #include "cpu/simple_thread.hh"
  55 #include "cpu/static_inst.hh"
  56 #include "cpu/thread_context.hh"
  57 #include "cpu/checker/cpu.hh"
  58 #include "debug/Checker.hh"
  59 #include "sim/full_system.hh"
  60 #include "sim/sim_object.hh"
  61 #include "sim/stats.hh"
  62
  63 using namespace std;
  64 using namespace TheISA;
  65
  66 template <class Impl>
  67 void
  68 Checker<Impl>::advancePC(const Fault &fault)
  69 {
  70     if (fault != NoFault) {
  71         curMacroStaticInst = StaticInst::nullStaticInstPtr;
  72         fault->invoke(tc, curStaticInst);
  73         thread->decoder.reset();
  74     } else {
  75         if (curStaticInst) {
  76             if (curStaticInst->isLastMicroop())
  77                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
  78             TheISA::PCState pcState = thread->pcState();
  79             TheISA::advancePC(pcState, curStaticInst);
  80             thread->pcState(pcState);
  81             DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
  82         }
  83     }
  84 }
  85 //////////////////////////////////////////////////
  86
  87 template <class Impl>
  88 void
  89 Checker<Impl>::handlePendingInt()
  90 {
  91     DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
  92                      thread->pcState(), instList.size());
  93     DynInstPtr boundaryInst = NULL;
  94     if (!instList.empty()) {
  95         // Set the instructions as completed and verify as much as possible.
  96         DynInstPtr inst;
  97         typename std::list<DynInstPtr>::iterator itr;
  98
  99         for (itr = instList.begin(); itr != instList.end(); itr++) {
 100             (*itr)->setCompleted();
 101         }
 102
 103         inst = instList.front();
 104         boundaryInst = instList.back();
 105         verify(inst); // verify the instructions
 106         inst = NULL;
 107     }
 108     if ((!boundaryInst && curMacroStaticInst &&
 109           curStaticInst->isDelayedCommit() &&
 110           !curStaticInst->isLastMicroop()) ||
 111         (boundaryInst && boundaryInst->isDelayedCommit() &&
 112          !boundaryInst->isLastMicroop())) {
 113         panic("%lli: Trying to take an interrupt in middle of "
 114               "a non-interuptable instruction!", curTick());
 115     }
 116     boundaryInst = NULL;
 117     thread->decoder.reset();
 118     curMacroStaticInst = StaticInst::nullStaticInstPtr;
 119 }
 120
 121 template <class Impl>
 122 void
 123 Checker<Impl>::verify(const DynInstPtr &completed_inst)
 124 {
 125     DynInstPtr inst;
 126
 127     // Make sure serializing instructions are actually
 128     // seen as serializing to commit. instList should be
 129     // empty in these cases.
 130     if ((completed_inst->isSerializing() ||
 131         completed_inst->isSerializeBefore()) &&
 132         (!instList.empty() ?
 133          (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
 134         panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
 135               " entering instList with other instructions\n", curTick(),
 136               completed_inst->seqNum, completed_inst->pcState());
 137     }
 138
 139     // Either check this instruction, or add it to a list of
 140     // instructions waiting to be checked.  Instructions must be
 141     // checked in program order, so if a store has committed yet not
 142     // completed, there may be some instructions that are waiting
 143     // behind it that have completed and must be checked.
 144     if (!instList.empty()) {
 145         if (youngestSN < completed_inst->seqNum) {
 146             DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
 147                     completed_inst->seqNum, completed_inst->pcState());
 148             instList.push_back(completed_inst);
 149             youngestSN = completed_inst->seqNum;
 150         }
 151
 152         if (!instList.front()->isCompleted()) {
 153             return;
 154         } else {
 155             inst = instList.front();
 156             instList.pop_front();
 157         }
 158     } else {
 159         if (!completed_inst->isCompleted()) {
 160             if (youngestSN < completed_inst->seqNum) {
 161                 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
 162                         completed_inst->seqNum, completed_inst->pcState());
 163                 instList.push_back(completed_inst);
 164                 youngestSN = completed_inst->seqNum;
 165             }
 166             return;
 167         } else {
 168             if (youngestSN < completed_inst->seqNum) {
 169                 inst = completed_inst;
 170                 youngestSN = completed_inst->seqNum;
 171             } else {
 172                 return;
 173             }
 174         }
 175     }
 176
 177     // Make sure a serializing instruction is actually seen as
 178     // serializing. instList should be empty here
 179     if (inst->isSerializeAfter() && !instList.empty()) {
 180         panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
 181              " exiting instList with other instructions\n", curTick(),
 182              completed_inst->seqNum, completed_inst->pcState());
 183     }
 184     unverifiedInst = inst;
 185     inst = NULL;
 186
 187     // Try to check all instructions that are completed, ending if we
 188     // run out of instructions to check or if an instruction is not
 189     // yet completed.
 190     while (1) {
 191         DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
 192                 unverifiedInst->seqNum, unverifiedInst->pcState());
 193         unverifiedReq = NULL;
 194         unverifiedReq = unverifiedInst->reqToVerify;
 195         unverifiedMemData = unverifiedInst->memData;
 196         // Make sure results queue is empty
 197         while (!result.empty()) {
 198             result.pop();
 199         }
 200         numCycles++;
 201
 202         Fault fault = NoFault;
 203
 204         // maintain $r0 semantics
 205         thread->setIntReg(ZeroReg, 0);
 206
 207         // Check if any recent PC changes match up with anything we
 208         // expect to happen.  This is mostly to check if traps or
 209         // PC-based events have occurred in both the checker and CPU.
 210         if (changedPC) {
 211             DPRINTF(Checker, "Changed PC recently to %s\n",
 212                     thread->pcState());
 213             if (willChangePC) {
 214                 if (newPCState == thread->pcState()) {
 215                     DPRINTF(Checker, "Changed PC matches expected PC\n");
 216                 } else {
 217                     warn("%lli: Changed PC does not match expected PC, "
 218                          "changed: %s, expected: %s",
 219                          curTick(), thread->pcState(), newPCState);
 220                     CheckerCPU::handleError();
 221                 }
 222                 willChangePC = false;
 223             }
 224             changedPC = false;
 225         }
 226
 227         // Try to fetch the instruction
 228         uint64_t fetchOffset = 0;
 229         bool fetchDone = false;
 230
 231         while (!fetchDone) {
 232             Addr fetch_PC = thread->instAddr();
 233             fetch_PC = (fetch_PC & PCMask) + fetchOffset;
 234
 235             MachInst machInst;
 236
 237             // If not in the middle of a macro instruction
 238             if (!curMacroStaticInst) {
 239                 // set up memory request for instruction fetch
 240                 auto mem_req = std::make_shared<Request>(
 241                     fetch_PC, sizeof(MachInst), 0, masterId, fetch_PC,
 242                     thread->contextId());
 243
 244                 mem_req->setVirt(fetch_PC, sizeof(MachInst),
 245                                  Request::INST_FETCH, masterId,
 246                                  thread->instAddr());
 247
 248                 fault = itb->translateFunctional(
 249                     mem_req, tc, BaseTLB::Execute);
 250
 251                 if (fault != NoFault) {
 252                     if (unverifiedInst->getFault() == NoFault) {
 253                         // In this case the instruction was not a dummy
 254                         // instruction carrying an ITB fault.  In the single
 255                         // threaded case the ITB should still be able to
 256                         // translate this instruction; in the SMT case it's
 257                         // possible that its ITB entry was kicked out.
 258                         warn("%lli: Instruction PC %s was not found in the "
 259                              "ITB!", curTick(), thread->pcState());
 260                         handleError(unverifiedInst);
 261
 262                         // go to the next instruction
 263                         advancePC(NoFault);
 264
 265                         // Give up on an ITB fault..
 266                         unverifiedInst = NULL;
 267                         return;
 268                     } else {
 269                         // The instruction is carrying an ITB fault.  Handle
 270                         // the fault and see if our results match the CPU on
 271                         // the next tick().
 272                         fault = unverifiedInst->getFault();
 273                         break;
 274                     }
 275                 } else {
 276                     PacketPtr pkt = new Packet(mem_req, MemCmd::ReadReq);
 277
 278                     pkt->dataStatic(&machInst);
 279                     icachePort->sendFunctional(pkt);
 280
 281                     delete pkt;
 282                 }
 283             }
 284
 285             if (fault == NoFault) {
 286                 TheISA::PCState pcState = thread->pcState();
 287
 288                 if (isRomMicroPC(pcState.microPC())) {
 289                     fetchDone = true;
 290                     curStaticInst = thread->decoder.fetchRomMicroop(
 291                             pcState.microPC(), nullptr);
 292                 } else if (!curMacroStaticInst) {
 293                     //We're not in the middle of a macro instruction
 294                     StaticInstPtr instPtr = nullptr;
 295
 296                     //Predecode, ie bundle up an ExtMachInst
 297                     //If more fetch data is needed, pass it in.
 298                     Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
 299                     thread->decoder.moreBytes(pcState, fetchPC, machInst);
 300
 301                     //If an instruction is ready, decode it.
 302                     //Otherwise, we'll have to fetch beyond the
 303                     //MachInst at the current pc.
 304                     if (thread->decoder.instReady()) {
 305                         fetchDone = true;
 306                         instPtr = thread->decoder.decode(pcState);
 307                         thread->pcState(pcState);
 308                     } else {
 309                         fetchDone = false;
 310                         fetchOffset += sizeof(TheISA::MachInst);
 311                     }
 312
 313                     //If we decoded an instruction and it's microcoded,
 314                     //start pulling out micro ops
 315                     if (instPtr && instPtr->isMacroop()) {
 316                         curMacroStaticInst = instPtr;
 317                         curStaticInst =
 318                             instPtr->fetchMicroop(pcState.microPC());
 319                     } else {
 320                         curStaticInst = instPtr;
 321                     }
 322                 } else {
 323                     // Read the next micro op from the macro-op
 324                     curStaticInst =
 325                         curMacroStaticInst->fetchMicroop(pcState.microPC());
 326                     fetchDone = true;
 327                 }
 328             }
 329         }
 330         // reset decoder on Checker
 331         thread->decoder.reset();
 332
 333         // Check Checker and CPU get same instruction, and record
 334         // any faults the CPU may have had.
 335         Fault unverifiedFault;
 336         if (fault == NoFault) {
 337             unverifiedFault = unverifiedInst->getFault();
 338
 339             // Checks that the instruction matches what we expected it to be.
 340             // Checks both the machine instruction and the PC.
 341             validateInst(unverifiedInst);
 342         }
 343
 344         // keep an instruction count
 345         numInst++;
 346
 347
 348         // Either the instruction was a fault and we should process the fault,
 349         // or we should just go ahead execute the instruction.  This assumes
 350         // that the instruction is properly marked as a fault.
 351         if (fault == NoFault) {
 352             // Execute Checker instruction and trace
 353             if (!unverifiedInst->isUnverifiable()) {
 354                 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
 355                                                            tc,
 356                                                            curStaticInst,
 357                                                            pcState(),
 358                                                            curMacroStaticInst);
 359                 fault = curStaticInst->execute(this, traceData);
 360                 if (traceData) {
 361                     traceData->dump();
 362                     delete traceData;
 363                 }
 364             }
 365
 366             if (fault == NoFault && unverifiedFault == NoFault) {
 367                 thread->funcExeInst++;
 368                 // Checks to make sure instrution results are correct.
 369                 validateExecution(unverifiedInst);
 370
 371                 if (curStaticInst->isLoad()) {
 372                     ++numLoad;
 373                 }
 374             } else if (fault != NoFault && unverifiedFault == NoFault) {
 375                 panic("%lli: sn: %lli at PC: %s took a fault in checker "
 376                       "but not in driver CPU\n", curTick(),
 377                       unverifiedInst->seqNum, unverifiedInst->pcState());
 378             } else if (fault == NoFault && unverifiedFault != NoFault) {
 379                 panic("%lli: sn: %lli at PC: %s took a fault in driver "
 380                       "CPU but not in checker\n", curTick(),
 381                       unverifiedInst->seqNum, unverifiedInst->pcState());
 382             }
 383         }
 384
 385         // Take any faults here
 386         if (fault != NoFault) {
 387             if (FullSystem) {
 388                 fault->invoke(tc, curStaticInst);
 389                 willChangePC = true;
 390                 newPCState = thread->pcState();
 391                 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
 392                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
 393             }
 394         } else {
 395            advancePC(fault);
 396         }
 397
 398         if (FullSystem) {
 399             // @todo: Determine if these should happen only if the
 400             // instruction hasn't faulted.  In the SimpleCPU case this may
 401             // not be true, but in the O3 case this may be true.
 402             Addr oldpc;
 403             int count = 0;
 404             do {
 405                 oldpc = thread->instAddr();
 406                 thread->pcEventQueue.service(oldpc, tc);
 407                 count++;
 408             } while (oldpc != thread->instAddr());
 409             if (count > 1) {
 410                 willChangePC = true;
 411                 newPCState = thread->pcState();
 412                 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
 413             }
 414         }
 415
 416         // @todo:  Optionally can check all registers. (Or just those
 417         // that have been modified).
 418         validateState();
 419
 420         // Continue verifying instructions if there's another completed
 421         // instruction waiting to be verified.
 422         if (instList.empty()) {
 423             break;
 424         } else if (instList.front()->isCompleted()) {
 425             unverifiedInst = NULL;
 426             unverifiedInst = instList.front();
 427             instList.pop_front();
 428         } else {
 429             break;
 430         }
 431     }
 432     unverifiedInst = NULL;
 433 }
 434
 435 template <class Impl>
 436 void
 437 Checker<Impl>::switchOut()
 438 {
 439     instList.clear();
 440 }
 441
 442 template <class Impl>
 443 void
 444 Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
 445 {
 446 }
 447
 448 template <class Impl>
 449 void
 450 Checker<Impl>::validateInst(const DynInstPtr &inst)
 451 {
 452     if (inst->instAddr() != thread->instAddr()) {
 453         warn("%lli: PCs do not match! Inst: %s, checker: %s",
 454              curTick(), inst->pcState(), thread->pcState());
 455         if (changedPC) {
 456             warn("%lli: Changed PCs recently, may not be an error",
 457                  curTick());
 458         } else {
 459             handleError(inst);
 460         }
 461     }
 462
 463     if (curStaticInst != inst->staticInst) {
 464         warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
 465                 curStaticInst->getName(), inst->staticInst->getName());
 466     }
 467 }
 468
 469 template <class Impl>
 470 void
 471 Checker<Impl>::validateExecution(const DynInstPtr &inst)
 472 {
 473     InstResult checker_val;
 474     InstResult inst_val;
 475     int idx = -1;
 476     bool result_mismatch = false;
 477     bool scalar_mismatch = false;
 478     bool vector_mismatch = false;
 479
 480     if (inst->isUnverifiable()) {
 481         // Unverifiable instructions assume they were executed
 482         // properly by the CPU. Grab the result from the
 483         // instruction and write it to the register.
 484         copyResult(inst, InstResult(0ul, InstResult::ResultType::Scalar), idx);
 485     } else if (inst->numDestRegs() > 0 && !result.empty()) {
 486         DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
 487                          inst->numDestRegs(), result.size());
 488         for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
 489             checker_val = result.front();
 490             result.pop();
 491             inst_val = inst->popResult(
 492                     InstResult(0ul, InstResult::ResultType::Scalar));
 493             if (checker_val != inst_val) {
 494                 result_mismatch = true;
 495                 idx = i;
 496                 scalar_mismatch = checker_val.isScalar();
 497                 vector_mismatch = checker_val.isVector();
 498                 panic_if(!(scalar_mismatch || vector_mismatch),
 499                         "Unknown type of result\n");
 500             }
 501         }
 502     } // Checker CPU checks all the saved results in the dyninst passed by
 503       // the cpu model being checked against the saved results present in
 504       // the static inst executed in the Checker.  Sometimes the number
 505       // of saved results differs between the dyninst and static inst, but
 506       // this is ok and not a bug.  May be worthwhile to try and correct this.
 507
 508     if (result_mismatch) {
 509         if (scalar_mismatch) {
 510             warn("%lli: Instruction results (%i) do not match! (Values may"
 511                  " not actually be integers) Inst: %#x, checker: %#x",
 512                  curTick(), idx, inst_val.asIntegerNoAssert(),
 513                  checker_val.asInteger());
 514         }
 515
 516         // It's useful to verify load values from memory, but in MP
 517         // systems the value obtained at execute may be different than
 518         // the value obtained at completion.  Similarly DMA can
 519         // present the same problem on even UP systems.  Thus there is
 520         // the option to only warn on loads having a result error.
 521         // The load/store queue in Detailed CPU can also cause problems
 522         // if load/store forwarding is allowed.
 523         if (inst->isLoad() && warnOnlyOnLoadError) {
 524             copyResult(inst, inst_val, idx);
 525         } else {
 526             handleError(inst);
 527         }
 528     }
 529
 530     if (inst->nextInstAddr() != thread->nextInstAddr()) {
 531         warn("%lli: Instruction next PCs do not match! Inst: %#x, "
 532              "checker: %#x",
 533              curTick(), inst->nextInstAddr(), thread->nextInstAddr());
 534         handleError(inst);
 535     }
 536
 537     // Checking side effect registers can be difficult if they are not
 538     // checked simultaneously with the execution of the instruction.
 539     // This is because other valid instructions may have modified
 540     // these registers in the meantime, and their values are not
 541     // stored within the DynInst.
 542     while (!miscRegIdxs.empty()) {
 543         int misc_reg_idx = miscRegIdxs.front();
 544         miscRegIdxs.pop();
 545
 546         if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
 547             thread->readMiscRegNoEffect(misc_reg_idx)) {
 548             warn("%lli: Misc reg idx %i (side effect) does not match! "
 549                  "Inst: %#x, checker: %#x",
 550                  curTick(), misc_reg_idx,
 551                  inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
 552                  thread->readMiscRegNoEffect(misc_reg_idx));
 553             handleError(inst);
 554         }
 555     }
 556 }
 557
 558
 559 // This function is weird, if it is called it means the Checker and
 560 // O3 have diverged, so panic is called for now.  It may be useful
 561 // to resynch states and continue if the divergence is a false positive
 562 template <class Impl>
 563 void
 564 Checker<Impl>::validateState()
 565 {
 566     if (updateThisCycle) {
 567         // Change this back to warn if divergences end up being false positives
 568         panic("%lli: Instruction PC %#x results didn't match up, copying all "
 569              "registers from main CPU", curTick(), unverifiedInst->instAddr());
 570
 571         // Terribly convoluted way to make sure O3 model does not implode
 572         bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
 573         unverifiedInst->thread->noSquashFromTC = true;
 574
 575         // Heavy-weight copying of all registers
 576         thread->copyArchRegs(unverifiedInst->tcBase());
 577         unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
 578
 579         // Set curStaticInst to unverifiedInst->staticInst
 580         curStaticInst = unverifiedInst->staticInst;
 581         // Also advance the PC.  Hopefully no PC-based events happened.
 582         advancePC(NoFault);
 583         updateThisCycle = false;
 584     }
 585 }
 586
 587 template <class Impl>
 588 void
 589 Checker<Impl>::copyResult(const DynInstPtr &inst,
 590                           const InstResult& mismatch_val, int start_idx)
 591 {
 592     // We've already popped one dest off the queue,
 593     // so do the fix-up then start with the next dest reg;
 594     if (start_idx >= 0) {
 595         const RegId& idx = inst->destRegIdx(start_idx);
 596         switch (idx.classValue()) {
 597           case IntRegClass:
 598             panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
 599             thread->setIntReg(idx.index(), mismatch_val.asInteger());
 600             break;
 601           case FloatRegClass:
 602             panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
 603             thread->setFloatReg(idx.index(), mismatch_val.asInteger());
 604             break;
 605           case VecRegClass:
 606             panic_if(!mismatch_val.isVector(), "Unexpected type of result");
 607             thread->setVecReg(idx, mismatch_val.asVector());
 608             break;
 609           case VecElemClass:
 610             panic_if(!mismatch_val.isVecElem(),
 611                      "Unexpected type of result");
 612             thread->setVecElem(idx, mismatch_val.asVectorElem());
 613             break;
 614           case CCRegClass:
 615             panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
 616             thread->setCCReg(idx.index(), mismatch_val.asInteger());
 617             break;
 618           case MiscRegClass:
 619             panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
 620             thread->setMiscReg(idx.index(), mismatch_val.asInteger());
 621             break;
 622           default:
 623             panic("Unknown register class: %d", (int)idx.classValue());
 624         }
 625     }
 626     start_idx++;
 627     InstResult res;
 628     for (int i = start_idx; i < inst->numDestRegs(); i++) {
 629         const RegId& idx = inst->destRegIdx(i);
 630         res = inst->popResult();
 631         switch (idx.classValue()) {
 632           case IntRegClass:
 633             panic_if(!res.isScalar(), "Unexpected type of result");
 634             thread->setIntReg(idx.index(), res.asInteger());
 635             break;
 636           case FloatRegClass:
 637             panic_if(!res.isScalar(), "Unexpected type of result");
 638             thread->setFloatReg(idx.index(), res.asInteger());
 639             break;
 640           case VecRegClass:
 641             panic_if(!res.isVector(), "Unexpected type of result");
 642             thread->setVecReg(idx, res.asVector());
 643             break;
 644           case VecElemClass:
 645             panic_if(!res.isVecElem(), "Unexpected type of result");
 646             thread->setVecElem(idx, res.asVectorElem());
 647             break;
 648           case CCRegClass:
 649             panic_if(!res.isScalar(), "Unexpected type of result");
 650             thread->setCCReg(idx.index(), res.asInteger());
 651             break;
 652           case MiscRegClass:
 653             panic_if(res.isValid(), "MiscReg expecting invalid result");
 654             // Try to get the proper misc register index for ARM here...
 655             thread->setMiscReg(idx.index(), 0);
 656             break;
 657             // else Register is out of range...
 658           default:
 659             panic("Unknown register class: %d", (int)idx.classValue());
 660         }
 661     }
 662 }
 663
 664 template <class Impl>
 665 void
 666 Checker<Impl>::dumpAndExit(const DynInstPtr &inst)
 667 {
 668     cprintf("Error detected, instruction information:\n");
 669     cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
 670             "Completed:%i\n",
 671             inst->pcState(),
 672             inst->nextInstAddr(),
 673             inst->seqNum,
 674             inst->threadNumber,
 675             inst->isCompleted());
 676     inst->dump();
 677     CheckerCPU::dumpAndExit();
 678 }
 679
 680 template <class Impl>
 681 void
 682 Checker<Impl>::dumpInsts()
 683 {
 684     int num = 0;
 685
 686     InstListIt inst_list_it = --(instList.end());
 687
 688     cprintf("Inst list size: %i\n", instList.size());
 689
 690     while (inst_list_it != instList.end())
 691     {
 692         cprintf("Instruction:%i\n",
 693                 num);
 694
 695         cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
 696                 "Completed:%i\n",
 697                 (*inst_list_it)->pcState(),
 698                 (*inst_list_it)->seqNum,
 699                 (*inst_list_it)->threadNumber,
 700                 (*inst_list_it)->isCompleted());
 701
 702         cprintf("\n");
 703
 704         inst_list_it--;
 705         ++num;
 706     }
 707
 708 }
 709
 710 #endif//__CPU_CHECKER_CPU_IMPL_HH__