src/cpu/checker/thread_context.hh

   1 /*
   2  * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
  43 #define __CPU_CHECKER_THREAD_CONTEXT_HH__
  44
  45 #include "arch/types.hh"
  46 #include "config/the_isa.hh"
  47 #include "cpu/checker/cpu.hh"
  48 #include "cpu/simple_thread.hh"
  49 #include "cpu/thread_context.hh"
  50 #include "debug/Checker.hh"
  51
  52 namespace TheISA
  53 {
  54     class Decoder;
  55 } // namespace TheISA
  56
  57 /**
  58  * Derived ThreadContext class for use with the Checker.  The template
  59  * parameter is the ThreadContext class used by the specific CPU being
  60  * verified.  This CheckerThreadContext is then used by the main CPU
  61  * in place of its usual ThreadContext class.  It handles updating the
  62  * checker's state any time state is updated externally through the
  63  * ThreadContext.
  64  */
  65 template <class TC>
  66 class CheckerThreadContext : public ThreadContext
  67 {
  68   public:
  69     CheckerThreadContext(TC *actual_tc,
  70                          CheckerCPU *checker_cpu)
  71         : actualTC(actual_tc), checkerTC(checker_cpu->thread),
  72           checkerCPU(checker_cpu)
  73     { }
  74
  75   private:
  76     /** The main CPU's ThreadContext, or class that implements the
  77      * ThreadContext interface. */
  78     TC *actualTC;
  79     /** The checker's own SimpleThread. Will be updated any time
  80      * anything uses this ThreadContext to externally update a
  81      * thread's state. */
  82     SimpleThread *checkerTC;
  83     /** Pointer to the checker CPU. */
  84     CheckerCPU *checkerCPU;
  85
  86   public:
  87     bool schedule(PCEvent *e) override { return actualTC->schedule(e); }
  88     bool remove(PCEvent *e) override { return actualTC->remove(e); }
  89
  90     void
  91     scheduleInstCountEvent(Event *event, Tick count) override
  92     {
  93         actualTC->scheduleInstCountEvent(event, count);
  94     }
  95     void
  96     descheduleInstCountEvent(Event *event) override
  97     {
  98         actualTC->descheduleInstCountEvent(event);
  99     }
 100     Tick
 101     getCurrentInstCount() override
 102     {
 103         return actualTC->getCurrentInstCount();
 104     }
 105
 106     BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
 107
 108     uint32_t socketId() const override { return actualTC->socketId(); }
 109
 110     int cpuId() const override { return actualTC->cpuId(); }
 111
 112     ContextID contextId() const override { return actualTC->contextId(); }
 113
 114     void
 115     setContextId(ContextID id) override
 116     {
 117        actualTC->setContextId(id);
 118        checkerTC->setContextId(id);
 119     }
 120
 121     /** Returns this thread's ID number. */
 122     int threadId() const override { return actualTC->threadId(); }
 123     void
 124     setThreadId(int id) override
 125     {
 126         checkerTC->setThreadId(id);
 127         actualTC->setThreadId(id);
 128     }
 129
 130     BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
 131
 132     BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
 133
 134     BaseMMU *getMMUPtr() override { return actualTC->getMMUPtr(); }
 135
 136     CheckerCPU *
 137     getCheckerCpuPtr() override
 138     {
 139         return checkerCPU;
 140     }
 141
 142     BaseISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
 143
 144     TheISA::Decoder *
 145     getDecoderPtr() override
 146     {
 147         return actualTC->getDecoderPtr();
 148     }
 149
 150     System *getSystemPtr() override { return actualTC->getSystemPtr(); }
 151
 152     Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
 153
 154     void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
 155
 156     PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
 157
 158     PortProxy &
 159     getVirtProxy() override
 160     {
 161         return actualTC->getVirtProxy();
 162     }
 163
 164     void
 165     initMemProxies(ThreadContext *tc) override
 166     {
 167         actualTC->initMemProxies(tc);
 168     }
 169
 170     void
 171     connectMemPorts(ThreadContext *tc)
 172     {
 173         actualTC->connectMemPorts(tc);
 174     }
 175
 176     Status status() const override { return actualTC->status(); }
 177
 178     void
 179     setStatus(Status new_status) override
 180     {
 181         actualTC->setStatus(new_status);
 182         checkerTC->setStatus(new_status);
 183     }
 184
 185     /// Set the status to Active.
 186     void activate() override { actualTC->activate(); }
 187
 188     /// Set the status to Suspended.
 189     void suspend() override { actualTC->suspend(); }
 190
 191     /// Set the status to Halted.
 192     void halt() override { actualTC->halt(); }
 193
 194     void
 195     takeOverFrom(ThreadContext *oldContext) override
 196     {
 197         actualTC->takeOverFrom(oldContext);
 198         checkerTC->copyState(oldContext);
 199     }
 200
 201     void
 202     regStats(const std::string &name) override
 203     {
 204         actualTC->regStats(name);
 205         checkerTC->regStats(name);
 206     }
 207
 208     Tick readLastActivate() override { return actualTC->readLastActivate(); }
 209     Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
 210
 211     // @todo: Do I need this?
 212     void
 213     copyArchRegs(ThreadContext *tc) override
 214     {
 215         actualTC->copyArchRegs(tc);
 216         checkerTC->copyArchRegs(tc);
 217     }
 218
 219     void
 220     clearArchRegs() override
 221     {
 222         actualTC->clearArchRegs();
 223         checkerTC->clearArchRegs();
 224     }
 225
 226     //
 227     // New accessors for new decoder.
 228     //
 229     RegVal
 230     readIntReg(RegIndex reg_idx) const override
 231     {
 232         return actualTC->readIntReg(reg_idx);
 233     }
 234
 235     RegVal
 236     readFloatReg(RegIndex reg_idx) const override
 237     {
 238         return actualTC->readFloatReg(reg_idx);
 239     }
 240
 241     const VecRegContainer &
 242     readVecReg (const RegId &reg) const override
 243     {
 244         return actualTC->readVecReg(reg);
 245     }
 246
 247     /**
 248      * Read vector register for modification, hierarchical indexing.
 249      */
 250     VecRegContainer &
 251     getWritableVecReg (const RegId &reg) override
 252     {
 253         return actualTC->getWritableVecReg(reg);
 254     }
 255
 256     /** Vector Register Lane Interfaces. */
 257     /** @{ */
 258     /** Reads source vector 8bit operand. */
 259     ConstVecLane8
 260     readVec8BitLaneReg(const RegId &reg) const override
 261     {
 262         return actualTC->readVec8BitLaneReg(reg);
 263     }
 264
 265     /** Reads source vector 16bit operand. */
 266     ConstVecLane16
 267     readVec16BitLaneReg(const RegId &reg) const override
 268     {
 269         return actualTC->readVec16BitLaneReg(reg);
 270     }
 271
 272     /** Reads source vector 32bit operand. */
 273     ConstVecLane32
 274     readVec32BitLaneReg(const RegId &reg) const override
 275     {
 276         return actualTC->readVec32BitLaneReg(reg);
 277     }
 278
 279     /** Reads source vector 64bit operand. */
 280     ConstVecLane64
 281     readVec64BitLaneReg(const RegId &reg) const override
 282     {
 283         return actualTC->readVec64BitLaneReg(reg);
 284     }
 285
 286     /** Write a lane of the destination vector register. */
 287     virtual void
 288     setVecLane(const RegId &reg,
 289                const LaneData<LaneSize::Byte> &val) override
 290     {
 291         return actualTC->setVecLane(reg, val);
 292     }
 293     virtual void
 294     setVecLane(const RegId &reg,
 295                const LaneData<LaneSize::TwoByte> &val) override
 296     {
 297         return actualTC->setVecLane(reg, val);
 298     }
 299     virtual void
 300     setVecLane(const RegId &reg,
 301                const LaneData<LaneSize::FourByte> &val) override
 302     {
 303         return actualTC->setVecLane(reg, val);
 304     }
 305     virtual void
 306     setVecLane(const RegId &reg,
 307                const LaneData<LaneSize::EightByte> &val) override
 308     {
 309         return actualTC->setVecLane(reg, val);
 310     }
 311     /** @} */
 312
 313     const VecElem &
 314     readVecElem(const RegId& reg) const override
 315     {
 316         return actualTC->readVecElem(reg);
 317     }
 318
 319     const VecPredRegContainer &
 320     readVecPredReg(const RegId& reg) const override
 321     {
 322         return actualTC->readVecPredReg(reg);
 323     }
 324
 325     VecPredRegContainer &
 326     getWritableVecPredReg(const RegId& reg) override
 327     {
 328         return actualTC->getWritableVecPredReg(reg);
 329     }
 330
 331     RegVal
 332     readCCReg(RegIndex reg_idx) const override
 333     {
 334         return actualTC->readCCReg(reg_idx);
 335     }
 336
 337     void
 338     setIntReg(RegIndex reg_idx, RegVal val) override
 339     {
 340         actualTC->setIntReg(reg_idx, val);
 341         checkerTC->setIntReg(reg_idx, val);
 342     }
 343
 344     void
 345     setFloatReg(RegIndex reg_idx, RegVal val) override
 346     {
 347         actualTC->setFloatReg(reg_idx, val);
 348         checkerTC->setFloatReg(reg_idx, val);
 349     }
 350
 351     void
 352     setVecReg(const RegId& reg, const VecRegContainer& val) override
 353     {
 354         actualTC->setVecReg(reg, val);
 355         checkerTC->setVecReg(reg, val);
 356     }
 357
 358     void
 359     setVecElem(const RegId& reg, const VecElem& val) override
 360     {
 361         actualTC->setVecElem(reg, val);
 362         checkerTC->setVecElem(reg, val);
 363     }
 364
 365     void
 366     setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override
 367     {
 368         actualTC->setVecPredReg(reg, val);
 369         checkerTC->setVecPredReg(reg, val);
 370     }
 371
 372     void
 373     setCCReg(RegIndex reg_idx, RegVal val) override
 374     {
 375         actualTC->setCCReg(reg_idx, val);
 376         checkerTC->setCCReg(reg_idx, val);
 377     }
 378
 379     /** Reads this thread's PC state. */
 380     TheISA::PCState pcState() const override { return actualTC->pcState(); }
 381
 382     /** Sets this thread's PC state. */
 383     void
 384     pcState(const TheISA::PCState &val) override
 385     {
 386         DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
 387                          val, checkerTC->pcState());
 388         checkerTC->pcState(val);
 389         checkerCPU->recordPCChange(val);
 390         return actualTC->pcState(val);
 391     }
 392
 393     void
 394     setNPC(Addr val)
 395     {
 396         checkerTC->setNPC(val);
 397         actualTC->setNPC(val);
 398     }
 399
 400     void
 401     pcStateNoRecord(const TheISA::PCState &val) override
 402     {
 403         return actualTC->pcState(val);
 404     }
 405
 406     /** Reads this thread's PC. */
 407     Addr instAddr() const override { return actualTC->instAddr(); }
 408
 409     /** Reads this thread's next PC. */
 410     Addr nextInstAddr() const override { return actualTC->nextInstAddr(); }
 411
 412     /** Reads this thread's next PC. */
 413     MicroPC microPC() const override { return actualTC->microPC(); }
 414
 415     RegVal
 416     readMiscRegNoEffect(RegIndex misc_reg) const override
 417     {
 418         return actualTC->readMiscRegNoEffect(misc_reg);
 419     }
 420
 421     RegVal
 422     readMiscReg(RegIndex misc_reg) override
 423     {
 424         return actualTC->readMiscReg(misc_reg);
 425     }
 426
 427     void
 428     setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
 429     {
 430         DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
 431                          " and O3..\n", misc_reg);
 432         checkerTC->setMiscRegNoEffect(misc_reg, val);
 433         actualTC->setMiscRegNoEffect(misc_reg, val);
 434     }
 435
 436     void
 437     setMiscReg(RegIndex misc_reg, RegVal val) override
 438     {
 439         DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
 440                          " and O3..\n", misc_reg);
 441         checkerTC->setMiscReg(misc_reg, val);
 442         actualTC->setMiscReg(misc_reg, val);
 443     }
 444
 445     RegId
 446     flattenRegId(const RegId& regId) const override
 447     {
 448         return actualTC->flattenRegId(regId);
 449     }
 450
 451     unsigned
 452     readStCondFailures() const override
 453     {
 454         return actualTC->readStCondFailures();
 455     }
 456
 457     void
 458     setStCondFailures(unsigned sc_failures) override
 459     {
 460         actualTC->setStCondFailures(sc_failures);
 461     }
 462
 463     Counter
 464     readFuncExeInst() const override
 465     {
 466         return actualTC->readFuncExeInst();
 467     }
 468
 469     RegVal
 470     readIntRegFlat(RegIndex idx) const override
 471     {
 472         return actualTC->readIntRegFlat(idx);
 473     }
 474
 475     void
 476     setIntRegFlat(RegIndex idx, RegVal val) override
 477     {
 478         actualTC->setIntRegFlat(idx, val);
 479     }
 480
 481     RegVal
 482     readFloatRegFlat(RegIndex idx) const override
 483     {
 484         return actualTC->readFloatRegFlat(idx);
 485     }
 486
 487     void
 488     setFloatRegFlat(RegIndex idx, RegVal val) override
 489     {
 490         actualTC->setFloatRegFlat(idx, val);
 491     }
 492
 493     const VecRegContainer &
 494     readVecRegFlat(RegIndex idx) const override
 495     {
 496         return actualTC->readVecRegFlat(idx);
 497     }
 498
 499     /**
 500      * Read vector register for modification, flat indexing.
 501      */
 502     VecRegContainer &
 503     getWritableVecRegFlat(RegIndex idx) override
 504     {
 505         return actualTC->getWritableVecRegFlat(idx);
 506     }
 507
 508     void
 509     setVecRegFlat(RegIndex idx, const VecRegContainer& val) override
 510     {
 511         actualTC->setVecRegFlat(idx, val);
 512     }
 513
 514     const VecElem &
 515     readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
 516     {
 517         return actualTC->readVecElemFlat(idx, elem_idx);
 518     }
 519
 520     void
 521     setVecElemFlat(RegIndex idx,
 522                    const ElemIndex& elem_idx, const VecElem& val) override
 523     {
 524         actualTC->setVecElemFlat(idx, elem_idx, val);
 525     }
 526
 527     const VecPredRegContainer &
 528     readVecPredRegFlat(RegIndex idx) const override
 529     {
 530         return actualTC->readVecPredRegFlat(idx);
 531     }
 532
 533     VecPredRegContainer &
 534     getWritableVecPredRegFlat(RegIndex idx) override
 535     {
 536         return actualTC->getWritableVecPredRegFlat(idx);
 537     }
 538
 539     void
 540     setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override
 541     {
 542         actualTC->setVecPredRegFlat(idx, val);
 543     }
 544
 545     RegVal
 546     readCCRegFlat(RegIndex idx) const override
 547     {
 548         return actualTC->readCCRegFlat(idx);
 549     }
 550
 551     void
 552     setCCRegFlat(RegIndex idx, RegVal val) override
 553     {
 554         actualTC->setCCRegFlat(idx, val);
 555     }
 556
 557     // hardware transactional memory
 558     void
 559     htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
 560     {
 561         panic("function not implemented");
 562     }
 563
 564     BaseHTMCheckpointPtr&
 565     getHtmCheckpointPtr() override
 566     {
 567         panic("function not implemented");
 568     }
 569
 570     void
 571     setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
 572     {
 573         panic("function not implemented");
 574     }
 575
 576 };
 577
 578 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__