src/cpu/checker/thread_context.hh

   1 /*
   2  * Copyright (c) 2011-2012, 2016 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  */
  43
  44 #ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
  45 #define __CPU_CHECKER_THREAD_CONTEXT_HH__
  46
  47 #include "arch/types.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/checker/cpu.hh"
  50 #include "cpu/simple_thread.hh"
  51 #include "cpu/thread_context.hh"
  52 #include "debug/Checker.hh"
  53
  54 class EndQuiesceEvent;
  55 namespace TheISA {
  56     namespace Kernel {
  57         class Statistics;
  58     };
  59     class Decoder;
  60 };
  61
  62 /**
  63  * Derived ThreadContext class for use with the Checker.  The template
  64  * parameter is the ThreadContext class used by the specific CPU being
  65  * verified.  This CheckerThreadContext is then used by the main CPU
  66  * in place of its usual ThreadContext class.  It handles updating the
  67  * checker's state any time state is updated externally through the
  68  * ThreadContext.
  69  */
  70 template <class TC>
  71 class CheckerThreadContext : public ThreadContext
  72 {
  73   public:
  74     CheckerThreadContext(TC *actual_tc,
  75                          CheckerCPU *checker_cpu)
  76         : actualTC(actual_tc), checkerTC(checker_cpu->thread),
  77           checkerCPU(checker_cpu)
  78     { }
  79
  80   private:
  81     /** The main CPU's ThreadContext, or class that implements the
  82      * ThreadContext interface. */
  83     TC *actualTC;
  84     /** The checker's own SimpleThread. Will be updated any time
  85      * anything uses this ThreadContext to externally update a
  86      * thread's state. */
  87     SimpleThread *checkerTC;
  88     /** Pointer to the checker CPU. */
  89     CheckerCPU *checkerCPU;
  90
  91   public:
  92
  93     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
  94
  95     uint32_t socketId() const { return actualTC->socketId(); }
  96
  97     int cpuId() const { return actualTC->cpuId(); }
  98
  99     ContextID contextId() const { return actualTC->contextId(); }
 100
 101     void setContextId(ContextID id)
 102     {
 103        actualTC->setContextId(id);
 104        checkerTC->setContextId(id);
 105     }
 106
 107     /** Returns this thread's ID number. */
 108     int threadId() const { return actualTC->threadId(); }
 109     void setThreadId(int id)
 110     {
 111         checkerTC->setThreadId(id);
 112         actualTC->setThreadId(id);
 113     }
 114
 115     BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
 116
 117     BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 118
 119     CheckerCPU *getCheckerCpuPtr()
 120     {
 121         return checkerCPU;
 122     }
 123
 124     TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
 125
 126     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 127
 128     TheISA::Kernel::Statistics *getKernelStats()
 129     { return actualTC->getKernelStats(); }
 130
 131     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 132
 133     void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
 134
 135     PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
 136
 137     FSTranslatingPortProxy &getVirtProxy()
 138     { return actualTC->getVirtProxy(); }
 139
 140     void initMemProxies(ThreadContext *tc)
 141     { actualTC->initMemProxies(tc); }
 142
 143     void connectMemPorts(ThreadContext *tc)
 144     {
 145         actualTC->connectMemPorts(tc);
 146     }
 147
 148     SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
 149
 150     /** Executes a syscall in SE mode. */
 151     void syscall(int64_t callnum, Fault *fault)
 152     { return actualTC->syscall(callnum, fault); }
 153
 154     Status status() const { return actualTC->status(); }
 155
 156     void setStatus(Status new_status)
 157     {
 158         actualTC->setStatus(new_status);
 159         checkerTC->setStatus(new_status);
 160     }
 161
 162     /// Set the status to Active.
 163     void activate() { actualTC->activate(); }
 164
 165     /// Set the status to Suspended.
 166     void suspend() { actualTC->suspend(); }
 167
 168     /// Set the status to Halted.
 169     void halt() { actualTC->halt(); }
 170
 171     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 172
 173     void takeOverFrom(ThreadContext *oldContext)
 174     {
 175         actualTC->takeOverFrom(oldContext);
 176         checkerTC->copyState(oldContext);
 177     }
 178
 179     void regStats(const std::string &name)
 180     {
 181         actualTC->regStats(name);
 182         checkerTC->regStats(name);
 183     }
 184
 185     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 186
 187     Tick readLastActivate() { return actualTC->readLastActivate(); }
 188     Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 189
 190     void profileClear() { return actualTC->profileClear(); }
 191     void profileSample() { return actualTC->profileSample(); }
 192
 193     // @todo: Do I need this?
 194     void copyArchRegs(ThreadContext *tc)
 195     {
 196         actualTC->copyArchRegs(tc);
 197         checkerTC->copyArchRegs(tc);
 198     }
 199
 200     void clearArchRegs()
 201     {
 202         actualTC->clearArchRegs();
 203         checkerTC->clearArchRegs();
 204     }
 205
 206     //
 207     // New accessors for new decoder.
 208     //
 209     uint64_t readIntReg(int reg_idx)
 210     { return actualTC->readIntReg(reg_idx); }
 211
 212     FloatRegBits readFloatRegBits(int reg_idx)
 213     { return actualTC->readFloatRegBits(reg_idx); }
 214
 215     const VecRegContainer& readVecReg(const RegId& reg) const
 216     { return actualTC->readVecReg(reg); }
 217
 218     /**
 219      * Read vector register for modification, hierarchical indexing.
 220      */
 221     VecRegContainer& getWritableVecReg(const RegId& reg)
 222     { return actualTC->getWritableVecReg(reg); }
 223
 224     /** Vector Register Lane Interfaces. */
 225     /** @{ */
 226     /** Reads source vector 8bit operand. */
 227     ConstVecLane8
 228     readVec8BitLaneReg(const RegId& reg) const
 229     { return actualTC->readVec8BitLaneReg(reg); }
 230
 231     /** Reads source vector 16bit operand. */
 232     ConstVecLane16
 233     readVec16BitLaneReg(const RegId& reg) const
 234     { return actualTC->readVec16BitLaneReg(reg); }
 235
 236     /** Reads source vector 32bit operand. */
 237     ConstVecLane32
 238     readVec32BitLaneReg(const RegId& reg) const
 239     { return actualTC->readVec32BitLaneReg(reg); }
 240
 241     /** Reads source vector 64bit operand. */
 242     ConstVecLane64
 243     readVec64BitLaneReg(const RegId& reg) const
 244     { return actualTC->readVec64BitLaneReg(reg); }
 245
 246     /** Write a lane of the destination vector register. */
 247     virtual void setVecLane(const RegId& reg,
 248             const LaneData<LaneSize::Byte>& val)
 249     { return actualTC->setVecLane(reg, val); }
 250     virtual void setVecLane(const RegId& reg,
 251             const LaneData<LaneSize::TwoByte>& val)
 252     { return actualTC->setVecLane(reg, val); }
 253     virtual void setVecLane(const RegId& reg,
 254             const LaneData<LaneSize::FourByte>& val)
 255     { return actualTC->setVecLane(reg, val); }
 256     virtual void setVecLane(const RegId& reg,
 257             const LaneData<LaneSize::EightByte>& val)
 258     { return actualTC->setVecLane(reg, val); }
 259     /** @} */
 260
 261     const VecElem& readVecElem(const RegId& reg) const
 262     { return actualTC->readVecElem(reg); }
 263
 264     CCReg readCCReg(int reg_idx)
 265     { return actualTC->readCCReg(reg_idx); }
 266
 267     void setIntReg(int reg_idx, uint64_t val)
 268     {
 269         actualTC->setIntReg(reg_idx, val);
 270         checkerTC->setIntReg(reg_idx, val);
 271     }
 272
 273     void setFloatRegBits(int reg_idx, FloatRegBits val)
 274     {
 275         actualTC->setFloatRegBits(reg_idx, val);
 276         checkerTC->setFloatRegBits(reg_idx, val);
 277     }
 278
 279     void setVecReg(const RegId& reg, const VecRegContainer& val)
 280     {
 281         actualTC->setVecReg(reg, val);
 282         checkerTC->setVecReg(reg, val);
 283     }
 284
 285     void setVecElem(const RegId& reg, const VecElem& val)
 286     {
 287         actualTC->setVecElem(reg, val);
 288         checkerTC->setVecElem(reg, val);
 289     }
 290
 291     void setCCReg(int reg_idx, CCReg val)
 292     {
 293         actualTC->setCCReg(reg_idx, val);
 294         checkerTC->setCCReg(reg_idx, val);
 295     }
 296
 297     /** Reads this thread's PC state. */
 298     TheISA::PCState pcState()
 299     { return actualTC->pcState(); }
 300
 301     /** Sets this thread's PC state. */
 302     void pcState(const TheISA::PCState &val)
 303     {
 304         DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
 305                          val, checkerTC->pcState());
 306         checkerTC->pcState(val);
 307         checkerCPU->recordPCChange(val);
 308         return actualTC->pcState(val);
 309     }
 310
 311     void setNPC(Addr val)
 312     {
 313         checkerTC->setNPC(val);
 314         actualTC->setNPC(val);
 315     }
 316
 317     void pcStateNoRecord(const TheISA::PCState &val)
 318     {
 319         return actualTC->pcState(val);
 320     }
 321
 322     /** Reads this thread's PC. */
 323     Addr instAddr()
 324     { return actualTC->instAddr(); }
 325
 326     /** Reads this thread's next PC. */
 327     Addr nextInstAddr()
 328     { return actualTC->nextInstAddr(); }
 329
 330     /** Reads this thread's next PC. */
 331     MicroPC microPC()
 332     { return actualTC->microPC(); }
 333
 334     MiscReg readMiscRegNoEffect(int misc_reg) const
 335     { return actualTC->readMiscRegNoEffect(misc_reg); }
 336
 337     MiscReg readMiscReg(int misc_reg)
 338     { return actualTC->readMiscReg(misc_reg); }
 339
 340     void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 341     {
 342         DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
 343                          " and O3..\n", misc_reg);
 344         checkerTC->setMiscRegNoEffect(misc_reg, val);
 345         actualTC->setMiscRegNoEffect(misc_reg, val);
 346     }
 347
 348     void setMiscReg(int misc_reg, const MiscReg &val)
 349     {
 350         DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
 351                          " and O3..\n", misc_reg);
 352         checkerTC->setMiscReg(misc_reg, val);
 353         actualTC->setMiscReg(misc_reg, val);
 354     }
 355
 356     RegId flattenRegId(const RegId& regId) const {
 357         return actualTC->flattenRegId(regId);
 358     }
 359
 360     unsigned readStCondFailures()
 361     { return actualTC->readStCondFailures(); }
 362
 363     void setStCondFailures(unsigned sc_failures)
 364     {
 365         actualTC->setStCondFailures(sc_failures);
 366     }
 367
 368     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 369
 370     uint64_t readIntRegFlat(int idx)
 371     { return actualTC->readIntRegFlat(idx); }
 372
 373     void setIntRegFlat(int idx, uint64_t val)
 374     { actualTC->setIntRegFlat(idx, val); }
 375
 376     FloatRegBits readFloatRegBitsFlat(int idx)
 377     { return actualTC->readFloatRegBitsFlat(idx); }
 378
 379     void setFloatRegBitsFlat(int idx, FloatRegBits val)
 380     { actualTC->setFloatRegBitsFlat(idx, val); }
 381
 382     const VecRegContainer& readVecRegFlat(int idx) const
 383     { return actualTC->readVecRegFlat(idx); }
 384
 385     /**
 386      * Read vector register for modification, flat indexing.
 387      */
 388     VecRegContainer& getWritableVecRegFlat(int idx)
 389     { return actualTC->getWritableVecRegFlat(idx); }
 390
 391     void setVecRegFlat(int idx, const VecRegContainer& val)
 392     { actualTC->setVecRegFlat(idx, val); }
 393
 394     const VecElem& readVecElemFlat(const RegIndex& idx,
 395                                    const ElemIndex& elem_idx) const
 396     { return actualTC->readVecElemFlat(idx, elem_idx); }
 397
 398     void setVecElemFlat(const RegIndex& idx,
 399                         const ElemIndex& elem_idx, const VecElem& val)
 400     { actualTC->setVecElemFlat(idx, elem_idx, val); }
 401
 402     CCReg readCCRegFlat(int idx)
 403     { return actualTC->readCCRegFlat(idx); }
 404
 405     void setCCRegFlat(int idx, CCReg val)
 406     { actualTC->setCCRegFlat(idx, val); }
 407 };
 408
 409 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__