src/cpu/checker/thread_context.hh

   1 /*
   2  * Copyright (c) 2011-2012, 2016-2018 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  */
  43
  44 #ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
  45 #define __CPU_CHECKER_THREAD_CONTEXT_HH__
  46
  47 #include "arch/types.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/checker/cpu.hh"
  50 #include "cpu/simple_thread.hh"
  51 #include "cpu/thread_context.hh"
  52 #include "debug/Checker.hh"
  53
  54 class EndQuiesceEvent;
  55 namespace Kernel {
  56     class Statistics;
  57 };
  58 namespace TheISA {
  59     class Decoder;
  60 };
  61
  62 /**
  63  * Derived ThreadContext class for use with the Checker.  The template
  64  * parameter is the ThreadContext class used by the specific CPU being
  65  * verified.  This CheckerThreadContext is then used by the main CPU
  66  * in place of its usual ThreadContext class.  It handles updating the
  67  * checker's state any time state is updated externally through the
  68  * ThreadContext.
  69  */
  70 template <class TC>
  71 class CheckerThreadContext : public ThreadContext
  72 {
  73   public:
  74     CheckerThreadContext(TC *actual_tc,
  75                          CheckerCPU *checker_cpu)
  76         : actualTC(actual_tc), checkerTC(checker_cpu->thread),
  77           checkerCPU(checker_cpu)
  78     { }
  79
  80   private:
  81     /** The main CPU's ThreadContext, or class that implements the
  82      * ThreadContext interface. */
  83     TC *actualTC;
  84     /** The checker's own SimpleThread. Will be updated any time
  85      * anything uses this ThreadContext to externally update a
  86      * thread's state. */
  87     SimpleThread *checkerTC;
  88     /** Pointer to the checker CPU. */
  89     CheckerCPU *checkerCPU;
  90
  91   public:
  92     bool schedule(PCEvent *e) override { return actualTC->schedule(e); }
  93     bool remove(PCEvent *e) override { return actualTC->remove(e); }
  94
  95     Tick
  96     nextInstEventCount() override
  97     {
  98         return actualTC->nextInstEventCount();
  99     }
 100     void
 101     serviceInstCountEvents(Tick count) override
 102     {
 103         actualTC->serviceInstCountEvents(count);
 104     }
 105     void
 106     scheduleInstCountEvent(Event *event, Tick count) override
 107     {
 108         actualTC->scheduleInstCountEvent(event, count);
 109     }
 110     void
 111     descheduleInstCountEvent(Event *event) override
 112     {
 113         actualTC->descheduleInstCountEvent(event);
 114     }
 115     Tick getCurrentInstCount() override { return getCurrentInstCount(); }
 116
 117     BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
 118
 119     uint32_t socketId() const override { return actualTC->socketId(); }
 120
 121     int cpuId() const override { return actualTC->cpuId(); }
 122
 123     ContextID contextId() const override { return actualTC->contextId(); }
 124
 125     void
 126     setContextId(ContextID id) override
 127     {
 128        actualTC->setContextId(id);
 129        checkerTC->setContextId(id);
 130     }
 131
 132     /** Returns this thread's ID number. */
 133     int threadId() const override { return actualTC->threadId(); }
 134     void
 135     setThreadId(int id) override
 136     {
 137         checkerTC->setThreadId(id);
 138         actualTC->setThreadId(id);
 139     }
 140
 141     BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
 142
 143     BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
 144
 145     CheckerCPU *
 146     getCheckerCpuPtr() override
 147     {
 148         return checkerCPU;
 149     }
 150
 151     TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
 152
 153     TheISA::Decoder *
 154     getDecoderPtr() override
 155     {
 156         return actualTC->getDecoderPtr();
 157     }
 158
 159     System *getSystemPtr() override { return actualTC->getSystemPtr(); }
 160
 161     ::Kernel::Statistics *
 162     getKernelStats() override
 163     {
 164         return actualTC->getKernelStats();
 165     }
 166
 167     Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
 168
 169     void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
 170
 171     PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
 172
 173     PortProxy &
 174     getVirtProxy() override
 175     {
 176         return actualTC->getVirtProxy();
 177     }
 178
 179     void
 180     initMemProxies(ThreadContext *tc) override
 181     {
 182         actualTC->initMemProxies(tc);
 183     }
 184
 185     void
 186     connectMemPorts(ThreadContext *tc)
 187     {
 188         actualTC->connectMemPorts(tc);
 189     }
 190
 191     /** Executes a syscall in SE mode. */
 192     void
 193     syscall(int64_t callnum, Fault *fault) override
 194     {
 195         return actualTC->syscall(callnum, fault);
 196     }
 197
 198     Status status() const override { return actualTC->status(); }
 199
 200     void
 201     setStatus(Status new_status) override
 202     {
 203         actualTC->setStatus(new_status);
 204         checkerTC->setStatus(new_status);
 205     }
 206
 207     /// Set the status to Active.
 208     void activate() override { actualTC->activate(); }
 209
 210     /// Set the status to Suspended.
 211     void suspend() override { actualTC->suspend(); }
 212
 213     /// Set the status to Halted.
 214     void halt() override { actualTC->halt(); }
 215
 216     void dumpFuncProfile() override { actualTC->dumpFuncProfile(); }
 217
 218     void
 219     takeOverFrom(ThreadContext *oldContext) override
 220     {
 221         actualTC->takeOverFrom(oldContext);
 222         checkerTC->copyState(oldContext);
 223     }
 224
 225     void
 226     regStats(const std::string &name) override
 227     {
 228         actualTC->regStats(name);
 229         checkerTC->regStats(name);
 230     }
 231
 232     EndQuiesceEvent *
 233     getQuiesceEvent() override
 234     {
 235         return actualTC->getQuiesceEvent();
 236     }
 237
 238     Tick readLastActivate() override { return actualTC->readLastActivate(); }
 239     Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
 240
 241     void profileClear() override { return actualTC->profileClear(); }
 242     void profileSample() override { return actualTC->profileSample(); }
 243
 244     // @todo: Do I need this?
 245     void
 246     copyArchRegs(ThreadContext *tc) override
 247     {
 248         actualTC->copyArchRegs(tc);
 249         checkerTC->copyArchRegs(tc);
 250     }
 251
 252     void
 253     clearArchRegs() override
 254     {
 255         actualTC->clearArchRegs();
 256         checkerTC->clearArchRegs();
 257     }
 258
 259     //
 260     // New accessors for new decoder.
 261     //
 262     RegVal
 263     readIntReg(RegIndex reg_idx) const override
 264     {
 265         return actualTC->readIntReg(reg_idx);
 266     }
 267
 268     RegVal
 269     readFloatReg(RegIndex reg_idx) const override
 270     {
 271         return actualTC->readFloatReg(reg_idx);
 272     }
 273
 274     const VecRegContainer &
 275     readVecReg (const RegId &reg) const override
 276     {
 277         return actualTC->readVecReg(reg);
 278     }
 279
 280     /**
 281      * Read vector register for modification, hierarchical indexing.
 282      */
 283     VecRegContainer &
 284     getWritableVecReg (const RegId &reg) override
 285     {
 286         return actualTC->getWritableVecReg(reg);
 287     }
 288
 289     /** Vector Register Lane Interfaces. */
 290     /** @{ */
 291     /** Reads source vector 8bit operand. */
 292     ConstVecLane8
 293     readVec8BitLaneReg(const RegId &reg) const override
 294     {
 295         return actualTC->readVec8BitLaneReg(reg);
 296     }
 297
 298     /** Reads source vector 16bit operand. */
 299     ConstVecLane16
 300     readVec16BitLaneReg(const RegId &reg) const override
 301     {
 302         return actualTC->readVec16BitLaneReg(reg);
 303     }
 304
 305     /** Reads source vector 32bit operand. */
 306     ConstVecLane32
 307     readVec32BitLaneReg(const RegId &reg) const override
 308     {
 309         return actualTC->readVec32BitLaneReg(reg);
 310     }
 311
 312     /** Reads source vector 64bit operand. */
 313     ConstVecLane64
 314     readVec64BitLaneReg(const RegId &reg) const override
 315     {
 316         return actualTC->readVec64BitLaneReg(reg);
 317     }
 318
 319     /** Write a lane of the destination vector register. */
 320     virtual void
 321     setVecLane(const RegId &reg,
 322                const LaneData<LaneSize::Byte> &val) override
 323     {
 324         return actualTC->setVecLane(reg, val);
 325     }
 326     virtual void
 327     setVecLane(const RegId &reg,
 328                const LaneData<LaneSize::TwoByte> &val) override
 329     {
 330         return actualTC->setVecLane(reg, val);
 331     }
 332     virtual void
 333     setVecLane(const RegId &reg,
 334                const LaneData<LaneSize::FourByte> &val) override
 335     {
 336         return actualTC->setVecLane(reg, val);
 337     }
 338     virtual void
 339     setVecLane(const RegId &reg,
 340                const LaneData<LaneSize::EightByte> &val) override
 341     {
 342         return actualTC->setVecLane(reg, val);
 343     }
 344     /** @} */
 345
 346     const VecElem &
 347     readVecElem(const RegId& reg) const override
 348     {
 349         return actualTC->readVecElem(reg);
 350     }
 351
 352     const VecPredRegContainer &
 353     readVecPredReg(const RegId& reg) const override
 354     {
 355         return actualTC->readVecPredReg(reg);
 356     }
 357
 358     VecPredRegContainer &
 359     getWritableVecPredReg(const RegId& reg) override
 360     {
 361         return actualTC->getWritableVecPredReg(reg);
 362     }
 363
 364     RegVal
 365     readCCReg(RegIndex reg_idx) const override
 366     {
 367         return actualTC->readCCReg(reg_idx);
 368     }
 369
 370     void
 371     setIntReg(RegIndex reg_idx, RegVal val) override
 372     {
 373         actualTC->setIntReg(reg_idx, val);
 374         checkerTC->setIntReg(reg_idx, val);
 375     }
 376
 377     void
 378     setFloatReg(RegIndex reg_idx, RegVal val) override
 379     {
 380         actualTC->setFloatReg(reg_idx, val);
 381         checkerTC->setFloatReg(reg_idx, val);
 382     }
 383
 384     void
 385     setVecReg(const RegId& reg, const VecRegContainer& val) override
 386     {
 387         actualTC->setVecReg(reg, val);
 388         checkerTC->setVecReg(reg, val);
 389     }
 390
 391     void
 392     setVecElem(const RegId& reg, const VecElem& val) override
 393     {
 394         actualTC->setVecElem(reg, val);
 395         checkerTC->setVecElem(reg, val);
 396     }
 397
 398     void
 399     setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override
 400     {
 401         actualTC->setVecPredReg(reg, val);
 402         checkerTC->setVecPredReg(reg, val);
 403     }
 404
 405     void
 406     setCCReg(RegIndex reg_idx, RegVal val) override
 407     {
 408         actualTC->setCCReg(reg_idx, val);
 409         checkerTC->setCCReg(reg_idx, val);
 410     }
 411
 412     /** Reads this thread's PC state. */
 413     TheISA::PCState pcState() const override { return actualTC->pcState(); }
 414
 415     /** Sets this thread's PC state. */
 416     void
 417     pcState(const TheISA::PCState &val) override
 418     {
 419         DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
 420                          val, checkerTC->pcState());
 421         checkerTC->pcState(val);
 422         checkerCPU->recordPCChange(val);
 423         return actualTC->pcState(val);
 424     }
 425
 426     void
 427     setNPC(Addr val)
 428     {
 429         checkerTC->setNPC(val);
 430         actualTC->setNPC(val);
 431     }
 432
 433     void
 434     pcStateNoRecord(const TheISA::PCState &val) override
 435     {
 436         return actualTC->pcState(val);
 437     }
 438
 439     /** Reads this thread's PC. */
 440     Addr instAddr() const override { return actualTC->instAddr(); }
 441
 442     /** Reads this thread's next PC. */
 443     Addr nextInstAddr() const override { return actualTC->nextInstAddr(); }
 444
 445     /** Reads this thread's next PC. */
 446     MicroPC microPC() const override { return actualTC->microPC(); }
 447
 448     RegVal
 449     readMiscRegNoEffect(RegIndex misc_reg) const override
 450     {
 451         return actualTC->readMiscRegNoEffect(misc_reg);
 452     }
 453
 454     RegVal
 455     readMiscReg(RegIndex misc_reg) override
 456     {
 457         return actualTC->readMiscReg(misc_reg);
 458     }
 459
 460     void
 461     setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
 462     {
 463         DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
 464                          " and O3..\n", misc_reg);
 465         checkerTC->setMiscRegNoEffect(misc_reg, val);
 466         actualTC->setMiscRegNoEffect(misc_reg, val);
 467     }
 468
 469     void
 470     setMiscReg(RegIndex misc_reg, RegVal val) override
 471     {
 472         DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
 473                          " and O3..\n", misc_reg);
 474         checkerTC->setMiscReg(misc_reg, val);
 475         actualTC->setMiscReg(misc_reg, val);
 476     }
 477
 478     RegId
 479     flattenRegId(const RegId& regId) const override
 480     {
 481         return actualTC->flattenRegId(regId);
 482     }
 483
 484     unsigned
 485     readStCondFailures() const override
 486     {
 487         return actualTC->readStCondFailures();
 488     }
 489
 490     void
 491     setStCondFailures(unsigned sc_failures) override
 492     {
 493         actualTC->setStCondFailures(sc_failures);
 494     }
 495
 496     Counter
 497     readFuncExeInst() const override
 498     {
 499         return actualTC->readFuncExeInst();
 500     }
 501
 502     RegVal
 503     readIntRegFlat(RegIndex idx) const override
 504     {
 505         return actualTC->readIntRegFlat(idx);
 506     }
 507
 508     void
 509     setIntRegFlat(RegIndex idx, RegVal val) override
 510     {
 511         actualTC->setIntRegFlat(idx, val);
 512     }
 513
 514     RegVal
 515     readFloatRegFlat(RegIndex idx) const override
 516     {
 517         return actualTC->readFloatRegFlat(idx);
 518     }
 519
 520     void
 521     setFloatRegFlat(RegIndex idx, RegVal val) override
 522     {
 523         actualTC->setFloatRegFlat(idx, val);
 524     }
 525
 526     const VecRegContainer &
 527     readVecRegFlat(RegIndex idx) const override
 528     {
 529         return actualTC->readVecRegFlat(idx);
 530     }
 531
 532     /**
 533      * Read vector register for modification, flat indexing.
 534      */
 535     VecRegContainer &
 536     getWritableVecRegFlat(RegIndex idx) override
 537     {
 538         return actualTC->getWritableVecRegFlat(idx);
 539     }
 540
 541     void
 542     setVecRegFlat(RegIndex idx, const VecRegContainer& val) override
 543     {
 544         actualTC->setVecRegFlat(idx, val);
 545     }
 546
 547     const VecElem &
 548     readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
 549     {
 550         return actualTC->readVecElemFlat(idx, elem_idx);
 551     }
 552
 553     void
 554     setVecElemFlat(RegIndex idx,
 555                    const ElemIndex& elem_idx, const VecElem& val) override
 556     {
 557         actualTC->setVecElemFlat(idx, elem_idx, val);
 558     }
 559
 560     const VecPredRegContainer &
 561     readVecPredRegFlat(RegIndex idx) const override
 562     {
 563         return actualTC->readVecPredRegFlat(idx);
 564     }
 565
 566     VecPredRegContainer &
 567     getWritableVecPredRegFlat(RegIndex idx) override
 568     {
 569         return actualTC->getWritableVecPredRegFlat(idx);
 570     }
 571
 572     void
 573     setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override
 574     {
 575         actualTC->setVecPredRegFlat(idx, val);
 576     }
 577
 578     RegVal
 579     readCCRegFlat(RegIndex idx) const override
 580     {
 581         return actualTC->readCCRegFlat(idx);
 582     }
 583
 584     void
 585     setCCRegFlat(RegIndex idx, RegVal val) override
 586     {
 587         actualTC->setCCRegFlat(idx, val);
 588     }
 589 };
 590
 591 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__