2 * Copyright (c) 2006 The Regents of The University of Michigan
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31 #ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
32 #define __CPU_CHECKER_THREAD_CONTEXT_HH__
34 #include "arch/types.hh"
35 #include "config/the_isa.hh"
36 #include "cpu/checker/cpu.hh"
37 #include "cpu/simple_thread.hh"
38 #include "cpu/thread_context.hh"
40 class EndQuiesceEvent;
48 * Derived ThreadContext class for use with the Checker. The template
49 * parameter is the ThreadContext class used by the specific CPU being
50 * verified. This CheckerThreadContext is then used by the main CPU
51 * in place of its usual ThreadContext class. It handles updating the
52 * checker's state any time state is updated externally through the
56 class CheckerThreadContext : public ThreadContext
59 CheckerThreadContext(TC *actual_tc,
60 CheckerCPU *checker_cpu)
61 : actualTC(actual_tc), checkerTC(checker_cpu->thread),
62 checkerCPU(checker_cpu)
66 /** The main CPU's ThreadContext, or class that implements the
67 * ThreadContext interface. */
69 /** The checker's own SimpleThread. Will be updated any time
70 * anything uses this ThreadContext to externally update a
72 SimpleThread *checkerTC;
73 /** Pointer to the checker CPU. */
74 CheckerCPU *checkerCPU;
78 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
82 actualTC->setCpuId(id);
83 checkerTC->setCpuId(id);
86 int cpuId() { return actualTC->cpuId(); }
88 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
90 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
93 System *getSystemPtr() { return actualTC->getSystemPtr(); }
95 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
97 TheISA::Kernel::Statistics *getKernelStats()
98 { return actualTC->getKernelStats(); }
100 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
102 VirtualPort *getVirtPort()
103 { return actualTC->getVirtPort(); }
105 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
107 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
110 Status status() const { return actualTC->status(); }
112 void setStatus(Status new_status)
114 actualTC->setStatus(new_status);
115 checkerTC->setStatus(new_status);
118 /// Set the status to Active. Optional delay indicates number of
119 /// cycles to wait before beginning execution.
120 void activate(int delay = 1) { actualTC->activate(delay); }
122 /// Set the status to Suspended.
123 void suspend() { actualTC->suspend(); }
125 /// Set the status to Halted.
126 void halt() { actualTC->halt(); }
129 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
132 void takeOverFrom(ThreadContext *oldContext)
134 actualTC->takeOverFrom(oldContext);
135 checkerTC->copyState(oldContext);
138 void regStats(const std::string &name) { actualTC->regStats(name); }
140 void serialize(std::ostream &os) { actualTC->serialize(os); }
141 void unserialize(Checkpoint *cp, const std::string §ion)
142 { actualTC->unserialize(cp, section); }
145 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
147 Tick readLastActivate() { return actualTC->readLastActivate(); }
148 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
150 void profileClear() { return actualTC->profileClear(); }
151 void profileSample() { return actualTC->profileSample(); }
154 int threadId() { return actualTC->threadId(); }
156 // @todo: Do I need this?
157 MachInst getInst() { return actualTC->getInst(); }
159 // @todo: Do I need this?
160 void copyArchRegs(ThreadContext *tc)
162 actualTC->copyArchRegs(tc);
163 checkerTC->copyArchRegs(tc);
168 actualTC->clearArchRegs();
169 checkerTC->clearArchRegs();
173 // New accessors for new decoder.
175 uint64_t readIntReg(int reg_idx)
176 { return actualTC->readIntReg(reg_idx); }
178 FloatReg readFloatReg(int reg_idx)
179 { return actualTC->readFloatReg(reg_idx); }
181 FloatRegBits readFloatRegBits(int reg_idx)
182 { return actualTC->readFloatRegBits(reg_idx); }
184 void setIntReg(int reg_idx, uint64_t val)
186 actualTC->setIntReg(reg_idx, val);
187 checkerTC->setIntReg(reg_idx, val);
190 void setFloatReg(int reg_idx, FloatReg val)
192 actualTC->setFloatReg(reg_idx, val);
193 checkerTC->setFloatReg(reg_idx, val);
196 void setFloatRegBits(int reg_idx, FloatRegBits val)
198 actualTC->setFloatRegBits(reg_idx, val);
199 checkerTC->setFloatRegBits(reg_idx, val);
202 uint64_t readPC() { return actualTC->readPC(); }
204 void setPC(uint64_t val)
206 actualTC->setPC(val);
207 checkerTC->setPC(val);
208 checkerCPU->recordPCChange(val);
211 uint64_t readNextPC() { return actualTC->readNextPC(); }
213 void setNextPC(uint64_t val)
215 actualTC->setNextPC(val);
216 checkerTC->setNextPC(val);
217 checkerCPU->recordNextPCChange(val);
220 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
222 void setNextNPC(uint64_t val)
224 actualTC->setNextNPC(val);
225 checkerTC->setNextNPC(val);
226 checkerCPU->recordNextPCChange(val);
229 MiscReg readMiscRegNoEffect(int misc_reg)
230 { return actualTC->readMiscRegNoEffect(misc_reg); }
232 MiscReg readMiscReg(int misc_reg)
233 { return actualTC->readMiscReg(misc_reg); }
235 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
237 checkerTC->setMiscRegNoEffect(misc_reg, val);
238 actualTC->setMiscRegNoEffect(misc_reg, val);
241 void setMiscReg(int misc_reg, const MiscReg &val)
243 checkerTC->setMiscReg(misc_reg, val);
244 actualTC->setMiscReg(misc_reg, val);
247 unsigned readStCondFailures()
248 { return actualTC->readStCondFailures(); }
250 void setStCondFailures(unsigned sc_failures)
252 checkerTC->setStCondFailures(sc_failures);
253 actualTC->setStCondFailures(sc_failures);
257 bool misspeculating() { return actualTC->misspeculating(); }
260 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
264 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__