src/cpu/checker/thread_context.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
  44 #define __CPU_CHECKER_THREAD_CONTEXT_HH__
  45
  46 #include "arch/types.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/checker/cpu.hh"
  49 #include "cpu/simple_thread.hh"
  50 #include "cpu/thread_context.hh"
  51 #include "debug/Checker.hh"
  52
  53 class EndQuiesceEvent;
  54 namespace TheISA {
  55     namespace Kernel {
  56         class Statistics;
  57     };
  58 };
  59
  60 /**
  61  * Derived ThreadContext class for use with the Checker.  The template
  62  * parameter is the ThreadContext class used by the specific CPU being
  63  * verified.  This CheckerThreadContext is then used by the main CPU
  64  * in place of its usual ThreadContext class.  It handles updating the
  65  * checker's state any time state is updated externally through the
  66  * ThreadContext.
  67  */
  68 template <class TC>
  69 class CheckerThreadContext : public ThreadContext
  70 {
  71   public:
  72     CheckerThreadContext(TC *actual_tc,
  73                          CheckerCPU *checker_cpu)
  74         : actualTC(actual_tc), checkerTC(checker_cpu->thread),
  75           checkerCPU(checker_cpu)
  76     { }
  77
  78   private:
  79     /** The main CPU's ThreadContext, or class that implements the
  80      * ThreadContext interface. */
  81     TC *actualTC;
  82     /** The checker's own SimpleThread. Will be updated any time
  83      * anything uses this ThreadContext to externally update a
  84      * thread's state. */
  85     SimpleThread *checkerTC;
  86     /** Pointer to the checker CPU. */
  87     CheckerCPU *checkerCPU;
  88
  89   public:
  90
  91     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
  92
  93     int cpuId() { return actualTC->cpuId(); }
  94
  95     int contextId() { return actualTC->contextId(); }
  96
  97     void setContextId(int id)
  98     {
  99        actualTC->setContextId(id);
 100        checkerTC->setContextId(id);
 101     }
 102
 103     /** Returns this thread's ID number. */
 104     int threadId() { return actualTC->threadId(); }
 105     void setThreadId(int id)
 106     {
 107         checkerTC->setThreadId(id);
 108         actualTC->setThreadId(id);
 109     }
 110
 111     TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
 112
 113     TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 114
 115     CheckerCPU *getCheckerCpuPtr()
 116     {
 117         return checkerCPU;
 118     }
 119
 120     Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
 121
 122     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 123
 124     PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
 125
 126     TheISA::Kernel::Statistics *getKernelStats()
 127     { return actualTC->getKernelStats(); }
 128
 129     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 130
 131     PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
 132
 133     FSTranslatingPortProxy &getVirtProxy()
 134     { return actualTC->getVirtProxy(); }
 135
 136     void initMemProxies(ThreadContext *tc)
 137     { actualTC->initMemProxies(tc); }
 138
 139     void connectMemPorts(ThreadContext *tc)
 140     {
 141         actualTC->connectMemPorts(tc);
 142     }
 143
 144     SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
 145
 146     /** Executes a syscall in SE mode. */
 147     void syscall(int64_t callnum)
 148     { return actualTC->syscall(callnum); }
 149
 150     Status status() const { return actualTC->status(); }
 151
 152     void setStatus(Status new_status)
 153     {
 154         actualTC->setStatus(new_status);
 155         checkerTC->setStatus(new_status);
 156     }
 157
 158     /// Set the status to Active.  Optional delay indicates number of
 159     /// cycles to wait before beginning execution.
 160     void activate(int delay = 1) { actualTC->activate(delay); }
 161
 162     /// Set the status to Suspended.
 163     void suspend(int delay) { actualTC->suspend(delay); }
 164
 165     /// Set the status to Halted.
 166     void halt(int delay) { actualTC->halt(delay); }
 167
 168     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 169
 170     void takeOverFrom(ThreadContext *oldContext)
 171     {
 172         actualTC->takeOverFrom(oldContext);
 173         checkerTC->copyState(oldContext);
 174     }
 175
 176     void regStats(const std::string &name)
 177     {
 178         actualTC->regStats(name);
 179         checkerTC->regStats(name);
 180     }
 181
 182     void serialize(std::ostream &os) { actualTC->serialize(os); }
 183     void unserialize(Checkpoint *cp, const std::string &section)
 184     { actualTC->unserialize(cp, section); }
 185
 186     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 187
 188     Tick readLastActivate() { return actualTC->readLastActivate(); }
 189     Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 190
 191     void profileClear() { return actualTC->profileClear(); }
 192     void profileSample() { return actualTC->profileSample(); }
 193
 194     // @todo: Do I need this?
 195     void copyArchRegs(ThreadContext *tc)
 196     {
 197         actualTC->copyArchRegs(tc);
 198         checkerTC->copyArchRegs(tc);
 199     }
 200
 201     void clearArchRegs()
 202     {
 203         actualTC->clearArchRegs();
 204         checkerTC->clearArchRegs();
 205     }
 206
 207     //
 208     // New accessors for new decoder.
 209     //
 210     uint64_t readIntReg(int reg_idx)
 211     { return actualTC->readIntReg(reg_idx); }
 212
 213     FloatReg readFloatReg(int reg_idx)
 214     { return actualTC->readFloatReg(reg_idx); }
 215
 216     FloatRegBits readFloatRegBits(int reg_idx)
 217     { return actualTC->readFloatRegBits(reg_idx); }
 218
 219     void setIntReg(int reg_idx, uint64_t val)
 220     {
 221         actualTC->setIntReg(reg_idx, val);
 222         checkerTC->setIntReg(reg_idx, val);
 223     }
 224
 225     void setFloatReg(int reg_idx, FloatReg val)
 226     {
 227         actualTC->setFloatReg(reg_idx, val);
 228         checkerTC->setFloatReg(reg_idx, val);
 229     }
 230
 231     void setFloatRegBits(int reg_idx, FloatRegBits val)
 232     {
 233         actualTC->setFloatRegBits(reg_idx, val);
 234         checkerTC->setFloatRegBits(reg_idx, val);
 235     }
 236
 237     /** Reads this thread's PC state. */
 238     TheISA::PCState pcState()
 239     { return actualTC->pcState(); }
 240
 241     /** Sets this thread's PC state. */
 242     void pcState(const TheISA::PCState &val)
 243     {
 244         DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
 245                          val, checkerTC->pcState());
 246         checkerTC->pcState(val);
 247         checkerCPU->recordPCChange(val);
 248         return actualTC->pcState(val);
 249     }
 250
 251     void pcStateNoRecord(const TheISA::PCState &val)
 252     {
 253         return actualTC->pcState(val);
 254     }
 255
 256     /** Reads this thread's PC. */
 257     Addr instAddr()
 258     { return actualTC->instAddr(); }
 259
 260     /** Reads this thread's next PC. */
 261     Addr nextInstAddr()
 262     { return actualTC->nextInstAddr(); }
 263
 264     /** Reads this thread's next PC. */
 265     MicroPC microPC()
 266     { return actualTC->microPC(); }
 267
 268     MiscReg readMiscRegNoEffect(int misc_reg)
 269     { return actualTC->readMiscRegNoEffect(misc_reg); }
 270
 271     MiscReg readMiscReg(int misc_reg)
 272     { return actualTC->readMiscReg(misc_reg); }
 273
 274     void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 275     {
 276         DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
 277                          " and O3..\n", misc_reg);
 278         checkerTC->setMiscRegNoEffect(misc_reg, val);
 279         actualTC->setMiscRegNoEffect(misc_reg, val);
 280     }
 281
 282     void setMiscReg(int misc_reg, const MiscReg &val)
 283     {
 284         DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
 285                          " and O3..\n", misc_reg);
 286         checkerTC->setMiscReg(misc_reg, val);
 287         actualTC->setMiscReg(misc_reg, val);
 288     }
 289
 290     int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
 291     int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
 292
 293     unsigned readStCondFailures()
 294     { return actualTC->readStCondFailures(); }
 295
 296     void setStCondFailures(unsigned sc_failures)
 297     {
 298         actualTC->setStCondFailures(sc_failures);
 299     }
 300
 301     // @todo: Fix this!
 302     bool misspeculating() { return actualTC->misspeculating(); }
 303
 304     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 305 };
 306
 307 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__