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29 #ifndef __CPU_EXEC_CONTEXT_HH__
30 #define __CPU_EXEC_CONTEXT_HH__
32 #include "config/full_system.hh"
33 #include "mem/request.hh"
34 #include "sim/faults.hh"
35 #include "sim/host.hh"
36 #include "sim/serialize.hh"
37 #include "sim/byteswap.hh"
39 // @todo: Figure out a more architecture independent way to obtain the ITB and
45 class TranslatingPort;
54 typedef TheISA::RegFile RegFile;
55 typedef TheISA::MachInst MachInst;
56 typedef TheISA::IntReg IntReg;
57 typedef TheISA::FloatReg FloatReg;
58 typedef TheISA::FloatRegBits FloatRegBits;
59 typedef TheISA::MiscRegFile MiscRegFile;
60 typedef TheISA::MiscReg MiscReg;
64 /// Initialized but not running yet. All CPUs start in
65 /// this state, but most transition to Active on cycle 1.
66 /// In MP or SMT systems, non-primary contexts will stay
67 /// in this state until a thread is assigned to them.
70 /// Running. Instructions should be executed only when
71 /// the context is in this state.
74 /// Temporarily inactive. Entered while waiting for
75 /// synchronization, etc.
78 /// Permanently shut down. Entered when target executes
79 /// m5exit pseudo-instruction. When all contexts enter
80 /// this state, the simulation will terminate.
84 virtual ~ExecContext() { };
86 virtual BaseCPU *getCpuPtr() = 0;
88 virtual void setCpuId(int id) = 0;
90 virtual int readCpuId() = 0;
93 virtual System *getSystemPtr() = 0;
95 virtual AlphaITB *getITBPtr() = 0;
97 virtual AlphaDTB * getDTBPtr() = 0;
99 virtual FunctionalPort *getPhysPort() = 0;
101 virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0;
103 virtual void delVirtPort(VirtualPort *vp) = 0;
105 virtual TranslatingPort *getMemPort() = 0;
107 virtual Process *getProcessPtr() = 0;
110 virtual Status status() const = 0;
112 virtual void setStatus(Status new_status) = 0;
114 /// Set the status to Active. Optional delay indicates number of
115 /// cycles to wait before beginning execution.
116 virtual void activate(int delay = 1) = 0;
118 /// Set the status to Suspended.
119 virtual void suspend() = 0;
121 /// Set the status to Unallocated.
122 virtual void deallocate() = 0;
124 /// Set the status to Halted.
125 virtual void halt() = 0;
128 virtual void dumpFuncProfile() = 0;
131 virtual void takeOverFrom(ExecContext *old_context) = 0;
133 virtual void regStats(const std::string &name) = 0;
135 virtual void serialize(std::ostream &os) = 0;
136 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
139 virtual Event *getQuiesceEvent() = 0;
141 // Not necessarily the best location for these...
142 // Having an extra function just to read these is obnoxious
143 virtual Tick readLastActivate() = 0;
144 virtual Tick readLastSuspend() = 0;
146 virtual void profileClear() = 0;
147 virtual void profileSample() = 0;
150 virtual int getThreadNum() = 0;
152 virtual int getInstAsid() = 0;
153 virtual int getDataAsid() = 0;
155 virtual Fault translateInstReq(RequestPtr &req) = 0;
157 virtual Fault translateDataReadReq(RequestPtr &req) = 0;
159 virtual Fault translateDataWriteReq(RequestPtr &req) = 0;
161 // Also somewhat obnoxious. Really only used for the TLB fault.
162 // However, may be quite useful in SPARC.
163 virtual TheISA::MachInst getInst() = 0;
165 virtual void copyArchRegs(ExecContext *xc) = 0;
167 virtual void clearArchRegs() = 0;
170 // New accessors for new decoder.
172 virtual uint64_t readIntReg(int reg_idx) = 0;
174 virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
176 virtual FloatReg readFloatReg(int reg_idx) = 0;
178 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
180 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
182 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
184 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
186 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
188 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
190 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
192 virtual uint64_t readPC() = 0;
194 virtual void setPC(uint64_t val) = 0;
196 virtual uint64_t readNextPC() = 0;
198 virtual void setNextPC(uint64_t val) = 0;
200 virtual uint64_t readNextNPC() = 0;
202 virtual void setNextNPC(uint64_t val) = 0;
204 virtual MiscReg readMiscReg(int misc_reg) = 0;
206 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
208 virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
210 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
212 // Also not necessarily the best location for these two. Hopefully will go
213 // away once we decide upon where st cond failures goes.
214 virtual unsigned readStCondFailures() = 0;
216 virtual void setStCondFailures(unsigned sc_failures) = 0;
219 virtual int readIntrFlag() = 0;
220 virtual void setIntrFlag(int val) = 0;
221 virtual Fault hwrei() = 0;
222 virtual bool inPalMode() = 0;
223 virtual bool simPalCheck(int palFunc) = 0;
226 // Only really makes sense for old CPU model. Still could be useful though.
227 virtual bool misspeculating() = 0;
230 virtual IntReg getSyscallArg(int i) = 0;
232 // used to shift args for indirect syscall
233 virtual void setSyscallArg(int i, IntReg val) = 0;
235 virtual void setSyscallReturn(SyscallReturn return_value) = 0;
237 virtual void syscall(int64_t callnum) = 0;
239 // Same with st cond failures.
240 virtual Counter readFuncExeInst() = 0;
242 virtual void setFuncExeInst(Counter new_val) = 0;
245 virtual void changeRegFileContext(RegFile::ContextParam param,
246 RegFile::ContextVal val) = 0;
250 class ProxyExecContext : public ExecContext
253 ProxyExecContext(XC *actual_xc)
254 { actualXC = actual_xc; }
261 BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
263 void setCpuId(int id) { actualXC->setCpuId(id); }
265 int readCpuId() { return actualXC->readCpuId(); }
268 System *getSystemPtr() { return actualXC->getSystemPtr(); }
270 AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
272 AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
274 FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); }
276 VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); }
278 void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); }
280 TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
282 Process *getProcessPtr() { return actualXC->getProcessPtr(); }
285 Status status() const { return actualXC->status(); }
287 void setStatus(Status new_status) { actualXC->setStatus(new_status); }
289 /// Set the status to Active. Optional delay indicates number of
290 /// cycles to wait before beginning execution.
291 void activate(int delay = 1) { actualXC->activate(delay); }
293 /// Set the status to Suspended.
294 void suspend() { actualXC->suspend(); }
296 /// Set the status to Unallocated.
297 void deallocate() { actualXC->deallocate(); }
299 /// Set the status to Halted.
300 void halt() { actualXC->halt(); }
303 void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
306 void takeOverFrom(ExecContext *oldContext)
307 { actualXC->takeOverFrom(oldContext); }
309 void regStats(const std::string &name) { actualXC->regStats(name); }
311 void serialize(std::ostream &os) { actualXC->serialize(os); }
312 void unserialize(Checkpoint *cp, const std::string §ion)
313 { actualXC->unserialize(cp, section); }
316 Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
318 Tick readLastActivate() { return actualXC->readLastActivate(); }
319 Tick readLastSuspend() { return actualXC->readLastSuspend(); }
321 void profileClear() { return actualXC->profileClear(); }
322 void profileSample() { return actualXC->profileSample(); }
325 int getThreadNum() { return actualXC->getThreadNum(); }
327 int getInstAsid() { return actualXC->getInstAsid(); }
328 int getDataAsid() { return actualXC->getDataAsid(); }
330 Fault translateInstReq(RequestPtr &req)
331 { return actualXC->translateInstReq(req); }
333 Fault translateDataReadReq(RequestPtr &req)
334 { return actualXC->translateDataReadReq(req); }
336 Fault translateDataWriteReq(RequestPtr &req)
337 { return actualXC->translateDataWriteReq(req); }
339 // @todo: Do I need this?
340 MachInst getInst() { return actualXC->getInst(); }
342 // @todo: Do I need this?
343 void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); }
345 void clearArchRegs() { actualXC->clearArchRegs(); }
348 // New accessors for new decoder.
350 uint64_t readIntReg(int reg_idx)
351 { return actualXC->readIntReg(reg_idx); }
353 FloatReg readFloatReg(int reg_idx, int width)
354 { return actualXC->readFloatReg(reg_idx, width); }
356 FloatReg readFloatReg(int reg_idx)
357 { return actualXC->readFloatReg(reg_idx); }
359 FloatRegBits readFloatRegBits(int reg_idx, int width)
360 { return actualXC->readFloatRegBits(reg_idx, width); }
362 FloatRegBits readFloatRegBits(int reg_idx)
363 { return actualXC->readFloatRegBits(reg_idx); }
365 void setIntReg(int reg_idx, uint64_t val)
366 { actualXC->setIntReg(reg_idx, val); }
368 void setFloatReg(int reg_idx, FloatReg val, int width)
369 { actualXC->setFloatReg(reg_idx, val, width); }
371 void setFloatReg(int reg_idx, FloatReg val)
372 { actualXC->setFloatReg(reg_idx, val); }
374 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
375 { actualXC->setFloatRegBits(reg_idx, val, width); }
377 void setFloatRegBits(int reg_idx, FloatRegBits val)
378 { actualXC->setFloatRegBits(reg_idx, val); }
380 uint64_t readPC() { return actualXC->readPC(); }
382 void setPC(uint64_t val) { actualXC->setPC(val); }
384 uint64_t readNextPC() { return actualXC->readNextPC(); }
386 void setNextPC(uint64_t val) { actualXC->setNextPC(val); }
388 uint64_t readNextNPC() { return actualXC->readNextNPC(); }
390 void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); }
392 MiscReg readMiscReg(int misc_reg)
393 { return actualXC->readMiscReg(misc_reg); }
395 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
396 { return actualXC->readMiscRegWithEffect(misc_reg, fault); }
398 Fault setMiscReg(int misc_reg, const MiscReg &val)
399 { return actualXC->setMiscReg(misc_reg, val); }
401 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
402 { return actualXC->setMiscRegWithEffect(misc_reg, val); }
404 unsigned readStCondFailures()
405 { return actualXC->readStCondFailures(); }
407 void setStCondFailures(unsigned sc_failures)
408 { actualXC->setStCondFailures(sc_failures); }
411 int readIntrFlag() { return actualXC->readIntrFlag(); }
413 void setIntrFlag(int val) { actualXC->setIntrFlag(val); }
415 Fault hwrei() { return actualXC->hwrei(); }
417 bool inPalMode() { return actualXC->inPalMode(); }
419 bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); }
423 bool misspeculating() { return actualXC->misspeculating(); }
426 IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
428 // used to shift args for indirect syscall
429 void setSyscallArg(int i, IntReg val)
430 { actualXC->setSyscallArg(i, val); }
432 void setSyscallReturn(SyscallReturn return_value)
433 { actualXC->setSyscallReturn(return_value); }
435 void syscall(int64_t callnum) { actualXC->syscall(callnum); }
437 Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
439 void setFuncExeInst(Counter new_val)
440 { return actualXC->setFuncExeInst(new_val); }
443 void changeRegFileContext(RegFile::ContextParam param,
444 RegFile::ContextVal val)
446 actualXC->changeRegFileContext(param, val);