2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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31 #error "Cannot include this file"
34 * The ExecContext is not a usable class. It is simply here for
35 * documentation purposes. It shows the interface that is used by the
36 * ISA to access and change CPU state.
39 // The register accessor methods provide the index of the
40 // instruction's operand (e.g., 0 or 1), not the architectural
41 // register index, to simplify the implementation of register
42 // renaming. We find the architectural register index by indexing
43 // into the instruction's own operand index table. Note that a
44 // raw pointer to the StaticInst is provided instead of a
45 // ref-counted StaticInstPtr to reduce overhead. This is fine as
46 // long as these methods don't copy the pointer into any long-term
47 // storage (which is pretty hard to imagine they would have reason
50 /** Reads an integer register. */
51 uint64_t readIntRegOperand(const StaticInst *si, int idx);
53 /** Reads a floating point register of single register width. */
54 FloatReg readFloatRegOperand(const StaticInst *si, int idx);
56 /** Reads a floating point register in its binary format, instead
58 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
60 /** Sets an integer register to a value. */
61 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
63 /** Sets a floating point register of single width to a value. */
64 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
66 /** Sets the bits of a floating point register of single width
67 * to a binary value. */
68 void setFloatRegOperandBits(const StaticInst *si, int idx,
73 /** Reads the NextPC. */
74 uint64_t readNextPC();
75 /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */
76 uint64_t readNextNPC();
79 void setPC(uint64_t val);
80 /** Sets the NextPC. */
81 void setNextPC(uint64_t val);
82 /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */
83 void setNextNPC(uint64_t val);
85 /** Reads a miscellaneous register. */
86 MiscReg readMiscRegNoEffect(int misc_reg);
88 /** Reads a miscellaneous register, handling any architectural
89 * side effects due to reading that register. */
90 MiscReg readMiscReg(int misc_reg);
92 /** Sets a miscellaneous register. */
93 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
95 /** Sets a miscellaneous register, handling any architectural
96 * side effects due to writing that register. */
97 void setMiscReg(int misc_reg, const MiscReg &val);
99 /** Records the effective address of the instruction. Only valid
102 /** Returns the effective address of the instruction. Only valid
106 /** Returns a pointer to the ThreadContext. */
107 ThreadContext *tcBase();
109 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
111 Fault writeMem(uint8_t *data, unsigned size,
112 Addr addr, unsigned flags, uint64_t *res);
114 /** Somewhat Alpha-specific function that handles returning from
115 * an error or interrupt. */
119 * Check for special simulator handling of specific PAL calls. If
120 * return value is false, actual PAL call will be suppressed.
122 bool simPalCheck(int palFunc);
124 /** Executes a syscall specified by the callnum. */
125 void syscall(int64_t callnum);
127 /** Finish a DTB address translation. */
128 void finishTranslation(WholeTranslationState *state);