src/cpu/exec_context.hh

   1 /*
   2  * Copyright (c) 2014, 2016-2018, 2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2015 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_EXEC_CONTEXT_HH__
  43 #define __CPU_EXEC_CONTEXT_HH__
  44
  45 #include "arch/registers.hh"
  46 #include "base/types.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/base.hh"
  49 #include "cpu/reg_class.hh"
  50 #include "cpu/static_inst_fwd.hh"
  51 #include "cpu/translation.hh"
  52 #include "mem/request.hh"
  53
  54 /**
  55  * The ExecContext is an abstract base class the provides the
  56  * interface used by the ISA to manipulate the state of the CPU model.
  57  *
  58  * Register accessor methods in this class typically provide the index
  59  * of the instruction's operand (e.g., 0 or 1), not the architectural
  60  * register index, to simplify the implementation of register
  61  * renaming.  The architectural register index can be found by
  62  * indexing into the instruction's own operand index table.
  63  *
  64  * @note The methods in this class typically take a raw pointer to the
  65  * StaticInst is provided instead of a ref-counted StaticInstPtr to
  66  * reduce overhead as an argument. This is fine as long as the
  67  * implementation doesn't copy the pointer into any long-term storage
  68  * (which is pretty hard to imagine they would have reason to do).
  69  */
  70 class ExecContext {
  71   public:
  72     typedef TheISA::PCState PCState;
  73
  74     using VecRegContainer = TheISA::VecRegContainer;
  75     using VecElem = TheISA::VecElem;
  76     using VecPredRegContainer = TheISA::VecPredRegContainer;
  77
  78   public:
  79     /**
  80      * @{
  81      * @name Integer Register Interfaces
  82      *
  83      */
  84
  85     /** Reads an integer register. */
  86     virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0;
  87
  88     /** Sets an integer register to a value. */
  89     virtual void setIntRegOperand(const StaticInst *si,
  90                                   int idx, RegVal val) = 0;
  91
  92     /** @} */
  93
  94
  95     /**
  96      * @{
  97      * @name Floating Point Register Interfaces
  98      */
  99
 100     /** Reads a floating point register in its binary format, instead
 101      * of by value. */
 102     virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0;
 103
 104     /** Sets the bits of a floating point register of single width
 105      * to a binary value. */
 106     virtual void setFloatRegOperandBits(const StaticInst *si,
 107                                         int idx, RegVal val) = 0;
 108
 109     /** @} */
 110
 111     /** Vector Register Interfaces. */
 112     /** @{ */
 113     /** Reads source vector register operand. */
 114     virtual const VecRegContainer&
 115     readVecRegOperand(const StaticInst *si, int idx) const = 0;
 116
 117     /** Gets destination vector register operand for modification. */
 118     virtual VecRegContainer&
 119     getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
 120
 121     /** Sets a destination vector register operand to a value. */
 122     virtual void
 123     setVecRegOperand(const StaticInst *si, int idx,
 124                      const VecRegContainer& val) = 0;
 125     /** @} */
 126
 127     /** Vector Register Lane Interfaces. */
 128     /** @{ */
 129     /** Reads source vector 8bit operand. */
 130     virtual ConstVecLane8
 131     readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
 132
 133     /** Reads source vector 16bit operand. */
 134     virtual ConstVecLane16
 135     readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
 136
 137     /** Reads source vector 32bit operand. */
 138     virtual ConstVecLane32
 139     readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;
 140
 141     /** Reads source vector 64bit operand. */
 142     virtual ConstVecLane64
 143     readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;
 144
 145     /** Write a lane of the destination vector operand. */
 146     /** @{ */
 147     virtual void setVecLaneOperand(const StaticInst *si, int idx,
 148             const LaneData<LaneSize::Byte>& val) = 0;
 149     virtual void setVecLaneOperand(const StaticInst *si, int idx,
 150             const LaneData<LaneSize::TwoByte>& val) = 0;
 151     virtual void setVecLaneOperand(const StaticInst *si, int idx,
 152             const LaneData<LaneSize::FourByte>& val) = 0;
 153     virtual void setVecLaneOperand(const StaticInst *si, int idx,
 154             const LaneData<LaneSize::EightByte>& val) = 0;
 155     /** @} */
 156
 157     /** Vector Elem Interfaces. */
 158     /** @{ */
 159     /** Reads an element of a vector register. */
 160     virtual VecElem readVecElemOperand(const StaticInst *si,
 161                                         int idx) const = 0;
 162
 163     /** Sets a vector register to a value. */
 164     virtual void setVecElemOperand(const StaticInst *si, int idx,
 165                                    const VecElem val) = 0;
 166     /** @} */
 167
 168     /** Predicate registers interface. */
 169     /** @{ */
 170     /** Reads source predicate register operand. */
 171     virtual const VecPredRegContainer&
 172     readVecPredRegOperand(const StaticInst *si, int idx) const = 0;
 173
 174     /** Gets destination predicate register operand for modification. */
 175     virtual VecPredRegContainer&
 176     getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0;
 177
 178     /** Sets a destination predicate register operand to a value. */
 179     virtual void
 180     setVecPredRegOperand(const StaticInst *si, int idx,
 181                          const VecPredRegContainer& val) = 0;
 182     /** @} */
 183
 184     /**
 185      * @{
 186      * @name Condition Code Registers
 187      */
 188     virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
 189     virtual void setCCRegOperand(
 190             const StaticInst *si, int idx, RegVal val) = 0;
 191     /** @} */
 192
 193     /**
 194      * @{
 195      * @name Misc Register Interfaces
 196      */
 197     virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
 198     virtual void setMiscRegOperand(const StaticInst *si,
 199                                    int idx, RegVal val) = 0;
 200
 201     /**
 202      * Reads a miscellaneous register, handling any architectural
 203      * side effects due to reading that register.
 204      */
 205     virtual RegVal readMiscReg(int misc_reg) = 0;
 206
 207     /**
 208      * Sets a miscellaneous register, handling any architectural
 209      * side effects due to writing that register.
 210      */
 211     virtual void setMiscReg(int misc_reg, RegVal val) = 0;
 212
 213     /** @} */
 214
 215     /**
 216      * @{
 217      * @name PC Control
 218      */
 219     virtual PCState pcState() const = 0;
 220     virtual void pcState(const PCState &val) = 0;
 221     /** @} */
 222
 223     /**
 224      * @{
 225      * @name Memory Interface
 226      */
 227     /**
 228      * Perform an atomic memory read operation.  Must be overridden
 229      * for exec contexts that support atomic memory mode.  Not pure
 230      * virtual since exec contexts that only support timing memory
 231      * mode need not override (though in that case this function
 232      * should never be called).
 233      */
 234     virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
 235             Request::Flags flags,
 236             const std::vector<bool>& byte_enable = std::vector<bool>())
 237     {
 238         panic("ExecContext::readMem() should be overridden\n");
 239     }
 240
 241     /**
 242      * Initiate a timing memory read operation.  Must be overridden
 243      * for exec contexts that support timing memory mode.  Not pure
 244      * virtual since exec contexts that only support atomic memory
 245      * mode need not override (though in that case this function
 246      * should never be called).
 247      */
 248     virtual Fault initiateMemRead(Addr addr, unsigned int size,
 249             Request::Flags flags,
 250             const std::vector<bool>& byte_enable = std::vector<bool>())
 251     {
 252         panic("ExecContext::initiateMemRead() should be overridden\n");
 253     }
 254
 255     /**
 256      * Initiate an HTM command,
 257      * e.g. tell Ruby we're starting/stopping a transaction
 258      */
 259     virtual Fault initiateHtmCmd(Request::Flags flags) = 0;
 260     /**
 261      * For atomic-mode contexts, perform an atomic memory write operation.
 262      * For timing-mode contexts, initiate a timing memory write operation.
 263      */
 264     virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
 265                            Request::Flags flags, uint64_t *res,
 266                            const std::vector<bool>& byte_enable =
 267                                std::vector<bool>()) = 0;
 268
 269     /**
 270      * For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic
 271      * Read-Modify-Write Memory Operation)
 272      */
 273     virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
 274                          Request::Flags flags,
 275                          AtomicOpFunctorPtr amo_op)
 276     {
 277         panic("ExecContext::amoMem() should be overridden\n");
 278     }
 279
 280     /**
 281      * For timing-mode contexts, initiate an atomic AMO (atomic
 282      * read-modify-write memory operation)
 283      */
 284     virtual Fault initiateMemAMO(Addr addr, unsigned int size,
 285                                  Request::Flags flags,
 286                                  AtomicOpFunctorPtr amo_op)
 287     {
 288         panic("ExecContext::initiateMemAMO() should be overridden\n");
 289     }
 290
 291     /**
 292      * Sets the number of consecutive store conditional failures.
 293      */
 294     virtual void setStCondFailures(unsigned int sc_failures) = 0;
 295
 296     /**
 297      * Returns the number of consecutive store conditional failures.
 298      */
 299     virtual unsigned int readStCondFailures() const = 0;
 300
 301     /** @} */
 302
 303     /** Returns a pointer to the ThreadContext. */
 304     virtual ThreadContext *tcBase() const = 0;
 305
 306     /**
 307      * @{
 308      * @name ARM-Specific Interfaces
 309      */
 310
 311     virtual bool readPredicate() const = 0;
 312     virtual void setPredicate(bool val) = 0;
 313     virtual bool readMemAccPredicate() const = 0;
 314     virtual void setMemAccPredicate(bool val) = 0;
 315
 316     // hardware transactional memory
 317     virtual uint64_t newHtmTransactionUid() const = 0;
 318     virtual uint64_t getHtmTransactionUid() const = 0;
 319     virtual bool inHtmTransactionalState() const = 0;
 320     virtual uint64_t getHtmTransactionalDepth() const = 0;
 321
 322     /** @} */
 323
 324     /**
 325      * @{
 326      * @name X86-Specific Interfaces
 327      */
 328
 329     /**
 330      * Invalidate a page in the DTLB <i>and</i> ITLB.
 331      */
 332     virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
 333     virtual void armMonitor(Addr address) = 0;
 334     virtual bool mwait(PacketPtr pkt) = 0;
 335     virtual void mwaitAtomic(ThreadContext *tc) = 0;
 336     virtual AddressMonitor *getAddrMonitor() = 0;
 337
 338     /** @} */
 339 };
 340
 341 #endif // __CPU_EXEC_CONTEXT_HH__