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45 #ifndef __CPU_EXEC_CONTEXT_HH__
46 #define __CPU_EXEC_CONTEXT_HH__
48 #include "arch/registers.hh"
49 #include "base/types.hh"
50 #include "config/the_isa.hh"
51 #include "cpu/base.hh"
52 #include "cpu/reg_class.hh"
53 #include "cpu/static_inst_fwd.hh"
54 #include "cpu/translation.hh"
55 #include "mem/request.hh"
58 * The ExecContext is an abstract base class the provides the
59 * interface used by the ISA to manipulate the state of the CPU model.
61 * Register accessor methods in this class typically provide the index
62 * of the instruction's operand (e.g., 0 or 1), not the architectural
63 * register index, to simplify the implementation of register
64 * renaming. The architectural register index can be found by
65 * indexing into the instruction's own operand index table.
67 * @note The methods in this class typically take a raw pointer to the
68 * StaticInst is provided instead of a ref-counted StaticInstPtr to
69 * reduce overhead as an argument. This is fine as long as the
70 * implementation doesn't copy the pointer into any long-term storage
71 * (which is pretty hard to imagine they would have reason to do).
75 typedef TheISA::IntReg IntReg;
76 typedef TheISA::PCState PCState;
77 typedef TheISA::FloatReg FloatReg;
78 typedef TheISA::FloatRegBits FloatRegBits;
79 typedef TheISA::MiscReg MiscReg;
81 typedef TheISA::CCReg CCReg;
82 using VecRegContainer = TheISA::VecRegContainer;
83 using VecElem = TheISA::VecElem;
88 * @name Integer Register Interfaces
92 /** Reads an integer register. */
93 virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
95 /** Sets an integer register to a value. */
96 virtual void setIntRegOperand(const StaticInst *si,
97 int idx, IntReg val) = 0;
104 * @name Floating Point Register Interfaces
107 /** Reads a floating point register of single register width. */
108 virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0;
110 /** Reads a floating point register in its binary format, instead
112 virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
115 /** Sets a floating point register of single width to a value. */
116 virtual void setFloatRegOperand(const StaticInst *si,
117 int idx, FloatReg val) = 0;
119 /** Sets the bits of a floating point register of single width
120 * to a binary value. */
121 virtual void setFloatRegOperandBits(const StaticInst *si,
122 int idx, FloatRegBits val) = 0;
126 /** Vector Register Interfaces. */
128 /** Reads source vector register operand. */
129 virtual const VecRegContainer&
130 readVecRegOperand(const StaticInst *si, int idx) const = 0;
132 /** Gets destination vector register operand for modification. */
133 virtual VecRegContainer&
134 getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
136 /** Sets a destination vector register operand to a value. */
138 setVecRegOperand(const StaticInst *si, int idx,
139 const VecRegContainer& val) = 0;
142 /** Vector Register Lane Interfaces. */
144 /** Reads source vector 8bit operand. */
145 virtual ConstVecLane8
146 readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
148 /** Reads source vector 16bit operand. */
149 virtual ConstVecLane16
150 readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
152 /** Reads source vector 32bit operand. */
153 virtual ConstVecLane32
154 readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;
156 /** Reads source vector 64bit operand. */
157 virtual ConstVecLane64
158 readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;
160 /** Write a lane of the destination vector operand. */
162 virtual void setVecLaneOperand(const StaticInst *si, int idx,
163 const LaneData<LaneSize::Byte>& val) = 0;
164 virtual void setVecLaneOperand(const StaticInst *si, int idx,
165 const LaneData<LaneSize::TwoByte>& val) = 0;
166 virtual void setVecLaneOperand(const StaticInst *si, int idx,
167 const LaneData<LaneSize::FourByte>& val) = 0;
168 virtual void setVecLaneOperand(const StaticInst *si, int idx,
169 const LaneData<LaneSize::EightByte>& val) = 0;
172 /** Vector Elem Interfaces. */
174 /** Reads an element of a vector register. */
175 virtual VecElem readVecElemOperand(const StaticInst *si,
178 /** Sets a vector register to a value. */
179 virtual void setVecElemOperand(const StaticInst *si, int idx,
180 const VecElem val) = 0;
185 * @name Condition Code Registers
187 virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
188 virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
193 * @name Misc Register Interfaces
195 virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
196 virtual void setMiscRegOperand(const StaticInst *si,
197 int idx, const MiscReg &val) = 0;
200 * Reads a miscellaneous register, handling any architectural
201 * side effects due to reading that register.
203 virtual MiscReg readMiscReg(int misc_reg) = 0;
206 * Sets a miscellaneous register, handling any architectural
207 * side effects due to writing that register.
209 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
217 virtual PCState pcState() const = 0;
218 virtual void pcState(const PCState &val) = 0;
223 * @name Memory Interface
226 * Record the effective address of the instruction.
228 * @note Only valid for memory ops.
230 virtual void setEA(Addr EA) = 0;
232 * Get the effective address of the instruction.
234 * @note Only valid for memory ops.
236 virtual Addr getEA() const = 0;
239 * Perform an atomic memory read operation. Must be overridden
240 * for exec contexts that support atomic memory mode. Not pure
241 * virtual since exec contexts that only support timing memory
242 * mode need not override (though in that case this function
243 * should never be called).
245 virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
246 Request::Flags flags)
248 panic("ExecContext::readMem() should be overridden\n");
252 * Initiate a timing memory read operation. Must be overridden
253 * for exec contexts that support timing memory mode. Not pure
254 * virtual since exec contexts that only support atomic memory
255 * mode need not override (though in that case this function
256 * should never be called).
258 virtual Fault initiateMemRead(Addr addr, unsigned int size,
259 Request::Flags flags)
261 panic("ExecContext::initiateMemRead() should be overridden\n");
265 * For atomic-mode contexts, perform an atomic memory write operation.
266 * For timing-mode contexts, initiate a timing memory write operation.
268 virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
269 Request::Flags flags, uint64_t *res) = 0;
272 * Sets the number of consecutive store conditional failures.
274 virtual void setStCondFailures(unsigned int sc_failures) = 0;
277 * Returns the number of consecutive store conditional failures.
279 virtual unsigned int readStCondFailures() const = 0;
285 * @name SysCall Emulation Interfaces
289 * Executes a syscall specified by the callnum.
291 virtual void syscall(int64_t callnum, Fault *fault) = 0;
295 /** Returns a pointer to the ThreadContext. */
296 virtual ThreadContext *tcBase() = 0;
300 * @name Alpha-Specific Interfaces
304 * Somewhat Alpha-specific function that handles returning from an
305 * error or interrupt.
307 virtual Fault hwrei() = 0;
310 * Check for special simulator handling of specific PAL calls. If
311 * return value is false, actual PAL call will be suppressed.
313 virtual bool simPalCheck(int palFunc) = 0;
319 * @name ARM-Specific Interfaces
322 virtual bool readPredicate() = 0;
323 virtual void setPredicate(bool val) = 0;
329 * @name X86-Specific Interfaces
333 * Invalidate a page in the DTLB <i>and</i> ITLB.
335 virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
336 virtual void armMonitor(Addr address) = 0;
337 virtual bool mwait(PacketPtr pkt) = 0;
338 virtual void mwaitAtomic(ThreadContext *tc) = 0;
339 virtual AddressMonitor *getAddrMonitor() = 0;
345 * @name MIPS-Specific Interfaces
348 #if THE_ISA == MIPS_ISA
349 virtual MiscReg readRegOtherThread(const RegId& reg,
350 ThreadID tid = InvalidThreadID) = 0;
351 virtual void setRegOtherThread(const RegId& reg, MiscReg val,
352 ThreadID tid = InvalidThreadID) = 0;
358 #endif // __CPU_EXEC_CONTEXT_HH__