src/cpu/exec_context.hh

   1 /*
   2  * Copyright (c) 2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2015 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  *          Andreas Sandberg
  43  */
  44
  45 #ifndef __CPU_EXEC_CONTEXT_HH__
  46 #define __CPU_EXEC_CONTEXT_HH__
  47
  48 #include "arch/registers.hh"
  49 #include "base/types.hh"
  50 #include "config/the_isa.hh"
  51 #include "cpu/base.hh"
  52 #include "cpu/static_inst_fwd.hh"
  53 #include "cpu/translation.hh"
  54 #include "mem/request.hh"
  55
  56 /**
  57  * The ExecContext is an abstract base class the provides the
  58  * interface used by the ISA to manipulate the state of the CPU model.
  59  *
  60  * Register accessor methods in this class typically provide the index
  61  * of the instruction's operand (e.g., 0 or 1), not the architectural
  62  * register index, to simplify the implementation of register
  63  * renaming.  The architectural register index can be found by
  64  * indexing into the instruction's own operand index table.
  65  *
  66  * @note The methods in this class typically take a raw pointer to the
  67  * StaticInst is provided instead of a ref-counted StaticInstPtr to
  68  * reduce overhead as an argument. This is fine as long as the
  69  * implementation doesn't copy the pointer into any long-term storage
  70  * (which is pretty hard to imagine they would have reason to do).
  71  */
  72 class ExecContext {
  73   public:
  74     typedef TheISA::IntReg IntReg;
  75     typedef TheISA::PCState PCState;
  76     typedef TheISA::FloatReg FloatReg;
  77     typedef TheISA::FloatRegBits FloatRegBits;
  78     typedef TheISA::MiscReg MiscReg;
  79
  80     typedef TheISA::CCReg CCReg;
  81
  82   public:
  83     /**
  84      * @{
  85      * @name Integer Register Interfaces
  86      *
  87      */
  88
  89     /** Reads an integer register. */
  90     virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
  91
  92     /** Sets an integer register to a value. */
  93     virtual void setIntRegOperand(const StaticInst *si,
  94                                   int idx, IntReg val) = 0;
  95
  96     /** @} */
  97
  98
  99     /**
 100      * @{
 101      * @name Floating Point Register Interfaces
 102      */
 103
 104     /** Reads a floating point register of single register width. */
 105     virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0;
 106
 107     /** Reads a floating point register in its binary format, instead
 108      * of by value. */
 109     virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
 110                                                  int idx) = 0;
 111
 112     /** Sets a floating point register of single width to a value. */
 113     virtual void setFloatRegOperand(const StaticInst *si,
 114                                     int idx, FloatReg val) = 0;
 115
 116     /** Sets the bits of a floating point register of single width
 117      * to a binary value. */
 118     virtual void setFloatRegOperandBits(const StaticInst *si,
 119                                         int idx, FloatRegBits val) = 0;
 120
 121     /** @} */
 122
 123     /**
 124      * @{
 125      * @name Condition Code Registers
 126      */
 127     virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
 128     virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
 129     /** @} */
 130
 131     /**
 132      * @{
 133      * @name Misc Register Interfaces
 134      */
 135     virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
 136     virtual void setMiscRegOperand(const StaticInst *si,
 137                                    int idx, const MiscReg &val) = 0;
 138
 139     /**
 140      * Reads a miscellaneous register, handling any architectural
 141      * side effects due to reading that register.
 142      */
 143     virtual MiscReg readMiscReg(int misc_reg) = 0;
 144
 145     /**
 146      * Sets a miscellaneous register, handling any architectural
 147      * side effects due to writing that register.
 148      */
 149     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 150
 151     /** @} */
 152
 153     /**
 154      * @{
 155      * @name PC Control
 156      */
 157     virtual PCState pcState() const = 0;
 158     virtual void pcState(const PCState &val) = 0;
 159     /** @} */
 160
 161     /**
 162      * @{
 163      * @name Memory Interface
 164      */
 165     /**
 166      * Record the effective address of the instruction.
 167      *
 168      * @note Only valid for memory ops.
 169      */
 170     virtual void setEA(Addr EA) = 0;
 171     /**
 172      * Get the effective address of the instruction.
 173      *
 174      * @note Only valid for memory ops.
 175      */
 176     virtual Addr getEA() const = 0;
 177
 178     /**
 179      * Perform an atomic memory read operation.  Must be overridden
 180      * for exec contexts that support atomic memory mode.  Not pure
 181      * virtual since exec contexts that only support timing memory
 182      * mode need not override (though in that case this function
 183      * should never be called).
 184      */
 185     virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
 186                           Request::Flags flags)
 187     {
 188         panic("ExecContext::readMem() should be overridden\n");
 189     }
 190
 191     /**
 192      * Initiate a timing memory read operation.  Must be overridden
 193      * for exec contexts that support timing memory mode.  Not pure
 194      * virtual since exec contexts that only support atomic memory
 195      * mode need not override (though in that case this function
 196      * should never be called).
 197      */
 198     virtual Fault initiateMemRead(Addr addr, unsigned int size,
 199                                   Request::Flags flags)
 200     {
 201         panic("ExecContext::initiateMemRead() should be overridden\n");
 202     }
 203
 204     /**
 205      * For atomic-mode contexts, perform an atomic memory write operation.
 206      * For timing-mode contexts, initiate a timing memory write operation.
 207      */
 208     virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
 209                            Request::Flags flags, uint64_t *res) = 0;
 210
 211     /**
 212      * Sets the number of consecutive store conditional failures.
 213      */
 214     virtual void setStCondFailures(unsigned int sc_failures) = 0;
 215
 216     /**
 217      * Returns the number of consecutive store conditional failures.
 218      */
 219     virtual unsigned int readStCondFailures() const = 0;
 220
 221     /** @} */
 222
 223     /**
 224      * @{
 225      * @name SysCall Emulation Interfaces
 226      */
 227
 228     /**
 229      * Executes a syscall specified by the callnum.
 230      */
 231     virtual void syscall(int64_t callnum) = 0;
 232
 233     /** @} */
 234
 235     /** Returns a pointer to the ThreadContext. */
 236     virtual ThreadContext *tcBase() = 0;
 237
 238     /**
 239      * @{
 240      * @name Alpha-Specific Interfaces
 241      */
 242
 243     /**
 244      * Somewhat Alpha-specific function that handles returning from an
 245      * error or interrupt.
 246      */
 247     virtual Fault hwrei() = 0;
 248
 249     /**
 250      * Check for special simulator handling of specific PAL calls.  If
 251      * return value is false, actual PAL call will be suppressed.
 252      */
 253     virtual bool simPalCheck(int palFunc) = 0;
 254
 255     /** @} */
 256
 257     /**
 258      * @{
 259      * @name ARM-Specific Interfaces
 260      */
 261
 262     virtual bool readPredicate() = 0;
 263     virtual void setPredicate(bool val) = 0;
 264
 265     /** @} */
 266
 267     /**
 268      * @{
 269      * @name X86-Specific Interfaces
 270      */
 271
 272     /**
 273      * Invalidate a page in the DTLB <i>and</i> ITLB.
 274      */
 275     virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
 276     virtual void armMonitor(Addr address) = 0;
 277     virtual bool mwait(PacketPtr pkt) = 0;
 278     virtual void mwaitAtomic(ThreadContext *tc) = 0;
 279     virtual AddressMonitor *getAddrMonitor() = 0;
 280
 281     /** @} */
 282
 283     /**
 284      * @{
 285      * @name MIPS-Specific Interfaces
 286      */
 287
 288 #if THE_ISA == MIPS_ISA
 289     virtual MiscReg readRegOtherThread(int regIdx,
 290                                        ThreadID tid = InvalidThreadID) = 0;
 291     virtual void setRegOtherThread(int regIdx, MiscReg val,
 292                                    ThreadID tid = InvalidThreadID) = 0;
 293 #endif
 294
 295     /** @} */
 296 };
 297
 298 #endif // __CPU_EXEC_CONTEXT_HH__