src/cpu/exetrace.cc

   1 /*
   2  * Copyright (c) 2017, 2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include "cpu/exetrace.hh"
  42
  43 #include <iomanip>
  44 #include <sstream>
  45
  46 #include "arch/utility.hh"
  47 #include "base/loader/symtab.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/base.hh"
  50 #include "cpu/static_inst.hh"
  51 #include "cpu/thread_context.hh"
  52 #include "debug/ExecAll.hh"
  53 #include "debug/FmtTicksOff.hh"
  54 #include "enums/OpClass.hh"
  55
  56 using namespace std;
  57 using namespace TheISA;
  58
  59 namespace Trace {
  60
  61 void
  62 Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
  63 {
  64     std::stringstream outs;
  65
  66     if (!Debug::ExecUser || !Debug::ExecKernel) {
  67         bool in_user_mode = TheISA::inUserMode(thread);
  68         if (in_user_mode && !Debug::ExecUser) return;
  69         if (!in_user_mode && !Debug::ExecKernel) return;
  70     }
  71
  72     if (Debug::ExecAsid)
  73         outs << "A" << dec << TheISA::getExecutingAsid(thread) << " ";
  74
  75     if (Debug::ExecThread)
  76         outs << "T" << thread->threadId() << " : ";
  77
  78     Addr cur_pc = pc.instAddr();
  79     Loader::SymbolTable::const_iterator it;
  80     ccprintf(outs, "%#x", cur_pc);
  81     if (Debug::ExecSymbol && (!FullSystem || !inUserMode(thread)) &&
  82             (it = Loader::debugSymbolTable.findNearest(cur_pc)) !=
  83                 Loader::debugSymbolTable.end()) {
  84         Addr delta = cur_pc - it->address;
  85         if (delta)
  86             ccprintf(outs, " @%s+%d", it->name, delta);
  87         else
  88             ccprintf(outs, " @%s", it->name);
  89     }
  90
  91     if (inst->isMicroop()) {
  92         ccprintf(outs, ".%2d", pc.microPC());
  93     } else {
  94         ccprintf(outs, "   ");
  95     }
  96
  97     ccprintf(outs, " : ");
  98
  99     //
 100     //  Print decoded instruction
 101     //
 102
 103     outs << setw(26) << left;
 104     outs << inst->disassemble(cur_pc, &Loader::debugSymbolTable);
 105
 106     if (ran) {
 107         outs << " : ";
 108
 109         if (Debug::ExecOpClass) {
 110             outs << Enums::OpClassStrings[inst->opClass()] << " : ";
 111         }
 112
 113         if (Debug::ExecResult && !predicate) {
 114             outs << "Predicated False";
 115         }
 116
 117         if (Debug::ExecResult && data_status != DataInvalid) {
 118             switch (data_status) {
 119               case DataVec:
 120                 {
 121                     ccprintf(outs, " D=0x[");
 122                     auto dv = data.as_vec->as<uint32_t>();
 123                     for (int i = TheISA::VecRegSizeBytes / 4 - 1; i >= 0;
 124                          i--) {
 125                         ccprintf(outs, "%08x", dv[i]);
 126                         if (i != 0) {
 127                             ccprintf(outs, "_");
 128                         }
 129                     }
 130                     ccprintf(outs, "]");
 131                 }
 132                 break;
 133               case DataVecPred:
 134                 {
 135                     ccprintf(outs, " D=0b[");
 136                     auto pv = data.as_pred->as<uint8_t>();
 137                     for (int i = TheISA::VecPredRegSizeBits - 1; i >= 0; i--) {
 138                         ccprintf(outs, pv[i] ? "1" : "0");
 139                         if (i != 0 && i % 4 == 0) {
 140                             ccprintf(outs, "_");
 141                         }
 142                     }
 143                     ccprintf(outs, "]");
 144                 }
 145                 break;
 146               default:
 147                 ccprintf(outs, " D=%#018x", data.as_int);
 148                 break;
 149             }
 150         }
 151
 152         if (Debug::ExecEffAddr && getMemValid())
 153             outs << " A=0x" << hex << addr;
 154
 155         if (Debug::ExecFetchSeq && fetch_seq_valid)
 156             outs << "  FetchSeq=" << dec << fetch_seq;
 157
 158         if (Debug::ExecCPSeq && cp_seq_valid)
 159             outs << "  CPSeq=" << dec << cp_seq;
 160
 161         if (Debug::ExecFlags) {
 162             outs << "  flags=(";
 163             inst->printFlags(outs, "|");
 164             outs << ")";
 165         }
 166     }
 167
 168     //
 169     //  End of line...
 170     //
 171     outs << endl;
 172
 173     Trace::getDebugLogger()->dprintf_flag(
 174         when, thread->getCpuPtr()->name(), "ExecEnable", "%s",
 175         outs.str().c_str());
 176 }
 177
 178 void
 179 Trace::ExeTracerRecord::dump()
 180 {
 181     /*
 182      * The behavior this check tries to achieve is that if ExecMacro is on,
 183      * the macroop will be printed. If it's on and microops are also on, it's
 184      * printed before the microops start printing to give context. If the
 185      * microops aren't printed, then it's printed only when the final microop
 186      * finishes. Macroops then behave like regular instructions and don't
 187      * complete/print when they fault.
 188      */
 189     if (Debug::ExecMacro && staticInst->isMicroop() &&
 190         ((Debug::ExecMicro &&
 191             macroStaticInst && staticInst->isFirstMicroop()) ||
 192             (!Debug::ExecMicro &&
 193              macroStaticInst && staticInst->isLastMicroop()))) {
 194         traceInst(macroStaticInst, false);
 195     }
 196     if (Debug::ExecMicro || !staticInst->isMicroop()) {
 197         traceInst(staticInst, true);
 198     }
 199 }
 200
 201 } // namespace Trace