src/cpu/exetrace.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Lisa Hsu
  30  *          Nathan Binkert
  31  *          Steve Raasch
  32  */
  33
  34 #include <iomanip>
  35
  36 #include "base/loader/symtab.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/exetrace.hh"
  39 #include "cpu/static_inst.hh"
  40 #include "cpu/thread_context.hh"
  41 #include "enums/OpClass.hh"
  42
  43 using namespace std;
  44 using namespace TheISA;
  45
  46 namespace Trace {
  47
  48 void
  49 ExeTracerRecord::dumpTicks(ostream &outs)
  50 {
  51     ccprintf(outs, "%7d: ", when);
  52 }
  53
  54 void
  55 Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
  56 {
  57     ostream &outs = Trace::output();
  58
  59     if (IsOn(ExecTicks))
  60         dumpTicks(outs);
  61
  62     outs << thread->getCpuPtr()->name() << " ";
  63
  64     if (IsOn(ExecSpeculative))
  65         outs << (misspeculating ? "-" : "+") << " ";
  66
  67     if (IsOn(ExecThread))
  68         outs << "T" << thread->threadId() << " : ";
  69
  70     std::string sym_str;
  71     Addr sym_addr;
  72     if (debugSymbolTable
  73         && IsOn(ExecSymbol)
  74         && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) {
  75         if (PC != sym_addr)
  76             sym_str += csprintf("+%d", PC - sym_addr);
  77         outs << "@" << sym_str;
  78     }
  79     else {
  80         outs << "0x" << hex << PC;
  81     }
  82
  83     if (inst->isMicroop()) {
  84         outs << "." << setw(2) << dec << upc;
  85     } else {
  86         outs << "   ";
  87     }
  88
  89     outs << " : ";
  90
  91     //
  92     //  Print decoded instruction
  93     //
  94
  95     outs << setw(26) << left;
  96     outs << inst->disassemble(PC, debugSymbolTable);
  97
  98     if (ran) {
  99         outs << " : ";
 100
 101         if (IsOn(ExecOpClass)) {
 102             outs << Enums::OpClassStrings[inst->opClass()] << " : ";
 103         }
 104
 105         if (IsOn(ExecResult) && data_status != DataInvalid) {
 106             ccprintf(outs, " D=%#018x", data.as_int);
 107         }
 108
 109         if (IsOn(ExecEffAddr) && addr_valid)
 110             outs << " A=0x" << hex << addr;
 111
 112         if (IsOn(ExecFetchSeq) && fetch_seq_valid)
 113             outs << "  FetchSeq=" << dec << fetch_seq;
 114
 115         if (IsOn(ExecCPSeq) && cp_seq_valid)
 116             outs << "  CPSeq=" << dec << cp_seq;
 117     }
 118
 119     //
 120     //  End of line...
 121     //
 122     outs << endl;
 123 }
 124
 125 void
 126 Trace::ExeTracerRecord::dump()
 127 {
 128     /*
 129      * The behavior this check tries to achieve is that if ExecMacro is on,
 130      * the macroop will be printed. If it's on and microops are also on, it's
 131      * printed before the microops start printing to give context. If the
 132      * microops aren't printed, then it's printed only when the final microop
 133      * finishes. Macroops then behave like regular instructions and don't
 134      * complete/print when they fault.
 135      */
 136     if (IsOn(ExecMacro) && staticInst->isMicroop() &&
 137             ((IsOn(ExecMicro) &&
 138              macroStaticInst && staticInst->isFirstMicroop()) ||
 139             (!IsOn(ExecMicro) &&
 140              macroStaticInst && staticInst->isLastMicroop()))) {
 141         traceInst(macroStaticInst, false);
 142     }
 143     if (IsOn(ExecMicro) || !staticInst->isMicroop()) {
 144         traceInst(staticInst, true);
 145     }
 146 }
 147
 148 /* namespace Trace */ }
 149
 150 ////////////////////////////////////////////////////////////////////////
 151 //
 152 //  ExeTracer Simulation Object
 153 //
 154 Trace::ExeTracer *
 155 ExeTracerParams::create()
 156 {
 157     return new Trace::ExeTracer(this);
 158 };