85df19348b4c7c51573a76177776fbf4b0d57478
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
40 #include "arch/predecoder.hh"
41 #include "arch/regfile.hh"
42 #include "arch/utility.hh"
43 #include "base/loader/symtab.hh"
44 #include "base/socket.hh"
45 #include "config/full_system.hh"
46 #include "cpu/base.hh"
47 #include "cpu/exetrace.hh"
48 #include "cpu/static_inst.hh"
49 #include "sim/param.hh"
50 #include "sim/system.hh"
53 #include "arch/tlb.hh"
56 //XXX This is temporary
57 #include "arch/isa_specific.hh"
58 #include "cpu/m5legion_interface.h"
61 using namespace TheISA
;
63 #if THE_ISA == SPARC_ISA && FULL_SYSTEM
64 static int diffcount
= 0;
65 static bool wasMicro
= false;
69 SharedData
*shared_data
= NULL
;
70 ListenSocket
*cosim_listener
= NULL
;
75 int shmfd
= shmget('M' << 24 | getuid(), sizeof(SharedData
), 0777);
77 fatal("Couldn't get shared memory fd. Is Legion running?");
79 shared_data
= (SharedData
*)shmat(shmfd
, NULL
, SHM_RND
);
80 if (shared_data
== (SharedData
*)-1)
81 fatal("Couldn't allocate shared memory");
83 if (shared_data
->flags
!= OWN_M5
)
84 fatal("Shared memory has invalid owner");
86 if (shared_data
->version
!= VERSION
)
87 fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION
,
88 shared_data
->version
);
90 // step legion forward one cycle so we can get register values
91 shared_data
->flags
= OWN_LEGION
;
94 ////////////////////////////////////////////////////////////////////////
96 // Methods for the InstRecord object
99 #if THE_ISA == SPARC_ISA
101 inline char * genCenteredLabel(int length
, char * buffer
, char * label
)
103 int labelLength
= strlen(label
);
104 assert(labelLength
<= length
);
105 int leftPad
= (length
- labelLength
) / 2;
106 int rightPad
= length
- leftPad
- labelLength
;
108 sprintf(format
, "%%%ds%%s%%%ds", leftPad
, rightPad
);
109 sprintf(buffer
, format
, "", label
, "");
113 inline void printRegPair(ostream
& os
, char const * title
, uint64_t a
, uint64_t b
)
115 ccprintf(os
, " %16s | %#018x %s %#-018x \n",
116 title
, a
, (a
== b
) ? "|" : "X", b
);
119 inline void printColumnLabels(ostream
& os
)
121 static char * regLabel
= genCenteredLabel(16, new char[17], "Register");
122 static char * m5Label
= genCenteredLabel(18, new char[18], "M5");
123 static char * legionLabel
= genCenteredLabel(18, new char[18], "Legion");
124 ccprintf(os
, " %s | %s | %s \n", regLabel
, m5Label
, legionLabel
);
125 ccprintf(os
, "--------------------+-----------------------+-----------------------\n");
128 inline void printSectionHeader(ostream
& os
, char * name
)
130 char sectionString
[70];
131 genCenteredLabel(69, sectionString
, name
);
132 ccprintf(os
, "====================================================================\n");
133 ccprintf(os
, "%69s\n", sectionString
);
134 ccprintf(os
, "====================================================================\n");
137 inline void printLevelHeader(ostream
& os
, int level
)
139 char sectionString
[70];
141 sprintf(levelName
, "Trap stack level %d", level
);
142 genCenteredLabel(69, sectionString
, levelName
);
143 ccprintf(os
, "====================================================================\n");
144 ccprintf(os
, "%69s\n", sectionString
);
145 ccprintf(os
, "====================================================================\n");
151 Trace::InstRecord::dump()
153 ostream
&outs
= Trace::output();
155 DPRINTF(Sparc
, "Instruction: %#X\n", staticInst
->machInst
);
157 if (IsOn(ExecRegDelta
))
161 #if THE_ISA == SPARC_ISA
163 //Don't print what happens for each micro-op, just print out
164 //once at the last op, and for regular instructions.
165 if(!staticInst
->isMicroop() || staticInst
->isLastMicroop())
170 cosim_listener
= new ListenSocket();
171 while(!cosim_listener
->listen(port
, true))
173 DPRINTF(GDBMisc
, "Can't bind port %d\n", port
);
176 ccprintf(cerr
, "Listening for cosimulator on port %d\n", port
);
177 fd
= cosim_listener
->accept();
179 char prefix
[] = "goli";
180 for(int p
= 0; p
< 4; p
++)
182 for(int i
= 0; i
< 8; i
++)
185 int res
= read(fd
, ®Val
, sizeof(regVal
));
187 panic("First read call failed! %s\n", strerror(errno
));
188 regVal
= TheISA::gtoh(regVal
);
189 uint64_t realRegVal
= thread
->readIntReg(p
* 8 + i
);
190 if((regVal
& 0xffffffffULL
) != (realRegVal
& 0xffffffffULL
))
192 DPRINTF(ExecRegDelta
, "Register %s%d should be %#x but is %#x.\n", prefix
[p
], i
, regVal
, realRegVal
);
195 //ccprintf(outs, "%s%d m5 = %#x statetrace = %#x\n", prefix[p], i, realRegVal, regVal);
198 /*for(int f = 0; f <= 62; f+=2)
201 int res = read(fd, ®Val, sizeof(regVal));
203 panic("First read call failed! %s\n", strerror(errno));
204 regVal = TheISA::gtoh(regVal);
205 uint64_t realRegVal = thread->readFloatRegBits(f, 64);
206 if(regVal != realRegVal)
208 DPRINTF(ExecRegDelta, "Register f%d should be %#x but is %#x.\n", f, regVal, realRegVal);
212 int res
= read(fd
, ®Val
, sizeof(regVal
));
214 panic("First read call failed! %s\n", strerror(errno
));
215 regVal
= TheISA::gtoh(regVal
);
216 uint64_t realRegVal
= thread
->readNextPC();
217 if(regVal
!= realRegVal
)
219 DPRINTF(ExecRegDelta
, "Register pc should be %#x but is %#x.\n", regVal
, realRegVal
);
222 res
= read(fd
, ®Val
, sizeof(regVal
));
224 panic("First read call failed! %s\n", strerror(errno
));
225 regVal
= TheISA::gtoh(regVal
);
226 realRegVal
= thread
->readNextNPC();
227 if(regVal
!= realRegVal
)
229 DPRINTF(ExecRegDelta
, "Register npc should be %#x but is %#x.\n", regVal
, realRegVal
);
232 res
= read(fd
, ®Val
, sizeof(regVal
));
234 panic("First read call failed! %s\n", strerror(errno
));
235 regVal
= TheISA::gtoh(regVal
);
236 realRegVal
= thread
->readIntReg(SparcISA::NumIntArchRegs
+ 2);
237 if((regVal
& 0xF) != (realRegVal
& 0xF))
239 DPRINTF(ExecRegDelta
, "Register ccr should be %#x but is %#x.\n", regVal
, realRegVal
);
245 #if 0 //THE_ISA == SPARC_ISA
246 //Don't print what happens for each micro-op, just print out
247 //once at the last op, and for regular instructions.
248 if(!staticInst
->isMicroop() || staticInst
->isLastMicroop())
250 static uint64_t regs
[32] = {
251 0, 0, 0, 0, 0, 0, 0, 0,
252 0, 0, 0, 0, 0, 0, 0, 0,
253 0, 0, 0, 0, 0, 0, 0, 0,
254 0, 0, 0, 0, 0, 0, 0, 0};
255 static uint64_t ccr
= 0;
256 static uint64_t y
= 0;
257 static uint64_t floats
[32];
259 static const char * prefixes
[4] = {"G", "O", "L", "I"};
262 outs
<< "PC = " << thread
->readNextPC();
263 outs
<< " NPC = " << thread
->readNextNPC();
264 newVal
= thread
->readIntReg(SparcISA::NumIntArchRegs
+ 2);
265 //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_CCR);
268 outs
<< " CCR = " << newVal
;
271 newVal
= thread
->readIntReg(SparcISA::NumIntArchRegs
+ 1);
272 //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_Y);
275 outs
<< " Y = " << newVal
;
278 for(int y
= 0; y
< 4; y
++)
280 for(int x
= 0; x
< 8; x
++)
282 int index
= x
+ 8 * y
;
283 newVal
= thread
->readIntReg(index
);
284 if(regs
[index
] != newVal
)
286 outs
<< " " << prefixes
[y
] << dec
<< x
<< " = " << hex
<< newVal
;
287 regs
[index
] = newVal
;
291 for(int y
= 0; y
< 32; y
++)
293 newVal
= thread
->readFloatRegBits(2 * y
, 64);
294 if(floats
[y
] != newVal
)
296 outs
<< " F" << dec
<< (2 * y
) << " = " << hex
<< newVal
;
305 } else if (IsOn(ExecIntel
)) {
306 ccprintf(outs
, "%7d ) ", when
);
307 outs
<< "0x" << hex
<< PC
<< ":\t";
308 if (staticInst
->isLoad()) {
309 ccprintf(outs
, "<RD %#x>", addr
);
310 } else if (staticInst
->isStore()) {
311 ccprintf(outs
, "<WR %#x>", addr
);
316 ccprintf(outs
, "%7d: ", when
);
318 outs
<< thread
->getCpuPtr()->name() << " ";
320 if (IsOn(ExecSpeculative
))
321 outs
<< (misspeculating
? "-" : "+") << " ";
323 if (IsOn(ExecThread
))
324 outs
<< "T" << thread
->getThreadNum() << " : ";
330 && debugSymbolTable
->findNearestSymbol(PC
, sym_str
, sym_addr
)
331 && IsOn(ExecSymbol
)) {
333 sym_str
+= csprintf("+%d", PC
- sym_addr
);
334 outs
<< "@" << sym_str
<< " : ";
337 outs
<< "0x" << hex
<< PC
<< " : ";
341 // Print decoded instruction
344 #if defined(__GNUC__) && (__GNUC__ < 3)
345 // There's a bug in gcc 2.x library that prevents setw()
346 // from working properly on strings
347 string
mc(staticInst
->disassemble(PC
, debugSymbolTable
));
348 while (mc
.length() < 26)
352 outs
<< setw(26) << left
<< staticInst
->disassemble(PC
, debugSymbolTable
);
357 if (IsOn(ExecOpClass
)) {
358 outs
<< opClassStrings
[staticInst
->opClass()] << " : ";
361 if (IsOn(ExecResult
) && data_status
!= DataInvalid
) {
364 if (data_status
== DataDouble
)
365 ccprintf(outs
, "%f", data
.as_double
);
367 ccprintf(outs
, "%#018x", data
.as_int
);
369 ccprintf(outs
, "%#018x", data
.as_int
);
373 if (IsOn(ExecEffAddr
) && addr_valid
)
374 outs
<< " A=0x" << hex
<< addr
;
376 if (IsOn(ExecIntRegs
) && regs_valid
) {
377 for (int i
= 0; i
< TheISA::NumIntRegs
;)
378 for (int j
= i
+ 1; i
<= j
; i
++)
379 ccprintf(outs
, "r%02d = %#018x%s", i
,
380 iregs
->regs
.readReg(i
),
381 ((i
== j
) ? "\n" : " "));
385 if (IsOn(ExecFetchSeq
) && fetch_seq_valid
)
386 outs
<< " FetchSeq=" << dec
<< fetch_seq
;
388 if (IsOn(ExecCPSeq
) && cp_seq_valid
)
389 outs
<< " CPSeq=" << dec
<< cp_seq
;
396 #if THE_ISA == SPARC_ISA && FULL_SYSTEM
397 static TheISA::Predecoder
predecoder(NULL
);
399 if (IsOn(ExecLegion
))
401 bool compared
= false;
404 bool diffInst
= false;
405 bool diffIntRegs
= false;
406 bool diffFpRegs
= false;
407 bool diffTpc
= false;
408 bool diffTnpc
= false;
409 bool diffTstate
= false;
411 bool diffTba
= false;
412 bool diffHpstate
= false;
413 bool diffHtstate
= false;
414 bool diffHtba
= false;
415 bool diffPstate
= false;
417 bool diffFsr
= false;
418 bool diffCcr
= false;
421 bool diffAsi
= false;
422 bool diffPil
= false;
423 bool diffCwp
= false;
424 bool diffCansave
= false;
425 bool diffCanrestore
= false;
426 bool diffOtherwin
= false;
427 bool diffCleanwin
= false;
428 bool diffTlb
= false;
434 // We took a trap on a micro-op...
435 if (wasMicro
&& !staticInst
->isMicroop())
437 // let's skip comparing this tick
439 if (shared_data
->flags
== OWN_M5
) {
440 shared_data
->flags
= OWN_LEGION
;
447 if (staticInst
->isLastMicroop())
449 else if (staticInst
->isMicroop())
453 if(!staticInst
->isMicroop() || staticInst
->isLastMicroop()) {
455 if (shared_data
->flags
== OWN_M5
) {
456 m5Pc
= PC
& TheISA::PAddrImplMask
;
457 if (bits(shared_data
->pstate
,3,3)) {
460 lgnPc
= shared_data
->pc
& TheISA::PAddrImplMask
;
464 if (shared_data
->cycle_count
!=
465 thread
->getCpuPtr()->instCount())
468 if (shared_data
->instruction
!=
469 (SparcISA::MachInst
)staticInst
->machInst
) {
472 // assume we have %g0 working correctly
473 for (int i
= 1; i
< TheISA::NumIntArchRegs
; i
++) {
474 if (thread
->readIntReg(i
) != shared_data
->intregs
[i
]) {
478 for (int i
= 0; i
< TheISA::NumFloatRegs
/2; i
++) {
479 if (thread
->readFloatRegBits(i
*2,FloatRegFile::DoubleWidth
) != shared_data
->fpregs
[i
]) {
483 uint64_t oldTl
= thread
->readMiscRegNoEffect(MISCREG_TL
);
484 if (oldTl
!= shared_data
->tl
)
486 for (int i
= 1; i
<= MaxTL
; i
++) {
487 thread
->setMiscRegNoEffect(MISCREG_TL
, i
);
488 if (thread
->readMiscRegNoEffect(MISCREG_TPC
) !=
489 shared_data
->tpc
[i
-1])
491 if (thread
->readMiscRegNoEffect(MISCREG_TNPC
) !=
492 shared_data
->tnpc
[i
-1])
494 if (thread
->readMiscRegNoEffect(MISCREG_TSTATE
) !=
495 shared_data
->tstate
[i
-1])
497 if (thread
->readMiscRegNoEffect(MISCREG_TT
) !=
498 shared_data
->tt
[i
-1])
500 if (thread
->readMiscRegNoEffect(MISCREG_HTSTATE
) !=
501 shared_data
->htstate
[i
-1])
504 thread
->setMiscRegNoEffect(MISCREG_TL
, oldTl
);
506 if(shared_data
->tba
!= thread
->readMiscRegNoEffect(MISCREG_TBA
))
508 //When the hpstate register is read by an instruction,
509 //legion has bit 11 set. When it's in storage, it doesn't.
510 //Since we don't directly support seperate interpretations
511 //of the registers like that, the bit is always set to 1 and
512 //we just don't compare it. It's not supposed to matter
514 if((shared_data
->hpstate
| (1 << 11)) != thread
->readMiscRegNoEffect(MISCREG_HPSTATE
))
516 if(shared_data
->htba
!= thread
->readMiscRegNoEffect(MISCREG_HTBA
))
518 if(shared_data
->pstate
!= thread
->readMiscRegNoEffect(MISCREG_PSTATE
))
520 //if(shared_data->y != thread->readMiscRegNoEffect(MISCREG_Y))
522 thread
->readIntReg(NumIntArchRegs
+ 1))
524 if(shared_data
->fsr
!= thread
->readMiscRegNoEffect(MISCREG_FSR
)) {
526 if (mbits(shared_data
->fsr
, 63,10) ==
527 mbits(thread
->readMiscRegNoEffect(MISCREG_FSR
), 63,10)) {
528 thread
->setMiscRegNoEffect(MISCREG_FSR
, shared_data
->fsr
);
532 //if(shared_data->ccr != thread->readMiscRegNoEffect(MISCREG_CCR))
533 if(shared_data
->ccr
!=
534 thread
->readIntReg(NumIntArchRegs
+ 2))
536 if(shared_data
->gl
!= thread
->readMiscRegNoEffect(MISCREG_GL
))
538 if(shared_data
->asi
!= thread
->readMiscRegNoEffect(MISCREG_ASI
))
540 if(shared_data
->pil
!= thread
->readMiscRegNoEffect(MISCREG_PIL
))
542 if(shared_data
->cwp
!= thread
->readMiscRegNoEffect(MISCREG_CWP
))
544 //if(shared_data->cansave != thread->readMiscRegNoEffect(MISCREG_CANSAVE))
545 if(shared_data
->cansave
!=
546 thread
->readIntReg(NumIntArchRegs
+ 3))
548 //if(shared_data->canrestore !=
549 // thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
550 if(shared_data
->canrestore
!=
551 thread
->readIntReg(NumIntArchRegs
+ 4))
552 diffCanrestore
= true;
553 //if(shared_data->otherwin != thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
554 if(shared_data
->otherwin
!=
555 thread
->readIntReg(NumIntArchRegs
+ 6))
557 //if(shared_data->cleanwin != thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
558 if(shared_data
->cleanwin
!=
559 thread
->readIntReg(NumIntArchRegs
+ 5))
562 for (int i
= 0; i
< 64; i
++) {
563 if (shared_data
->itb
[i
] != thread
->getITBPtr()->TteRead(i
))
565 if (shared_data
->dtb
[i
] != thread
->getDTBPtr()->TteRead(i
))
569 if (diffPC
|| diffCC
|| diffInst
|| diffIntRegs
||
570 diffFpRegs
|| diffTpc
|| diffTnpc
|| diffTstate
||
571 diffTt
|| diffHpstate
|| diffHtstate
|| diffHtba
||
572 diffPstate
|| diffY
|| diffCcr
|| diffTl
|| diffFsr
||
573 diffGl
|| diffAsi
|| diffPil
|| diffCwp
|| diffCansave
||
574 diffCanrestore
|| diffOtherwin
|| diffCleanwin
|| diffTlb
)
577 outs
<< "Differences found between M5 and Legion:";
583 outs
<< " [Instruction]";
585 outs
<< " [IntRegs]";
597 outs
<< " [Hpstate]";
599 outs
<< " [Htstate]";
621 outs
<< " [Cansave]";
623 outs
<< " [Canrestore]";
625 outs
<< " [Otherwin]";
627 outs
<< " [Cleanwin]";
630 outs
<< endl
<< endl
;
632 outs
<< right
<< setfill(' ') << setw(15)
633 << "M5 PC: " << "0x"<< setw(16) << setfill('0')
634 << hex
<< m5Pc
<< endl
;
635 outs
<< setfill(' ') << setw(15)
636 << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
637 << lgnPc
<< endl
<< endl
;
639 outs
<< right
<< setfill(' ') << setw(15)
640 << "M5 CC: " << "0x"<< setw(16) << setfill('0')
641 << hex
<< thread
->getCpuPtr()->instCount() << endl
;
642 outs
<< setfill(' ') << setw(15)
643 << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex
644 << shared_data
->cycle_count
<< endl
<< endl
;
646 outs
<< setfill(' ') << setw(15)
647 << "M5 Inst: " << "0x"<< setw(8)
648 << setfill('0') << hex
<< staticInst
->machInst
649 << staticInst
->disassemble(m5Pc
, debugSymbolTable
)
652 predecoder
.setTC(thread
);
653 predecoder
.moreBytes(m5Pc
, m5Pc
,
654 shared_data
->instruction
);
656 assert(predecoder
.extMachInstReady());
658 StaticInstPtr legionInst
=
659 StaticInst::decode(predecoder
.getExtMachInst(), lgnPc
);
660 outs
<< setfill(' ') << setw(15)
662 << "0x" << setw(8) << setfill('0') << hex
663 << shared_data
->instruction
664 << legionInst
->disassemble(lgnPc
, debugSymbolTable
)
667 printSectionHeader(outs
, "General State");
668 printColumnLabels(outs
);
669 printRegPair(outs
, "HPstate",
670 thread
->readMiscRegNoEffect(MISCREG_HPSTATE
),
671 shared_data
->hpstate
| (1 << 11));
672 printRegPair(outs
, "Htba",
673 thread
->readMiscRegNoEffect(MISCREG_HTBA
),
675 printRegPair(outs
, "Pstate",
676 thread
->readMiscRegNoEffect(MISCREG_PSTATE
),
677 shared_data
->pstate
);
678 printRegPair(outs
, "Y",
679 //thread->readMiscRegNoEffect(MISCREG_Y),
680 thread
->readIntReg(NumIntArchRegs
+ 1),
682 printRegPair(outs
, "FSR",
683 thread
->readMiscRegNoEffect(MISCREG_FSR
),
685 printRegPair(outs
, "Ccr",
686 //thread->readMiscRegNoEffect(MISCREG_CCR),
687 thread
->readIntReg(NumIntArchRegs
+ 2),
689 printRegPair(outs
, "Tl",
690 thread
->readMiscRegNoEffect(MISCREG_TL
),
692 printRegPair(outs
, "Gl",
693 thread
->readMiscRegNoEffect(MISCREG_GL
),
695 printRegPair(outs
, "Asi",
696 thread
->readMiscRegNoEffect(MISCREG_ASI
),
698 printRegPair(outs
, "Pil",
699 thread
->readMiscRegNoEffect(MISCREG_PIL
),
701 printRegPair(outs
, "Cwp",
702 thread
->readMiscRegNoEffect(MISCREG_CWP
),
704 printRegPair(outs
, "Cansave",
705 //thread->readMiscRegNoEffect(MISCREG_CANSAVE),
706 thread
->readIntReg(NumIntArchRegs
+ 3),
707 shared_data
->cansave
);
708 printRegPair(outs
, "Canrestore",
709 //thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
710 thread
->readIntReg(NumIntArchRegs
+ 4),
711 shared_data
->canrestore
);
712 printRegPair(outs
, "Otherwin",
713 //thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
714 thread
->readIntReg(NumIntArchRegs
+ 6),
715 shared_data
->otherwin
);
716 printRegPair(outs
, "Cleanwin",
717 //thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
718 thread
->readIntReg(NumIntArchRegs
+ 5),
719 shared_data
->cleanwin
);
721 for (int i
= 1; i
<= MaxTL
; i
++) {
722 printLevelHeader(outs
, i
);
723 printColumnLabels(outs
);
724 thread
->setMiscRegNoEffect(MISCREG_TL
, i
);
725 printRegPair(outs
, "Tpc",
726 thread
->readMiscRegNoEffect(MISCREG_TPC
),
727 shared_data
->tpc
[i
-1]);
728 printRegPair(outs
, "Tnpc",
729 thread
->readMiscRegNoEffect(MISCREG_TNPC
),
730 shared_data
->tnpc
[i
-1]);
731 printRegPair(outs
, "Tstate",
732 thread
->readMiscRegNoEffect(MISCREG_TSTATE
),
733 shared_data
->tstate
[i
-1]);
734 printRegPair(outs
, "Tt",
735 thread
->readMiscRegNoEffect(MISCREG_TT
),
736 shared_data
->tt
[i
-1]);
737 printRegPair(outs
, "Htstate",
738 thread
->readMiscRegNoEffect(MISCREG_HTSTATE
),
739 shared_data
->htstate
[i
-1]);
741 thread
->setMiscRegNoEffect(MISCREG_TL
, oldTl
);
744 printSectionHeader(outs
, "General Purpose Registers");
745 static const char * regtypes
[4] = {"%g", "%o", "%l", "%i"};
746 for(int y
= 0; y
< 4; y
++) {
747 for(int x
= 0; x
< 8; x
++) {
749 sprintf(label
, "%s%d", regtypes
[y
], x
);
750 printRegPair(outs
, label
,
751 thread
->readIntReg(y
*8+x
),
752 shared_data
->intregs
[y
*8+x
]);
756 for (int x
= 0; x
< 32; x
++) {
758 sprintf(label
, "%%f%d", x
);
759 printRegPair(outs
, label
,
760 thread
->readFloatRegBits(x
*2,FloatRegFile::DoubleWidth
),
761 shared_data
->fpregs
[x
]);
765 printColumnLabels(outs
);
767 for (int x
= 0; x
< 64; x
++) {
768 if (shared_data
->itb
[x
] != ULL(0xFFFFFFFFFFFFFFFF) ||
769 thread
->getITBPtr()->TteRead(x
) != ULL(0xFFFFFFFFFFFFFFFF)) {
770 sprintf(label
, "I-TLB:%02d", x
);
771 printRegPair(outs
, label
, thread
->getITBPtr()->TteRead(x
),
772 shared_data
->itb
[x
]);
775 for (int x
= 0; x
< 64; x
++) {
776 if (shared_data
->dtb
[x
] != ULL(0xFFFFFFFFFFFFFFFF) ||
777 thread
->getDTBPtr()->TteRead(x
) != ULL(0xFFFFFFFFFFFFFFFF)) {
778 sprintf(label
, "D-TLB:%02d", x
);
779 printRegPair(outs
, label
, thread
->getDTBPtr()->TteRead(x
),
780 shared_data
->dtb
[x
]);
783 thread
->getITBPtr()->dumpAll();
784 thread
->getDTBPtr()->dumpAll();
789 fatal("Differences found between Legion and M5\n");
794 shared_data
->flags
= OWN_LEGION
;
802 /* namespace Trace */ }