src/cpu/exetrace.cc

   1 /*
   2  * Copyright (c) 2017, 2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include "cpu/exetrace.hh"
  42
  43 #include <iomanip>
  44 #include <sstream>
  45
  46 #include "arch/utility.hh"
  47 #include "base/loader/symtab.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/base.hh"
  50 #include "cpu/static_inst.hh"
  51 #include "cpu/thread_context.hh"
  52 #include "debug/ExecAll.hh"
  53 #include "debug/FmtTicksOff.hh"
  54 #include "enums/OpClass.hh"
  55
  56 using namespace std;
  57 using namespace TheISA;
  58
  59 namespace Trace {
  60
  61 void
  62 Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
  63 {
  64     std::stringstream outs;
  65
  66     if (!Debug::ExecUser || !Debug::ExecKernel) {
  67         bool in_user_mode = TheISA::inUserMode(thread);
  68         if (in_user_mode && !Debug::ExecUser) return;
  69         if (!in_user_mode && !Debug::ExecKernel) return;
  70     }
  71
  72     if (Debug::ExecAsid)
  73         outs << "A" << dec << TheISA::getExecutingAsid(thread) << " ";
  74
  75     if (Debug::ExecThread)
  76         outs << "T" << thread->threadId() << " : ";
  77
  78     Addr cur_pc = pc.instAddr();
  79     Loader::SymbolTable::const_iterator it;
  80     if (Debug::ExecSymbol && (!FullSystem || !inUserMode(thread)) &&
  81             (it = Loader::debugSymbolTable.findNearest(cur_pc)) !=
  82                 Loader::debugSymbolTable.end()) {
  83         Addr delta = cur_pc - it->address;
  84         if (delta)
  85             ccprintf(outs, "@%s+%d", it->name, delta);
  86         else
  87             ccprintf(outs, "@%s", it->name);
  88     } else {
  89         ccprintf(outs, "%#x", cur_pc);
  90     }
  91
  92     if (inst->isMicroop()) {
  93         ccprintf(outs, ".%2d", pc.microPC());
  94     } else {
  95         ccprintf(outs, "   ");
  96     }
  97
  98     ccprintf(outs, " : ");
  99
 100     //
 101     //  Print decoded instruction
 102     //
 103
 104     outs << setw(26) << left;
 105     outs << inst->disassemble(cur_pc, &Loader::debugSymbolTable);
 106
 107     if (ran) {
 108         outs << " : ";
 109
 110         if (Debug::ExecOpClass) {
 111             outs << Enums::OpClassStrings[inst->opClass()] << " : ";
 112         }
 113
 114         if (Debug::ExecResult && !predicate) {
 115             outs << "Predicated False";
 116         }
 117
 118         if (Debug::ExecResult && data_status != DataInvalid) {
 119             switch (data_status) {
 120               case DataVec:
 121                 {
 122                     ccprintf(outs, " D=0x[");
 123                     auto dv = data.as_vec->as<uint32_t>();
 124                     for (int i = TheISA::VecRegSizeBytes / 4 - 1; i >= 0;
 125                          i--) {
 126                         ccprintf(outs, "%08x", dv[i]);
 127                         if (i != 0) {
 128                             ccprintf(outs, "_");
 129                         }
 130                     }
 131                     ccprintf(outs, "]");
 132                 }
 133                 break;
 134               case DataVecPred:
 135                 {
 136                     ccprintf(outs, " D=0b[");
 137                     auto pv = data.as_pred->as<uint8_t>();
 138                     for (int i = TheISA::VecPredRegSizeBits - 1; i >= 0; i--) {
 139                         ccprintf(outs, pv[i] ? "1" : "0");
 140                         if (i != 0 && i % 4 == 0) {
 141                             ccprintf(outs, "_");
 142                         }
 143                     }
 144                     ccprintf(outs, "]");
 145                 }
 146                 break;
 147               default:
 148                 ccprintf(outs, " D=%#018x", data.as_int);
 149                 break;
 150             }
 151         }
 152
 153         if (Debug::ExecEffAddr && getMemValid())
 154             outs << " A=0x" << hex << addr;
 155
 156         if (Debug::ExecFetchSeq && fetch_seq_valid)
 157             outs << "  FetchSeq=" << dec << fetch_seq;
 158
 159         if (Debug::ExecCPSeq && cp_seq_valid)
 160             outs << "  CPSeq=" << dec << cp_seq;
 161
 162         if (Debug::ExecFlags) {
 163             outs << "  flags=(";
 164             inst->printFlags(outs, "|");
 165             outs << ")";
 166         }
 167     }
 168
 169     //
 170     //  End of line...
 171     //
 172     outs << endl;
 173
 174     Trace::getDebugLogger()->dprintf_flag(
 175         when, thread->getCpuPtr()->name(), "ExecEnable", "%s",
 176         outs.str().c_str());
 177 }
 178
 179 void
 180 Trace::ExeTracerRecord::dump()
 181 {
 182     /*
 183      * The behavior this check tries to achieve is that if ExecMacro is on,
 184      * the macroop will be printed. If it's on and microops are also on, it's
 185      * printed before the microops start printing to give context. If the
 186      * microops aren't printed, then it's printed only when the final microop
 187      * finishes. Macroops then behave like regular instructions and don't
 188      * complete/print when they fault.
 189      */
 190     if (Debug::ExecMacro && staticInst->isMicroop() &&
 191         ((Debug::ExecMicro &&
 192             macroStaticInst && staticInst->isFirstMicroop()) ||
 193             (!Debug::ExecMicro &&
 194              macroStaticInst && staticInst->isLastMicroop()))) {
 195         traceInst(macroStaticInst, false);
 196     }
 197     if (Debug::ExecMicro || !staticInst->isMicroop()) {
 198         traceInst(staticInst, true);
 199     }
 200 }
 201
 202 } // namespace Trace
 203
 204 ////////////////////////////////////////////////////////////////////////
 205 //
 206 //  ExeTracer Simulation Object
 207 //
 208 Trace::ExeTracer *
 209 ExeTracerParams::create()
 210 {
 211     return new Trace::ExeTracer(this);
 212 }