src/cpu/exetrace.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Lisa Hsu
  30  *          Nathan Binkert
  31  *          Steve Raasch
  32  */
  33
  34 #include <iomanip>
  35
  36 #include "base/loader/symtab.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/exetrace.hh"
  39 #include "cpu/static_inst.hh"
  40 #include "cpu/thread_context.hh"
  41 #include "config/the_isa.hh"
  42 #include "enums/OpClass.hh"
  43
  44 using namespace std;
  45 using namespace TheISA;
  46
  47 namespace Trace {
  48
  49 void
  50 ExeTracerRecord::dumpTicks(ostream &outs)
  51 {
  52     ccprintf(outs, "%7d: ", when);
  53 }
  54
  55 void
  56 Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
  57 {
  58     ostream &outs = Trace::output();
  59
  60     if (IsOn(ExecTicks))
  61         dumpTicks(outs);
  62
  63     outs << thread->getCpuPtr()->name() << " ";
  64
  65     if (IsOn(ExecSpeculative))
  66         outs << (misspeculating ? "-" : "+") << " ";
  67
  68     if (IsOn(ExecThread))
  69         outs << "T" << thread->threadId() << " : ";
  70
  71     std::string sym_str;
  72     Addr sym_addr;
  73     if (debugSymbolTable
  74         && IsOn(ExecSymbol)
  75 #if FULL_SYSTEM
  76         && !inUserMode(thread)
  77 #endif
  78         && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) {
  79         if (PC != sym_addr)
  80             sym_str += csprintf("+%d", PC - sym_addr);
  81         outs << "@" << sym_str;
  82     }
  83     else {
  84         outs << "0x" << hex << PC;
  85     }
  86
  87     if (inst->isMicroop()) {
  88         outs << "." << setw(2) << dec << upc;
  89     } else {
  90         outs << "   ";
  91     }
  92
  93     outs << " : ";
  94
  95     //
  96     //  Print decoded instruction
  97     //
  98
  99     outs << setw(26) << left;
 100     outs << inst->disassemble(PC, debugSymbolTable);
 101
 102     if (ran) {
 103         outs << " : ";
 104
 105         if (IsOn(ExecOpClass)) {
 106             outs << Enums::OpClassStrings[inst->opClass()] << " : ";
 107         }
 108
 109         if (IsOn(ExecResult) && data_status != DataInvalid) {
 110             ccprintf(outs, " D=%#018x", data.as_int);
 111         }
 112
 113         if (IsOn(ExecEffAddr) && addr_valid)
 114             outs << " A=0x" << hex << addr;
 115
 116         if (IsOn(ExecFetchSeq) && fetch_seq_valid)
 117             outs << "  FetchSeq=" << dec << fetch_seq;
 118
 119         if (IsOn(ExecCPSeq) && cp_seq_valid)
 120             outs << "  CPSeq=" << dec << cp_seq;
 121     }
 122
 123     //
 124     //  End of line...
 125     //
 126     outs << endl;
 127 }
 128
 129 void
 130 Trace::ExeTracerRecord::dump()
 131 {
 132     /*
 133      * The behavior this check tries to achieve is that if ExecMacro is on,
 134      * the macroop will be printed. If it's on and microops are also on, it's
 135      * printed before the microops start printing to give context. If the
 136      * microops aren't printed, then it's printed only when the final microop
 137      * finishes. Macroops then behave like regular instructions and don't
 138      * complete/print when they fault.
 139      */
 140     if (IsOn(ExecMacro) && staticInst->isMicroop() &&
 141             ((IsOn(ExecMicro) &&
 142              macroStaticInst && staticInst->isFirstMicroop()) ||
 143             (!IsOn(ExecMicro) &&
 144              macroStaticInst && staticInst->isLastMicroop()))) {
 145         traceInst(macroStaticInst, false);
 146     }
 147     if (IsOn(ExecMicro) || !staticInst->isMicroop()) {
 148         traceInst(staticInst, true);
 149     }
 150 }
 151
 152 /* namespace Trace */ }
 153
 154 ////////////////////////////////////////////////////////////////////////
 155 //
 156 //  ExeTracer Simulation Object
 157 //
 158 Trace::ExeTracer *
 159 ExeTracerParams::create()
 160 {
 161     return new Trace::ExeTracer(this);
 162 };