2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
39 #include "arch/regfile.hh"
40 #include "arch/utility.hh"
41 #include "base/loader/symtab.hh"
42 #include "config/full_system.hh"
43 #include "cpu/base.hh"
44 #include "cpu/exetrace.hh"
45 #include "cpu/static_inst.hh"
46 #include "sim/param.hh"
47 #include "sim/system.hh"
50 #include "arch/tlb.hh"
53 //XXX This is temporary
54 #include "arch/isa_specific.hh"
55 #include "cpu/m5legion_interface.h"
58 using namespace TheISA
;
60 #if THE_ISA == SPARC_ISA && FULL_SYSTEM
61 static int diffcount
= 0;
65 SharedData
*shared_data
= NULL
;
68 ////////////////////////////////////////////////////////////////////////
70 // Methods for the InstRecord object
73 #if THE_ISA == SPARC_ISA
75 inline char * genCenteredLabel(int length
, char * buffer
, char * label
)
77 int labelLength
= strlen(label
);
78 assert(labelLength
<= length
);
79 int leftPad
= (length
- labelLength
) / 2;
80 int rightPad
= length
- leftPad
- labelLength
;
82 sprintf(format
, "%%%ds%%s%%%ds", leftPad
, rightPad
);
83 sprintf(buffer
, format
, "", label
, "");
87 inline void printRegPair(ostream
& os
, char const * title
, uint64_t a
, uint64_t b
)
89 ccprintf(os
, " %16s | %#018x %s %#-018x \n",
90 title
, a
, (a
== b
) ? "|" : "X", b
);
93 inline void printColumnLabels(ostream
& os
)
95 static char * regLabel
= genCenteredLabel(16, new char[17], "Register");
96 static char * m5Label
= genCenteredLabel(18, new char[18], "M5");
97 static char * legionLabel
= genCenteredLabel(18, new char[18], "Legion");
98 ccprintf(os
, " %s | %s | %s \n", regLabel
, m5Label
, legionLabel
);
99 ccprintf(os
, "--------------------+-----------------------+-----------------------\n");
102 inline void printSectionHeader(ostream
& os
, char * name
)
104 char sectionString
[70];
105 genCenteredLabel(69, sectionString
, name
);
106 ccprintf(os
, "====================================================================\n");
107 ccprintf(os
, "%69s\n", sectionString
);
108 ccprintf(os
, "====================================================================\n");
111 inline void printLevelHeader(ostream
& os
, int level
)
113 char sectionString
[70];
115 sprintf(levelName
, "Trap stack level %d", level
);
116 genCenteredLabel(69, sectionString
, levelName
);
117 ccprintf(os
, "====================================================================\n");
118 ccprintf(os
, "%69s\n", sectionString
);
119 ccprintf(os
, "====================================================================\n");
125 Trace::InstRecord::dump(ostream
&outs
)
127 if (flags
[PRINT_REG_DELTA
])
129 #if THE_ISA == SPARC_ISA
130 //Don't print what happens for each micro-op, just print out
131 //once at the last op, and for regular instructions.
132 if(!staticInst
->isMicroOp() || staticInst
->isLastMicroOp())
134 static uint64_t regs
[32] = {
135 0, 0, 0, 0, 0, 0, 0, 0,
136 0, 0, 0, 0, 0, 0, 0, 0,
137 0, 0, 0, 0, 0, 0, 0, 0,
138 0, 0, 0, 0, 0, 0, 0, 0};
139 static uint64_t ccr
= 0;
140 static uint64_t y
= 0;
141 static uint64_t floats
[32];
143 static const char * prefixes
[4] = {"G", "O", "L", "I"};
146 outs
<< "PC = " << thread
->readNextPC();
147 outs
<< " NPC = " << thread
->readNextNPC();
148 newVal
= thread
->readMiscReg(SparcISA::MISCREG_CCR
);
151 outs
<< " CCR = " << newVal
;
154 newVal
= thread
->readMiscReg(SparcISA::MISCREG_Y
);
157 outs
<< " Y = " << newVal
;
160 for(int y
= 0; y
< 4; y
++)
162 for(int x
= 0; x
< 8; x
++)
164 int index
= x
+ 8 * y
;
165 newVal
= thread
->readIntReg(index
);
166 if(regs
[index
] != newVal
)
168 outs
<< " " << prefixes
[y
] << dec
<< x
<< " = " << hex
<< newVal
;
169 regs
[index
] = newVal
;
173 for(int y
= 0; y
< 32; y
++)
175 newVal
= thread
->readFloatRegBits(2 * y
, 64);
176 if(floats
[y
] != newVal
)
178 outs
<< " F" << dec
<< (2 * y
) << " = " << hex
<< newVal
;
186 else if (flags
[INTEL_FORMAT
]) {
188 bool is_trace_system
= (thread
->getCpuPtr()->system
->name() == trace_system
);
190 bool is_trace_system
= true;
192 if (is_trace_system
) {
193 ccprintf(outs
, "%7d ) ", cycle
);
194 outs
<< "0x" << hex
<< PC
<< ":\t";
195 if (staticInst
->isLoad()) {
196 outs
<< "<RD 0x" << hex
<< addr
;
198 } else if (staticInst
->isStore()) {
199 outs
<< "<WR 0x" << hex
<< addr
;
205 if (flags
[PRINT_CYCLE
])
206 ccprintf(outs
, "%7d: ", cycle
);
208 outs
<< thread
->getCpuPtr()->name() << " ";
210 if (flags
[TRACE_MISSPEC
])
211 outs
<< (misspeculating
? "-" : "+") << " ";
213 if (flags
[PRINT_THREAD_NUM
])
214 outs
<< "T" << thread
->getThreadNum() << " : ";
220 && debugSymbolTable
->findNearestSymbol(PC
, sym_str
, sym_addr
)
221 && flags
[PC_SYMBOL
]) {
223 sym_str
+= csprintf("+%d", PC
- sym_addr
);
224 outs
<< "@" << sym_str
<< " : ";
227 outs
<< "0x" << hex
<< PC
<< " : ";
231 // Print decoded instruction
234 #if defined(__GNUC__) && (__GNUC__ < 3)
235 // There's a bug in gcc 2.x library that prevents setw()
236 // from working properly on strings
237 string
mc(staticInst
->disassemble(PC
, debugSymbolTable
));
238 while (mc
.length() < 26)
242 outs
<< setw(26) << left
<< staticInst
->disassemble(PC
, debugSymbolTable
);
247 if (flags
[PRINT_OP_CLASS
]) {
248 outs
<< opClassStrings
[staticInst
->opClass()] << " : ";
251 if (flags
[PRINT_RESULT_DATA
] && data_status
!= DataInvalid
) {
254 if (data_status
== DataDouble
)
255 ccprintf(outs
, "%f", data
.as_double
);
257 ccprintf(outs
, "%#018x", data
.as_int
);
259 ccprintf(outs
, "%#018x", data
.as_int
);
263 if (flags
[PRINT_EFF_ADDR
] && addr_valid
)
264 outs
<< " A=0x" << hex
<< addr
;
266 if (flags
[PRINT_INT_REGS
] && regs_valid
) {
267 for (int i
= 0; i
< TheISA::NumIntRegs
;)
268 for (int j
= i
+ 1; i
<= j
; i
++)
269 ccprintf(outs
, "r%02d = %#018x%s", i
,
270 iregs
->regs
.readReg(i
),
271 ((i
== j
) ? "\n" : " "));
275 if (flags
[PRINT_FETCH_SEQ
] && fetch_seq_valid
)
276 outs
<< " FetchSeq=" << dec
<< fetch_seq
;
278 if (flags
[PRINT_CP_SEQ
] && cp_seq_valid
)
279 outs
<< " CPSeq=" << dec
<< cp_seq
;
286 #if THE_ISA == SPARC_ISA && FULL_SYSTEM
288 if (flags
[LEGION_LOCKSTEP
])
290 bool compared
= false;
293 bool diffInst
= false;
294 bool diffRegs
= false;
295 bool diffTpc
= false;
296 bool diffTnpc
= false;
297 bool diffTstate
= false;
299 bool diffTba
= false;
300 bool diffHpstate
= false;
301 bool diffHtstate
= false;
302 bool diffHtba
= false;
303 bool diffPstate
= false;
305 bool diffCcr
= false;
308 bool diffAsi
= false;
309 bool diffPil
= false;
310 bool diffCwp
= false;
311 bool diffCansave
= false;
312 bool diffCanrestore
= false;
313 bool diffOtherwin
= false;
314 bool diffCleanwin
= false;
315 bool diffTlb
= false;
319 if(!staticInst
->isMicroOp() || staticInst
->isLastMicroOp()) {
321 if (shared_data
->flags
== OWN_M5
) {
322 m5Pc
= PC
& TheISA::PAddrImplMask
;
323 lgnPc
= shared_data
->pc
& TheISA::PAddrImplMask
;
327 if (shared_data
->cycle_count
!=
328 thread
->getCpuPtr()->instCount())
331 if (shared_data
->instruction
!=
332 (SparcISA::MachInst
)staticInst
->machInst
) {
335 for (int i
= 0; i
< TheISA::NumIntArchRegs
; i
++) {
336 if (thread
->readIntReg(i
) != shared_data
->intregs
[i
]) {
340 uint64_t oldTl
= thread
->readMiscReg(MISCREG_TL
);
341 if (oldTl
!= shared_data
->tl
)
343 for (int i
= 1; i
<= MaxTL
; i
++) {
344 thread
->setMiscReg(MISCREG_TL
, i
);
345 if (thread
->readMiscReg(MISCREG_TPC
) !=
346 shared_data
->tpc
[i
-1])
348 if (thread
->readMiscReg(MISCREG_TNPC
) !=
349 shared_data
->tnpc
[i
-1])
351 if (thread
->readMiscReg(MISCREG_TSTATE
) !=
352 shared_data
->tstate
[i
-1])
354 if (thread
->readMiscReg(MISCREG_TT
) !=
355 shared_data
->tt
[i
-1])
357 if (thread
->readMiscReg(MISCREG_HTSTATE
) !=
358 shared_data
->htstate
[i
-1])
361 thread
->setMiscReg(MISCREG_TL
, oldTl
);
363 if(shared_data
->tba
!= thread
->readMiscReg(MISCREG_TBA
))
365 //When the hpstate register is read by an instruction,
366 //legion has bit 11 set. When it's in storage, it doesn't.
367 //Since we don't directly support seperate interpretations
368 //of the registers like that, the bit is always set to 1 and
369 //we just don't compare it. It's not supposed to matter
371 if((shared_data
->hpstate
| (1 << 11)) != thread
->readMiscReg(MISCREG_HPSTATE
))
373 if(shared_data
->htba
!= thread
->readMiscReg(MISCREG_HTBA
))
375 if(shared_data
->pstate
!= thread
->readMiscReg(MISCREG_PSTATE
))
377 if(shared_data
->y
!= thread
->readMiscReg(MISCREG_Y
))
379 if(shared_data
->ccr
!= thread
->readMiscReg(MISCREG_CCR
))
381 if(shared_data
->gl
!= thread
->readMiscReg(MISCREG_GL
))
383 if(shared_data
->asi
!= thread
->readMiscReg(MISCREG_ASI
))
385 if(shared_data
->pil
!= thread
->readMiscReg(MISCREG_PIL
))
387 if(shared_data
->cwp
!= thread
->readMiscReg(MISCREG_CWP
))
389 if(shared_data
->cansave
!= thread
->readMiscReg(MISCREG_CANSAVE
))
391 if(shared_data
->canrestore
!=
392 thread
->readMiscReg(MISCREG_CANRESTORE
))
393 diffCanrestore
= true;
394 if(shared_data
->otherwin
!= thread
->readMiscReg(MISCREG_OTHERWIN
))
396 if(shared_data
->cleanwin
!= thread
->readMiscReg(MISCREG_CLEANWIN
))
399 for (int i
= 0; i
< 64; i
++) {
400 if (shared_data
->itb
[i
] != thread
->getITBPtr()->TteRead(i
))
402 if (shared_data
->dtb
[i
] != thread
->getDTBPtr()->TteRead(i
))
406 if ((diffPC
|| diffCC
|| diffInst
|| diffRegs
|| diffTpc
||
407 diffTnpc
|| diffTstate
|| diffTt
|| diffHpstate
||
408 diffHtstate
|| diffHtba
|| diffPstate
|| diffY
||
409 diffCcr
|| diffTl
|| diffGl
|| diffAsi
|| diffPil
||
410 diffCwp
|| diffCansave
|| diffCanrestore
||
411 diffOtherwin
|| diffCleanwin
|| diffTlb
)
412 && !((staticInst
->machInst
& 0xC1F80000) == 0x81D00000)
413 && !(((staticInst
->machInst
& 0xC0000000) == 0xC0000000)
414 && shared_data
->tl
== thread
->readMiscReg(MISCREG_TL
) + 1)
417 outs
<< "Differences found between M5 and Legion:";
423 outs
<< " [Instruction]";
425 outs
<< " [IntRegs]";
435 outs
<< " [Hpstate]";
437 outs
<< " [Htstate]";
457 outs
<< " [Cansave]";
459 outs
<< " [Canrestore]";
461 outs
<< " [Otherwin]";
463 outs
<< " [Cleanwin]";
466 outs
<< endl
<< endl
;
468 outs
<< right
<< setfill(' ') << setw(15)
469 << "M5 PC: " << "0x"<< setw(16) << setfill('0')
470 << hex
<< m5Pc
<< endl
;
471 outs
<< setfill(' ') << setw(15)
472 << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
473 << lgnPc
<< endl
<< endl
;
475 outs
<< right
<< setfill(' ') << setw(15)
476 << "M5 CC: " << "0x"<< setw(16) << setfill('0')
477 << hex
<< thread
->getCpuPtr()->instCount() << endl
;
478 outs
<< setfill(' ') << setw(15)
479 << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex
480 << shared_data
->cycle_count
<< endl
<< endl
;
482 outs
<< setfill(' ') << setw(15)
483 << "M5 Inst: " << "0x"<< setw(8)
484 << setfill('0') << hex
<< staticInst
->machInst
485 << staticInst
->disassemble(m5Pc
, debugSymbolTable
)
488 StaticInstPtr legionInst
=
489 StaticInst::decode(makeExtMI(shared_data
->instruction
,
491 outs
<< setfill(' ') << setw(15)
493 << "0x" << setw(8) << setfill('0') << hex
494 << shared_data
->instruction
495 << legionInst
->disassemble(lgnPc
, debugSymbolTable
)
498 printSectionHeader(outs
, "General State");
499 printColumnLabels(outs
);
500 printRegPair(outs
, "HPstate",
501 thread
->readMiscReg(MISCREG_HPSTATE
),
502 shared_data
->hpstate
| (1 << 11));
503 printRegPair(outs
, "Htba",
504 thread
->readMiscReg(MISCREG_HTBA
),
506 printRegPair(outs
, "Pstate",
507 thread
->readMiscReg(MISCREG_PSTATE
),
508 shared_data
->pstate
);
509 printRegPair(outs
, "Y",
510 thread
->readMiscReg(MISCREG_Y
),
512 printRegPair(outs
, "Ccr",
513 thread
->readMiscReg(MISCREG_CCR
),
515 printRegPair(outs
, "Tl",
516 thread
->readMiscReg(MISCREG_TL
),
518 printRegPair(outs
, "Gl",
519 thread
->readMiscReg(MISCREG_GL
),
521 printRegPair(outs
, "Asi",
522 thread
->readMiscReg(MISCREG_ASI
),
524 printRegPair(outs
, "Pil",
525 thread
->readMiscReg(MISCREG_PIL
),
527 printRegPair(outs
, "Cwp",
528 thread
->readMiscReg(MISCREG_CWP
),
530 printRegPair(outs
, "Cansave",
531 thread
->readMiscReg(MISCREG_CANSAVE
),
532 shared_data
->cansave
);
533 printRegPair(outs
, "Canrestore",
534 thread
->readMiscReg(MISCREG_CANRESTORE
),
535 shared_data
->canrestore
);
536 printRegPair(outs
, "Otherwin",
537 thread
->readMiscReg(MISCREG_OTHERWIN
),
538 shared_data
->otherwin
);
539 printRegPair(outs
, "Cleanwin",
540 thread
->readMiscReg(MISCREG_CLEANWIN
),
541 shared_data
->cleanwin
);
543 for (int i
= 1; i
<= MaxTL
; i
++) {
544 printLevelHeader(outs
, i
);
545 printColumnLabels(outs
);
546 thread
->setMiscReg(MISCREG_TL
, i
);
547 printRegPair(outs
, "Tpc",
548 thread
->readMiscReg(MISCREG_TPC
),
549 shared_data
->tpc
[i
-1]);
550 printRegPair(outs
, "Tnpc",
551 thread
->readMiscReg(MISCREG_TNPC
),
552 shared_data
->tnpc
[i
-1]);
553 printRegPair(outs
, "Tstate",
554 thread
->readMiscReg(MISCREG_TSTATE
),
555 shared_data
->tstate
[i
-1]);
556 printRegPair(outs
, "Tt",
557 thread
->readMiscReg(MISCREG_TT
),
558 shared_data
->tt
[i
-1]);
559 printRegPair(outs
, "Htstate",
560 thread
->readMiscReg(MISCREG_HTSTATE
),
561 shared_data
->htstate
[i
-1]);
563 thread
->setMiscReg(MISCREG_TL
, oldTl
);
566 printSectionHeader(outs
, "General Purpose Registers");
567 static const char * regtypes
[4] = {"%g", "%o", "%l", "%i"};
568 for(int y
= 0; y
< 4; y
++)
570 for(int x
= 0; x
< 8; x
++)
573 sprintf(label
, "%s%d", regtypes
[y
], x
);
574 printRegPair(outs
, label
,
575 thread
->readIntReg(y
*8+x
),
576 shared_data
->intregs
[y
*8+x
]);
577 /*outs << regtypes[y] << x << " " ;
578 outs << "0x" << hex << setw(16)
579 << thread->readIntReg(y*8+x);
580 if (thread->readIntReg(y*8 + x)
581 != shared_data->intregs[y*8+x])
585 outs << "0x" << setw(16) << hex
586 << shared_data->intregs[y*8+x]
590 printColumnLabels(outs
);
592 for (int x
= 0; x
< 64; x
++) {
593 if (shared_data
->itb
[x
] != ULL(0xFFFFFFFFFFFFFFFF) ||
594 thread
->getITBPtr()->TteRead(x
) != ULL(0xFFFFFFFFFFFFFFFF)) {
595 sprintf(label
, "I-TLB:%02d", x
);
596 printRegPair(outs
, label
, thread
->getITBPtr()->TteRead(x
), shared_data
->itb
[x
]);
599 for (int x
= 0; x
< 64; x
++) {
600 if (shared_data
->dtb
[x
] != ULL(0xFFFFFFFFFFFFFFFF) ||
601 thread
->getDTBPtr()->TteRead(x
) != ULL(0xFFFFFFFFFFFFFFFF)) {
602 sprintf(label
, "D-TLB:%02d", x
);
603 printRegPair(outs
, label
, thread
->getDTBPtr()->TteRead(x
), shared_data
->dtb
[x
]);
606 thread
->getITBPtr()->dumpAll();
607 thread
->getDTBPtr()->dumpAll();
611 fatal("Differences found between Legion and M5\n");
615 shared_data
->flags
= OWN_LEGION
;
624 vector
<bool> Trace::InstRecord::flags(NUM_BITS
);
625 string
Trace::InstRecord::trace_system
;
627 ////////////////////////////////////////////////////////////////////////
629 // Parameter space for per-cycle execution address tracing options.
630 // Derive from ParamContext so we can override checkParams() function.
632 class ExecutionTraceParamContext
: public ParamContext
635 ExecutionTraceParamContext(const string
&_iniSection
)
636 : ParamContext(_iniSection
)
640 void checkParams(); // defined at bottom of file
643 ExecutionTraceParamContext
exeTraceParams("exetrace");
645 Param
<bool> exe_trace_spec(&exeTraceParams
, "speculative",
646 "capture speculative instructions", true);
648 Param
<bool> exe_trace_print_cycle(&exeTraceParams
, "print_cycle",
649 "print cycle number", true);
650 Param
<bool> exe_trace_print_opclass(&exeTraceParams
, "print_opclass",
651 "print op class", true);
652 Param
<bool> exe_trace_print_thread(&exeTraceParams
, "print_thread",
653 "print thread number", true);
654 Param
<bool> exe_trace_print_effaddr(&exeTraceParams
, "print_effaddr",
655 "print effective address", true);
656 Param
<bool> exe_trace_print_data(&exeTraceParams
, "print_data",
657 "print result data", true);
658 Param
<bool> exe_trace_print_iregs(&exeTraceParams
, "print_iregs",
659 "print all integer regs", false);
660 Param
<bool> exe_trace_print_fetchseq(&exeTraceParams
, "print_fetchseq",
661 "print fetch sequence number", false);
662 Param
<bool> exe_trace_print_cp_seq(&exeTraceParams
, "print_cpseq",
663 "print correct-path sequence number", false);
664 Param
<bool> exe_trace_print_reg_delta(&exeTraceParams
, "print_reg_delta",
665 "print which registers changed to what", false);
666 Param
<bool> exe_trace_pc_symbol(&exeTraceParams
, "pc_symbol",
667 "Use symbols for the PC if available", true);
668 Param
<bool> exe_trace_intel_format(&exeTraceParams
, "intel_format",
669 "print trace in intel compatible format", false);
670 Param
<bool> exe_trace_legion_lockstep(&exeTraceParams
, "legion_lockstep",
671 "Compare sim state to legion state every cycle",
673 Param
<string
> exe_trace_system(&exeTraceParams
, "trace_system",
674 "print trace of which system (client or server)",
679 // Helper function for ExecutionTraceParamContext::checkParams() just
680 // to get us into the InstRecord namespace
683 Trace::InstRecord::setParams()
685 flags
[TRACE_MISSPEC
] = exe_trace_spec
;
687 flags
[PRINT_CYCLE
] = exe_trace_print_cycle
;
688 flags
[PRINT_OP_CLASS
] = exe_trace_print_opclass
;
689 flags
[PRINT_THREAD_NUM
] = exe_trace_print_thread
;
690 flags
[PRINT_RESULT_DATA
] = exe_trace_print_effaddr
;
691 flags
[PRINT_EFF_ADDR
] = exe_trace_print_data
;
692 flags
[PRINT_INT_REGS
] = exe_trace_print_iregs
;
693 flags
[PRINT_FETCH_SEQ
] = exe_trace_print_fetchseq
;
694 flags
[PRINT_CP_SEQ
] = exe_trace_print_cp_seq
;
695 flags
[PRINT_REG_DELTA
] = exe_trace_print_reg_delta
;
696 flags
[PC_SYMBOL
] = exe_trace_pc_symbol
;
697 flags
[INTEL_FORMAT
] = exe_trace_intel_format
;
698 flags
[LEGION_LOCKSTEP
] = exe_trace_legion_lockstep
;
699 trace_system
= exe_trace_system
;
701 // If were going to be in lockstep with Legion
702 // Setup shared memory, and get otherwise ready
703 if (flags
[LEGION_LOCKSTEP
]) {
704 int shmfd
= shmget('M' << 24 | getuid(), sizeof(SharedData
), 0777);
706 fatal("Couldn't get shared memory fd. Is Legion running?");
708 shared_data
= (SharedData
*)shmat(shmfd
, NULL
, SHM_RND
);
709 if (shared_data
== (SharedData
*)-1)
710 fatal("Couldn't allocate shared memory");
712 if (shared_data
->flags
!= OWN_M5
)
713 fatal("Shared memory has invalid owner");
715 if (shared_data
->version
!= VERSION
)
716 fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION
,
717 shared_data
->version
);
719 // step legion forward one cycle so we can get register values
720 shared_data
->flags
= OWN_LEGION
;
725 ExecutionTraceParamContext::checkParams()
727 Trace::InstRecord::setParams();