2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #ifndef __EXETRACE_HH__
33 #define __EXETRACE_HH__
38 #include "sim/host.hh"
39 #include "cpu/inst_seq.hh" // for InstSeqNum
40 #include "base/trace.hh"
41 #include "cpu/thread_context.hh"
42 #include "cpu/static_inst.hh"
49 class InstRecord : public Record
52 typedef TheISA::IntRegFile IntRegFile;
54 // The following fields are initialized by the constructor and
55 // thus guaranteed to be valid.
57 // need to make this ref-counted so it doesn't go away before we
59 StaticInstPtr staticInst;
64 // The remaining fields are only valid for particular instruction
65 // types (e.g, addresses for memory ops) or when particular
66 // options are enabled (e.g., tracing full register contents).
67 // Each data field has an associated valid flag to indicate
68 // whether the data field is valid.
78 DataInt8 = 1, // set to equal number of bytes
98 InstRecord(Tick _cycle, BaseCPU *_cpu,
99 const StaticInstPtr &_staticInst,
100 Addr _pc, bool spec, int _thread)
101 : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
102 misspeculating(spec), thread(_thread)
104 data_status = DataInvalid;
108 fetch_seq_valid = false;
109 cp_seq_valid = false;
112 virtual ~InstRecord() { }
114 virtual void dump(std::ostream &outs);
116 void setAddr(Addr a) { addr = a; addr_valid = true; }
118 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
119 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
120 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
121 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
123 void setData(int64_t d) { setData((uint64_t)d); }
124 void setData(int32_t d) { setData((uint32_t)d); }
125 void setData(int16_t d) { setData((uint16_t)d); }
126 void setData(int8_t d) { setData((uint8_t)d); }
128 void setData(double d) { data.as_double = d; data_status = DataDouble; }
130 void setFetchSeq(InstSeqNum seq)
131 { fetch_seq = seq; fetch_seq_valid = true; }
133 void setCPSeq(InstSeqNum seq)
134 { cp_seq = seq; cp_seq_valid = true; }
136 void setRegs(const IntRegFile ®s);
138 void finalize() { theLog.append(this); }
140 enum InstExecFlagBits {
155 static std::vector<bool> flags;
156 static std::string trace_system;
158 static void setParams();
160 static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
165 InstRecord::setRegs(const IntRegFile ®s)
168 iregs = new iRegFile;
170 memcpy(&iregs->regs, ®s, sizeof(IntRegFile));
176 getInstRecord(Tick cycle, ThreadContext *tc, BaseCPU *cpu,
177 const StaticInstPtr staticInst,
178 Addr pc, int thread = 0)
180 if (DTRACE(InstExec) &&
181 (InstRecord::traceMisspec() || !tc->misspeculating())) {
182 return new InstRecord(cycle, cpu, staticInst, pc,
183 tc->misspeculating(), thread);
192 #endif // __EXETRACE_HH__