src/cpu/func_unit.cc

   1 /*
   2  * Copyright (c) 2002-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Raasch
  29  */
  30
  31 #include <sstream>
  32
  33 #include "base/misc.hh"
  34 #include "cpu/func_unit.hh"
  35 #include "sim/builder.hh"
  36
  37 using namespace std;
  38
  39
  40 ////////////////////////////////////////////////////////////////////////////
  41 //
  42 //  The funciton unit
  43 //
  44 FuncUnit::FuncUnit()
  45 {
  46     capabilityList.reset();
  47 }
  48
  49
  50 //  Copy constructor
  51 FuncUnit::FuncUnit(const FuncUnit &fu)
  52 {
  53
  54     for (int i = 0; i < Num_OpClasses; ++i) {
  55         opLatencies[i] = fu.opLatencies[i];
  56         issueLatencies[i] = fu.issueLatencies[i];
  57     }
  58
  59     capabilityList = fu.capabilityList;
  60 }
  61
  62
  63 void
  64 FuncUnit::addCapability(OpClass cap, unsigned oplat, unsigned issuelat)
  65 {
  66     if (issuelat == 0 || oplat == 0)
  67         panic("FuncUnit:  you don't really want a zero-cycle latency do you?");
  68
  69     capabilityList.set(cap);
  70
  71     opLatencies[cap] = oplat;
  72     issueLatencies[cap] = issuelat;
  73 }
  74
  75 bool
  76 FuncUnit::provides(OpClass capability)
  77 {
  78     return capabilityList[capability];
  79 }
  80
  81 bitset<Num_OpClasses>
  82 FuncUnit::capabilities()
  83 {
  84     return capabilityList;
  85 }
  86
  87 unsigned &
  88 FuncUnit::opLatency(OpClass cap)
  89 {
  90     return opLatencies[cap];
  91 }
  92
  93 unsigned
  94 FuncUnit::issueLatency(OpClass capability)
  95 {
  96     return issueLatencies[capability];
  97 }
  98
  99 ////////////////////////////////////////////////////////////////////////////
 100 //
 101 //  The SimObjects we use to get the FU information into the simulator
 102 //
 103 ////////////////////////////////////////////////////////////////////////////
 104
 105 //
 106 //  We use 2 objects to specify this data in the INI file:
 107 //    (1) OpDesc - Describes the operation class & latencies
 108 //                   (multiple OpDesc objects can refer to the same
 109 //                   operation classes)
 110 //    (2) FUDesc - Describes the operations available in the unit &
 111 //                   the number of these units
 112 //
 113 //
 114
 115
 116 //
 117 //  The operation-class description object
 118 //
 119
 120 BEGIN_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
 121
 122     SimpleEnumParam<OpClass> opClass;
 123     Param<unsigned>    opLat;
 124     Param<unsigned>    issueLat;
 125
 126 END_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
 127
 128 BEGIN_INIT_SIM_OBJECT_PARAMS(OpDesc)
 129
 130     INIT_ENUM_PARAM(opClass, "type of operation", opClassStrings),
 131     INIT_PARAM(opLat,        "cycles until result is available"),
 132     INIT_PARAM(issueLat,     "cycles until another can be issued")
 133
 134 END_INIT_SIM_OBJECT_PARAMS(OpDesc)
 135
 136
 137 CREATE_SIM_OBJECT(OpDesc)
 138 {
 139     return new OpDesc(getInstanceName(), opClass, opLat, issueLat);
 140 }
 141
 142 REGISTER_SIM_OBJECT("OpDesc", OpDesc)
 143
 144
 145 //
 146 //  The FuDesc object
 147 //
 148
 149 BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
 150
 151     SimObjectVectorParam<OpDesc *> opList;
 152     Param<unsigned>                count;
 153
 154 END_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
 155
 156
 157 BEGIN_INIT_SIM_OBJECT_PARAMS(FUDesc)
 158
 159     INIT_PARAM(opList, "list of operation classes for this FU type"),
 160     INIT_PARAM(count,  "number of these FU's available")
 161
 162 END_INIT_SIM_OBJECT_PARAMS(FUDesc)
 163
 164
 165 CREATE_SIM_OBJECT(FUDesc)
 166 {
 167     return new FUDesc(getInstanceName(), opList, count);
 168 }
 169
 170 REGISTER_SIM_OBJECT("FUDesc", FUDesc)
 171