1 # Copyright (c) 2007 MIPS Technologies, Inc.
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Korey Sewell
29 from m5
.params
import *
30 from m5
.proxy
import *
31 from BaseCPU
import BaseCPU
33 class ThreadModel(Enum
):
34 vals
= ['Single', 'SMT', 'SwitchOnCacheMiss']
36 class InOrderCPU(BaseCPU
):
38 activity
= Param
.Unsigned(0, "Initial count")
40 threadModel
= Param
.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
42 cachePorts
= Param
.Unsigned(2, "Cache Ports")
43 stageWidth
= Param
.Unsigned(4, "Stage width")
45 fetchBuffSize
= Param
.Unsigned(4, "Fetch Buffer Size (Number of Cache Blocks Stored)")
46 memBlockSize
= Param
.Unsigned(64, "Memory Block Size")
48 predType
= Param
.String("tournament", "Branch predictor type ('local', 'tournament')")
49 localPredictorSize
= Param
.Unsigned(2048, "Size of local predictor")
50 localCtrBits
= Param
.Unsigned(2, "Bits per counter")
51 localHistoryTableSize
= Param
.Unsigned(2048, "Size of local history table")
52 localHistoryBits
= Param
.Unsigned(11, "Bits for the local history")
53 globalPredictorSize
= Param
.Unsigned(8192, "Size of global predictor")
54 globalCtrBits
= Param
.Unsigned(2, "Bits per counter")
55 globalHistoryBits
= Param
.Unsigned(13, "Bits of history")
56 choicePredictorSize
= Param
.Unsigned(8192, "Size of choice predictor")
57 choiceCtrBits
= Param
.Unsigned(2, "Bits of choice counters")
59 BTBEntries
= Param
.Unsigned(4096, "Number of BTB entries")
60 BTBTagSize
= Param
.Unsigned(16, "Size of the BTB tags, in bits")
62 RASSize
= Param
.Unsigned(16, "RAS size")
64 instShiftAmt
= Param
.Unsigned(2, "Number of bits to shift instructions by")
65 functionTrace
= Param
.Bool(False, "Enable function trace")
66 functionTraceStart
= Param
.Tick(0, "Cycle to start function trace")
67 stageTracing
= Param
.Bool(False, "Enable tracing of each stage in CPU")
69 multLatency
= Param
.Unsigned(1, "Latency for Multiply Operations")
70 multRepeatRate
= Param
.Unsigned(1, "Repeat Rate for Multiply Operations")
71 div8Latency
= Param
.Unsigned(1, "Latency for 8-bit Divide Operations")
72 div8RepeatRate
= Param
.Unsigned(1, "Repeat Rate for 8-bit Divide Operations")
73 div16Latency
= Param
.Unsigned(1, "Latency for 16-bit Divide Operations")
74 div16RepeatRate
= Param
.Unsigned(1, "Repeat Rate for 16-bit Divide Operations")
75 div24Latency
= Param
.Unsigned(1, "Latency for 24-bit Divide Operations")
76 div24RepeatRate
= Param
.Unsigned(1, "Repeat Rate for 24-bit Divide Operations")
77 div32Latency
= Param
.Unsigned(1, "Latency for 32-bit Divide Operations")
78 div32RepeatRate
= Param
.Unsigned(1, "Repeat Rate for 32-bit Divide Operations")