src/cpu/inorder/InOrderCPU.py

   1 # Copyright (c) 2007 MIPS Technologies, Inc.
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Korey Sewell
  28
  29 from m5.params import *
  30 from m5.proxy import *
  31 from m5 import build_env
  32 from BaseCPU import BaseCPU
  33
  34 class InOrderCPU(BaseCPU):
  35     type = 'InOrderCPU'
  36     activity = Param.Unsigned(0, "Initial count")
  37
  38     cachePorts = Param.Unsigned(2, "Cache Ports")
  39     stageWidth = Param.Unsigned(1, "Stage width")
  40
  41     fetchMemPort = Param.String("icache_port" , "Name of Memory Port to get instructions from")
  42     dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from")
  43     icache_port = Port("Instruction Port")
  44     dcache_port = Port("Data Port")
  45     _mem_ports = ['icache_port', 'dcache_port']
  46
  47     predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
  48     localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
  49     localCtrBits = Param.Unsigned(2, "Bits per counter")
  50     localHistoryTableSize = Param.Unsigned(2048, "Size of local history table")
  51     localHistoryBits = Param.Unsigned(11, "Bits for the local history")
  52     globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
  53     globalCtrBits = Param.Unsigned(2, "Bits per counter")
  54     globalHistoryBits = Param.Unsigned(13, "Bits of history")
  55     choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
  56     choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
  57
  58     BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
  59     BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
  60
  61     RASSize = Param.Unsigned(16, "RAS size")
  62
  63     instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
  64     functionTrace = Param.Bool(False, "Enable function trace")
  65     functionTraceStart = Param.Tick(0, "Cycle to start function trace")
  66     stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU")
  67
  68     memBlockSize = Param.Unsigned(64, "Memory Block Size")
  69
  70     multLatency = Param.Unsigned(1, "Latency for Multiply Operations")
  71     multRepeatRate = Param.Unsigned(1, "Repeat Rate for Multiply Operations")
  72     div8Latency = Param.Unsigned(1, "Latency for 8-bit Divide Operations")
  73     div8RepeatRate = Param.Unsigned(1, "Repeat Rate for 8-bit Divide Operations")
  74     div16Latency = Param.Unsigned(1, "Latency for 16-bit Divide Operations")
  75     div16RepeatRate = Param.Unsigned(1, "Repeat Rate for 16-bit Divide Operations")
  76     div24Latency = Param.Unsigned(1, "Latency for 24-bit Divide Operations")
  77     div24RepeatRate = Param.Unsigned(1, "Repeat Rate for 24-bit Divide Operations")
  78     div32Latency = Param.Unsigned(1, "Latency for 32-bit Divide Operations")
  79     div32RepeatRate = Param.Unsigned(1, "Repeat Rate for 32-bit Divide Operations")