src/cpu/inorder/InOrderCPU.py

   1 # Copyright (c) 2007 MIPS Technologies, Inc.
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Korey Sewell
  28
  29 from m5.params import *
  30 from m5.proxy import *
  31 from BaseCPU import BaseCPU
  32 from BranchPredictor import BranchPredictor
  33
  34 class ThreadModel(Enum):
  35     vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
  36
  37 class InOrderCPU(BaseCPU):
  38     type = 'InOrderCPU'
  39     cxx_header = "cpu/inorder/cpu.hh"
  40     activity = Param.Unsigned(0, "Initial count")
  41
  42     @classmethod
  43     def memory_mode(cls):
  44         return 'timing'
  45
  46     @classmethod
  47     def require_caches(cls):
  48         return True
  49
  50     threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
  51
  52     cachePorts = Param.Unsigned(2, "Cache Ports")
  53     stageWidth = Param.Unsigned(4, "Stage width")
  54
  55     fetchBuffSize = Param.Unsigned(4, "Fetch Buffer Size (Number of Cache Blocks Stored)")
  56     memBlockSize = Param.Unsigned(64, "Memory Block Size")
  57
  58     stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU")
  59
  60     multLatency = Param.Cycles(1, "Latency for Multiply Operations")
  61     multRepeatRate = Param.Cycles(1, "Repeat Rate for Multiply Operations")
  62     div8Latency = Param.Cycles(1, "Latency for 8-bit Divide Operations")
  63     div8RepeatRate = Param.Cycles(1, "Repeat Rate for 8-bit Divide Operations")
  64     div16Latency = Param.Cycles(1, "Latency for 16-bit Divide Operations")
  65     div16RepeatRate = Param.Cycles(1, "Repeat Rate for 16-bit Divide Operations")
  66     div24Latency = Param.Cycles(1, "Latency for 24-bit Divide Operations")
  67     div24RepeatRate = Param.Cycles(1, "Repeat Rate for 24-bit Divide Operations")
  68     div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations")
  69     div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations")
  70
  71     branchPred = BranchPredictor(numThreads = Parent.numThreads)