src/cpu/inorder/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2007 MIPS Technologies, Inc.
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 #
  29 # Authors: Korey Sewell
  30
  31 Import('*')
  32
  33 if 'InOrderCPU' in env['CPU_MODELS']:
  34         SimObject('InOrderCPU.py')
  35         SimObject('InOrderTrace.py')
  36
  37         TraceFlag('ResReqCount')
  38         TraceFlag('FreeList')
  39         TraceFlag('InOrderCachePort')
  40         TraceFlag('InOrderStage')
  41         TraceFlag('InOrderStall')
  42         TraceFlag('InOrderCPU')
  43         TraceFlag('InOrderMDU')
  44         TraceFlag('RegDepMap')
  45         TraceFlag('InOrderDynInst')
  46         TraceFlag('Resource')
  47         TraceFlag('RefCount')
  48
  49         CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
  50                'InOrderMDU', 'RegDepMap', 'Resource'])
  51
  52         Source('pipeline_traits.cc')
  53         Source('inorder_dyn_inst.cc')
  54         Source('inorder_cpu_builder.cc')
  55         Source('inorder_trace.cc')
  56         Source('pipeline_stage.cc')
  57         Source('first_stage.cc')
  58         Source('resource.cc')
  59         Source('resources/agen_unit.cc')
  60         Source('resources/execution_unit.cc')
  61         Source('resources/bpred_unit.cc')
  62         Source('resources/branch_predictor.cc')
  63         Source('resources/cache_unit.cc')
  64         Source('resources/use_def.cc')
  65         Source('resources/decode_unit.cc')
  66         Source('resources/inst_buffer.cc')
  67         Source('resources/graduation_unit.cc')
  68         Source('resources/tlb_unit.cc')
  69         Source('resources/fetch_seq_unit.cc')
  70         Source('resources/mult_div_unit.cc')
  71         Source('resource_pool.cc')
  72         Source('reg_dep_map.cc')
  73         Source('../o3/btb.cc')
  74         Source('../o3/tournament_pred.cc')
  75         Source('../o3/2bit_local_pred.cc')
  76         Source('../o3/ras.cc')
  77         Source('thread_context.cc')
  78         Source('cpu.cc')
  79