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[gem5.git] / src / cpu / inorder / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2007 MIPS Technologies, Inc.
4 # All rights reserved.
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
16 #
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #
29 # Authors: Korey Sewell
30
31 Import('*')
32
33 if 'InOrderCPU' in env['CPU_MODELS']:
34 SimObject('InOrderCPU.py')
35 SimObject('InOrderTrace.py')
36
37 TraceFlag('ResReqCount')
38 TraceFlag('InOrderStage')
39 TraceFlag('InOrderStall')
40 TraceFlag('InOrderCPU')
41 TraceFlag('RegDepMap')
42 TraceFlag('InOrderDynInst')
43 TraceFlag('Resource')
44 TraceFlag('InOrderAGEN')
45 TraceFlag('InOrderFetchSeq')
46 TraceFlag('InOrderTLB')
47 TraceFlag('InOrderCachePort')
48 TraceFlag('InOrderBPred')
49 TraceFlag('InOrderDecode')
50 TraceFlag('InOrderExecute')
51 TraceFlag('InOrderInstBuffer')
52 TraceFlag('InOrderUseDef')
53 TraceFlag('InOrderMDU')
54 TraceFlag('InOrderGraduation')
55 TraceFlag('ThreadModel')
56 TraceFlag('RefCount')
57 TraceFlag('AddrDep')
58
59
60 CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
61 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred',
62 'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef',
63 'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource',
64 'ThreadModel'])
65
66 Source('pipeline_traits.cc')
67 Source('inorder_dyn_inst.cc')
68 Source('inorder_cpu_builder.cc')
69 Source('inorder_trace.cc')
70 Source('pipeline_stage.cc')
71 Source('first_stage.cc')
72 Source('resource.cc')
73 Source('resources/agen_unit.cc')
74 Source('resources/execution_unit.cc')
75 Source('resources/bpred_unit.cc')
76 Source('resources/branch_predictor.cc')
77 Source('resources/cache_unit.cc')
78 Source('resources/use_def.cc')
79 Source('resources/decode_unit.cc')
80 Source('resources/inst_buffer.cc')
81 Source('resources/graduation_unit.cc')
82 Source('resources/fetch_seq_unit.cc')
83 Source('resources/mult_div_unit.cc')
84 Source('resource_pool.cc')
85 Source('reg_dep_map.cc')
86 Source('thread_state.cc')
87 Source('thread_context.cc')
88 Source('cpu.cc')
89