src/cpu/inorder/comm.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_COMM_HH__
  33 #define __CPU_INORDER_COMM_HH__
  34
  35 #include <vector>
  36
  37 #include "arch/isa_traits.hh"
  38 #include "base/types.hh"
  39 #include "cpu/inorder/inorder_dyn_inst.hh"
  40 #include "cpu/inorder/pipeline_traits.hh"
  41 #include "cpu/inst_seq.hh"
  42
  43 /** Struct that defines the information passed from in between stages */
  44 /** This information mainly goes forward through the pipeline. */
  45 struct InterStageStruct {
  46     //@todo: probably should make this a list since the amount of
  47     //       instructions that get passed forward per cycle is
  48     //       really dependent on issue width, CPI, etc.
  49     std::vector<ThePipeline::DynInstPtr> insts;
  50
  51     // Add any information that needs to be passed forward to stages
  52     // below ...
  53 };
  54
  55 /** Struct that defines all backwards communication. */
  56 struct TimeStruct {
  57     struct StageComm {
  58         bool squash;
  59         InstSeqNum doneSeqNum;
  60
  61         bool uncached;
  62         ThePipeline::DynInstPtr uncachedLoad;
  63
  64         StageComm()
  65             : squash(false), doneSeqNum(0), uncached(false), uncachedLoad(NULL)
  66         { }
  67     };
  68
  69     StageComm stageInfo[ThePipeline::NumStages][ThePipeline::MaxThreads];
  70     bool stageBlock[ThePipeline::NumStages][ThePipeline::MaxThreads];
  71     bool stageUnblock[ThePipeline::NumStages][ThePipeline::MaxThreads];
  72
  73     TimeStruct()
  74     {
  75         for (int i = 0; i < ThePipeline::NumStages; i++) {
  76             for (int j = 0; j < ThePipeline::MaxThreads; j++) {
  77                 stageBlock[i][j] = false;
  78                 stageUnblock[i][j] = false;
  79             }
  80         }
  81     }
  82
  83 };
  84
  85 #endif //__CPU_INORDER_COMM_HH__