src/cpu/inorder/comm.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_COMM_HH__
  33 #define __CPU_INORDER_COMM_HH__
  34
  35 #include <vector>
  36
  37 #include "arch/faults.hh"
  38 #include "arch/isa_traits.hh"
  39 #include "base/types.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/pipeline_traits.hh"
  42 #include "cpu/inst_seq.hh"
  43
  44 /** Struct that defines the information passed from in between stages */
  45 /** This information mainly goes forward through the pipeline. */
  46 struct InterStageStruct {
  47     int size;
  48     ThePipeline::DynInstPtr insts[ThePipeline::StageWidth];
  49     bool squash;
  50     bool branchMispredict;
  51     bool branchTaken;
  52     uint64_t mispredPC;
  53     uint64_t nextPC;
  54     InstSeqNum squashedSeqNum;
  55     bool includeSquashInst;
  56
  57     InterStageStruct()
  58         :size(0),  squash(false),
  59          branchMispredict(false), branchTaken(false),
  60          mispredPC(0), nextPC(0),
  61          squashedSeqNum(0), includeSquashInst(false)
  62     { }
  63
  64 };
  65
  66 /** Turn This into a Class */
  67 /** Struct that defines all backwards communication. */
  68 struct TimeStruct {
  69     struct stageComm {
  70         bool squash;
  71         bool predIncorrect;
  72         uint64_t branchAddr;
  73
  74         // @todo: Might want to package this kind of branch stuff into a single
  75         // struct as it is used pretty frequently.
  76         bool branchMispredict;
  77         bool branchTaken;
  78         uint64_t mispredPC;
  79         uint64_t nextPC;
  80
  81         unsigned branchCount;
  82
  83         // Represents the instruction that has either been retired or
  84         // squashed.  Similar to having a single bus that broadcasts the
  85         // retired or squashed sequence number.
  86         InstSeqNum doneSeqNum;
  87         InstSeqNum bdelayDoneSeqNum;
  88         bool squashDelaySlot;
  89
  90         //Just in case we want to do a commit/squash on a cycle
  91         //(necessary for multiple ROBs?)
  92         bool commitInsts;
  93         InstSeqNum squashSeqNum;
  94
  95         // Communication specifically to the IQ to tell the IQ that it can
  96         // schedule a non-speculative instruction.
  97         InstSeqNum nonSpecSeqNum;
  98
  99         bool uncached;
 100         ThePipeline::DynInstPtr uncachedLoad;
 101
 102         bool interruptPending;
 103         bool clearInterrupt;
 104     };
 105
 106     stageComm stageInfo[ThePipeline::NumStages][ThePipeline::MaxThreads];
 107
 108     bool stageBlock[ThePipeline::NumStages][ThePipeline::MaxThreads];
 109     bool stageUnblock[ThePipeline::NumStages][ThePipeline::MaxThreads];
 110 };
 111
 112 #endif //__CPU_INORDER_COMM_HH__