2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "config/full_system.hh"
36 #include "config/the_isa.hh"
37 #include "cpu/activity.hh"
38 #include "cpu/base.hh"
39 #include "cpu/exetrace.hh"
40 #include "cpu/inorder/cpu.hh"
41 #include "cpu/inorder/first_stage.hh"
42 #include "cpu/inorder/inorder_dyn_inst.hh"
43 #include "cpu/inorder/pipeline_traits.hh"
44 #include "cpu/inorder/resource_pool.hh"
45 #include "cpu/inorder/resources/resource_list.hh"
46 #include "cpu/inorder/thread_context.hh"
47 #include "cpu/inorder/thread_state.hh"
48 #include "cpu/simple_thread.hh"
49 #include "cpu/thread_context.hh"
50 #include "mem/translating_port.hh"
51 #include "params/InOrderCPU.hh"
52 #include "sim/process.hh"
53 #include "sim/stat_control.hh"
56 #include "cpu/quiesce_event.hh"
57 #include "sim/system.hh"
60 #if THE_ISA == ALPHA_ISA
61 #include "arch/alpha/osfpal.hh"
65 using namespace TheISA
;
66 using namespace ThePipeline
;
68 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
69 : Event(CPU_Tick_Pri
), cpu(c
)
74 InOrderCPU::TickEvent::process()
81 InOrderCPU::TickEvent::description()
83 return "InOrderCPU tick event";
86 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
87 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
88 unsigned event_pri_offset
)
89 : Event(Event::Priority((unsigned int)CPU_Tick_Pri
+ event_pri_offset
)),
92 setEvent(e_type
, fault
, _tid
, inst
);
96 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
99 "ActivateNextReadyThread",
105 "SquashFromMemStall",
110 InOrderCPU::CPUEvent::process()
112 switch (cpuEventType
)
115 cpu
->activateThread(tid
);
118 case ActivateNextReadyThread
:
119 cpu
->activateNextReadyThread();
122 case DeactivateThread
:
123 cpu
->deactivateThread(tid
);
127 cpu
->haltThread(tid
);
131 cpu
->suspendThread(tid
);
134 case SquashFromMemStall
:
135 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
139 cpu
->trapCPU(fault
, tid
, inst
);
143 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
146 cpu
->cpuEventRemoveList
.push(this);
152 InOrderCPU::CPUEvent::description()
154 return "InOrderCPU event";
158 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
160 assert(!scheduled() || squashed());
161 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
165 InOrderCPU::CPUEvent::unscheduleEvent()
171 InOrderCPU::InOrderCPU(Params
*params
)
173 cpu_id(params
->cpu_id
),
177 stageWidth(params
->stageWidth
),
179 removeInstsThisCycle(false),
180 activityRec(params
->name
, NumStages
, 10, params
->activity
),
182 system(params
->system
),
183 physmem(system
->physmem
),
184 #endif // FULL_SYSTEM
190 deferRegistration(false/*params->deferRegistration*/),
191 stageTracing(params
->stageTracing
),
194 ThreadID active_threads
;
197 resPool
= new ResourcePool(this, params
);
199 // Resize for Multithreading CPUs
200 thread
.resize(numThreads
);
205 active_threads
= params
->workload
.size();
207 if (active_threads
> MaxThreads
) {
208 panic("Workload Size too large. Increase the 'MaxThreads'"
209 "in your InOrder implementation or "
210 "edit your workload size.");
214 if (active_threads
> 1) {
215 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
217 if (threadModel
== SMT
) {
218 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
219 } else if (threadModel
== SwitchOnCacheMiss
) {
220 DPRINTF(InOrderCPU
, "Setting Thread Model to "
221 "Switch On Cache Miss\n");
225 threadModel
= Single
;
232 // Bind the fetch & data ports from the resource pool.
233 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
234 if (fetchPortIdx
== 0) {
235 fatal("Unable to find port to fetch instructions from.\n");
238 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
239 if (dataPortIdx
== 0) {
240 fatal("Unable to find port for data.\n");
243 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
245 // SMT is not supported in FS mode yet.
246 assert(numThreads
== 1);
247 thread
[tid
] = new Thread(this, 0);
249 if (tid
< (ThreadID
)params
->workload
.size()) {
250 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
251 tid
, params
->workload
[tid
]->prog_fname
);
253 new Thread(this, tid
, params
->workload
[tid
]);
255 //Allocate Empty thread so M5 can use later
256 //when scheduling threads to CPU
257 Process
* dummy_proc
= params
->workload
[0];
258 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
261 // Eventually set this with parameters...
265 // Setup the TC that will serve as the interface to the threads/CPU.
266 InOrderThreadContext
*tc
= new InOrderThreadContext
;
268 tc
->thread
= thread
[tid
];
270 // Give the thread the TC.
271 thread
[tid
]->tc
= tc
;
272 thread
[tid
]->setFuncExeInst(0);
273 globalSeqNum
[tid
] = 1;
275 // Add the TC to the CPU's list of TC's.
276 this->threadContexts
.push_back(tc
);
279 // Initialize TimeBuffer Stage Queues
280 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
281 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
282 stageQueue
[stNum
]->id(stNum
);
286 // Set Up Pipeline Stages
287 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
289 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
291 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
293 pipelineStage
[stNum
]->setCPU(this);
294 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
295 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
297 // Take Care of 1st/Nth stages
299 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
300 if (stNum
< NumStages
- 1)
301 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
304 // Initialize thread specific variables
305 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
306 archRegDepMap
[tid
].setCPU(this);
308 nonSpecInstActive
[tid
] = false;
309 nonSpecSeqNum
[tid
] = 0;
311 squashSeqNum
[tid
] = MaxAddr
;
312 lastSquashCycle
[tid
] = 0;
314 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
315 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
318 isa
[tid
].expandForMultithreading(numThreads
, 1/*numVirtProcs*/);
320 // Define dummy instructions and resource requests to be used.
321 dummyInst
[tid
] = new InOrderDynInst(this,
327 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0),
335 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
336 dummyReqInst
->setSquashed();
337 dummyReqInst
->resetInstCount();
339 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
340 dummyBufferInst
->setSquashed();
341 dummyBufferInst
->resetInstCount();
343 endOfSkedIt
= skedCache
.end();
344 frontEndSked
= createFrontEndSked();
346 lastRunningCycle
= curTick();
348 // Reset CPU to reset state.
350 Fault resetFault
= new ResetFault();
351 resetFault
->invoke(tcBase());
357 // Schedule First Tick Event, CPU will reschedule itself from here on out.
358 scheduleTickEvent(0);
361 InOrderCPU::~InOrderCPU()
366 std::map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
369 InOrderCPU::createFrontEndSked()
371 RSkedPtr res_sked
= NULL
;
373 StageScheduler
F(res_sked
, stage_num
++);
374 StageScheduler
D(res_sked
, stage_num
++);
377 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
378 F
.needs(ICache
, FetchUnit::InitiateFetch
);
381 D
.needs(ICache
, FetchUnit::CompleteFetch
);
382 D
.needs(Decode
, DecodeUnit::DecodeInst
);
383 D
.needs(BPred
, BranchPredictor::PredictBranch
);
384 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
390 InOrderCPU::createBackEndSked(DynInstPtr inst
)
392 RSkedPtr res_sked
= lookupSked(inst
);
393 if (res_sked
!= NULL
) {
397 int stage_num
= ThePipeline::BackEndStartStage
;
398 StageScheduler
X(res_sked
, stage_num
++);
399 StageScheduler
M(res_sked
, stage_num
++);
400 StageScheduler
W(res_sked
, stage_num
++);
402 if (!inst
->staticInst
) {
403 warn_once("Static Instruction Object Not Set. Can't Create"
404 " Back End Schedule");
409 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
410 if (!idx
|| !inst
->isStore()) {
411 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
415 if ( inst
->isNonSpeculative() ) {
416 // skip execution of non speculative insts until later
417 } else if ( inst
->isMemRef() ) {
418 if ( inst
->isLoad() ) {
419 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
421 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
422 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
424 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
427 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
428 X
.needs(MDU
, MultDivUnit::EndMultDiv
);
432 if ( inst
->isLoad() ) {
433 M
.needs(DCache
, CacheUnit::InitiateReadData
);
434 } else if ( inst
->isStore() ) {
435 if ( inst
->numSrcRegs() >= 2 ) {
436 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
438 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
439 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
444 if ( inst
->isLoad() ) {
445 W
.needs(DCache
, CacheUnit::CompleteReadData
);
446 } else if ( inst
->isStore() ) {
447 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
450 if ( inst
->isNonSpeculative() ) {
451 if ( inst
->isMemRef() ) fatal("Non-Speculative Memory Instruction");
452 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
455 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
456 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
459 W
.needs(Grad
, GraduationUnit::GraduateInst
);
465 InOrderCPU::regStats()
467 /* Register the Resource Pool's stats here.*/
470 /* Register for each Pipeline Stage */
471 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
472 pipelineStage
[stage_num
]->regStats();
475 /* Register any of the InOrderCPU's stats here.*/
477 .name(name() + ".instsPerContextSwitch")
478 .desc("Instructions Committed Per Context Switch")
479 .prereq(instsPerCtxtSwitch
);
482 .name(name() + ".contextSwitches")
483 .desc("Number of context switches");
486 .name(name() + ".comLoads")
487 .desc("Number of Load instructions committed");
490 .name(name() + ".comStores")
491 .desc("Number of Store instructions committed");
494 .name(name() + ".comBranches")
495 .desc("Number of Branches instructions committed");
498 .name(name() + ".comNops")
499 .desc("Number of Nop instructions committed");
502 .name(name() + ".comNonSpec")
503 .desc("Number of Non-Speculative instructions committed");
506 .name(name() + ".comInts")
507 .desc("Number of Integer instructions committed");
510 .name(name() + ".comFloats")
511 .desc("Number of Floating Point instructions committed");
514 .name(name() + ".timesIdled")
515 .desc("Number of times that the entire CPU went into an idle state and"
516 " unscheduled itself")
520 .name(name() + ".idleCycles")
521 .desc("Number of cycles cpu's stages were not processed");
524 .name(name() + ".runCycles")
525 .desc("Number of cycles cpu stages are processed.");
528 .name(name() + ".activity")
529 .desc("Percentage of cycles cpu is active")
531 activity
= (runCycles
/ numCycles
) * 100;
535 .name(name() + ".threadCycles")
536 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
539 .name(name() + ".smtCycles")
540 .desc("Total number of cycles that the CPU was in SMT-mode");
544 .name(name() + ".committedInsts")
545 .desc("Number of Instructions Simulated (Per-Thread)");
549 .name(name() + ".smtCommittedInsts")
550 .desc("Number of SMT Instructions Simulated (Per-Thread)");
553 .name(name() + ".committedInsts_total")
554 .desc("Number of Instructions Simulated (Total)");
557 .name(name() + ".cpi")
558 .desc("CPI: Cycles Per Instruction (Per-Thread)")
560 cpi
= numCycles
/ committedInsts
;
563 .name(name() + ".smt_cpi")
564 .desc("CPI: Total SMT-CPI")
566 smtCpi
= smtCycles
/ smtCommittedInsts
;
569 .name(name() + ".cpi_total")
570 .desc("CPI: Total CPI of All Threads")
572 totalCpi
= numCycles
/ totalCommittedInsts
;
575 .name(name() + ".ipc")
576 .desc("IPC: Instructions Per Cycle (Per-Thread)")
578 ipc
= committedInsts
/ numCycles
;
581 .name(name() + ".smt_ipc")
582 .desc("IPC: Total SMT-IPC")
584 smtIpc
= smtCommittedInsts
/ smtCycles
;
587 .name(name() + ".ipc_total")
588 .desc("IPC: Total IPC of All Threads")
590 totalIpc
= totalCommittedInsts
/ numCycles
;
599 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
603 bool pipes_idle
= true;
605 //Tick each of the stages
606 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
607 pipelineStage
[stNum
]->tick();
609 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
617 // Now advance the time buffers one tick
618 timeBuffer
.advance();
619 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
620 stageQueue
[sqNum
]->advance();
622 activityRec
.advance();
624 // Any squashed requests, events, or insts then remove them now
625 cleanUpRemovedReqs();
626 cleanUpRemovedEvents();
627 cleanUpRemovedInsts();
629 // Re-schedule CPU for this cycle
630 if (!tickEvent
.scheduled()) {
631 if (_status
== SwitchedOut
) {
633 lastRunningCycle
= curTick();
634 } else if (!activityRec
.active()) {
635 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
636 lastRunningCycle
= curTick();
639 //Tick next_tick = curTick() + cycles(1);
640 //tickEvent.schedule(next_tick);
641 schedule(&tickEvent
, nextCycle(curTick() + 1));
642 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
643 nextCycle(curTick() + 1));
648 updateThreadPriority();
655 if (!deferRegistration
) {
656 registerThreadContexts();
659 // Set inSyscall so that the CPU doesn't squash when initially
660 // setting up registers.
661 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
662 thread
[tid
]->inSyscall
= true;
665 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
666 ThreadContext
*src_tc
= threadContexts
[tid
];
667 TheISA::initCPU(src_tc
, src_tc
->contextId());
672 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
673 thread
[tid
]->inSyscall
= false;
675 // Call Initializiation Routine for Resource Pool
682 for (int i
= 0; i
< numThreads
; i
++) {
683 isa
[i
].reset(coreType
, numThreads
,
684 1/*numVirtProcs*/, dynamic_cast<BaseCPU
*>(this));
689 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
691 return resPool
->getPort(if_name
, idx
);
696 InOrderCPU::hwrei(ThreadID tid
)
698 panic("hwrei: Unimplemented");
705 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
707 panic("simPalCheck: Unimplemented");
714 InOrderCPU::getInterrupts()
716 // Check if there are any outstanding interrupts
717 return interrupts
->getInterrupt(threadContexts
[0]);
722 InOrderCPU::processInterrupts(Fault interrupt
)
724 // Check for interrupts here. For now can copy the code that
725 // exists within isa_fullsys_traits.hh. Also assume that thread 0
726 // is the one that handles the interrupts.
727 // @todo: Possibly consolidate the interrupt checking code.
728 // @todo: Allow other threads to handle interrupts.
730 assert(interrupt
!= NoFault
);
731 interrupts
->updateIntrInfo(threadContexts
[0]);
733 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
735 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
736 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
741 InOrderCPU::updateMemPorts()
743 // Update all ThreadContext's memory ports (Functional/Virtual
745 ThreadID size
= thread
.size();
746 for (ThreadID i
= 0; i
< size
; ++i
)
747 thread
[i
]->connectMemPorts(thread
[i
]->getTC());
752 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
754 //@ Squash Pipeline during TRAP
755 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
759 InOrderCPU::trapCPU(Fault fault
, ThreadID tid
, DynInstPtr inst
)
761 fault
->invoke(tcBase(tid
), inst
->staticInst
);
765 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
767 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
772 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
775 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
777 // Squash all instructions in each stage including
778 // instruction that caused the squash (seq_num - 1)
779 // NOTE: The stage bandwidth needs to be cleared so thats why
780 // the stalling instruction is squashed as well. The stalled
781 // instruction is previously placed in another intermediate buffer
782 // while it's stall is being handled.
783 InstSeqNum squash_seq_num
= seq_num
- 1;
785 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
786 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
791 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
792 ThreadID tid
, DynInstPtr inst
,
793 unsigned delay
, unsigned event_pri_offset
)
795 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
798 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
800 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
801 eventNames
[c_event
], curTick() + delay
, tid
);
802 schedule(cpu_event
, sked_tick
);
804 cpu_event
->process();
805 cpuEventRemoveList
.push(cpu_event
);
808 // Broadcast event to the Resource Pool
809 // Need to reset tid just in case this is a dummy instruction
811 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
815 InOrderCPU::isThreadActive(ThreadID tid
)
817 list
<ThreadID
>::iterator isActive
=
818 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
820 return (isActive
!= activeThreads
.end());
824 InOrderCPU::isThreadReady(ThreadID tid
)
826 list
<ThreadID
>::iterator isReady
=
827 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
829 return (isReady
!= readyThreads
.end());
833 InOrderCPU::isThreadSuspended(ThreadID tid
)
835 list
<ThreadID
>::iterator isSuspended
=
836 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
838 return (isSuspended
!= suspendedThreads
.end());
842 InOrderCPU::activateNextReadyThread()
844 if (readyThreads
.size() >= 1) {
845 ThreadID ready_tid
= readyThreads
.front();
847 // Activate in Pipeline
848 activateThread(ready_tid
);
850 // Activate in Resource Pool
851 resPool
->activateAll(ready_tid
);
853 list
<ThreadID
>::iterator ready_it
=
854 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
855 readyThreads
.erase(ready_it
);
858 "Attempting to activate new thread, but No Ready Threads to"
861 "Unable to switch to next active thread.\n");
866 InOrderCPU::activateThread(ThreadID tid
)
868 if (isThreadSuspended(tid
)) {
870 "Removing [tid:%i] from suspended threads list.\n", tid
);
872 list
<ThreadID
>::iterator susp_it
=
873 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
875 suspendedThreads
.erase(susp_it
);
878 if (threadModel
== SwitchOnCacheMiss
&&
879 numActiveThreads() == 1) {
881 "Ignoring activation of [tid:%i], since [tid:%i] is "
882 "already running.\n", tid
, activeThreadId());
884 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
887 readyThreads
.push_back(tid
);
889 } else if (!isThreadActive(tid
)) {
891 "Adding [tid:%i] to active threads list.\n", tid
);
892 activeThreads
.push_back(tid
);
894 activateThreadInPipeline(tid
);
896 thread
[tid
]->lastActivate
= curTick();
898 tcBase(tid
)->setStatus(ThreadContext::Active
);
907 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
909 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
910 pipelineStage
[stNum
]->activateThread(tid
);
915 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
917 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
919 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
921 // Be sure to signal that there's some activity so the CPU doesn't
922 // deschedule itself.
923 activityRec
.activity();
929 InOrderCPU::deactivateThread(ThreadID tid
)
931 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
933 if (isThreadActive(tid
)) {
934 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
936 list
<ThreadID
>::iterator thread_it
=
937 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
939 removePipelineStalls(*thread_it
);
941 activeThreads
.erase(thread_it
);
943 // Ideally, this should be triggered from the
944 // suspendContext/Thread functions
945 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
948 assert(!isThreadActive(tid
));
952 InOrderCPU::removePipelineStalls(ThreadID tid
)
954 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
957 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
958 pipelineStage
[stNum
]->removeStalls(tid
);
964 InOrderCPU::updateThreadPriority()
966 if (activeThreads
.size() > 1)
968 //DEFAULT TO ROUND ROBIN SCHEME
969 //e.g. Move highest priority to end of thread list
970 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
971 list
<ThreadID
>::iterator list_end
= activeThreads
.end();
973 unsigned high_thread
= *list_begin
;
975 activeThreads
.erase(list_begin
);
977 activeThreads
.push_back(high_thread
);
982 InOrderCPU::tickThreadStats()
984 /** Keep track of cycles that each thread is active */
985 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
986 while (thread_it
!= activeThreads
.end()) {
987 threadCycles
[*thread_it
]++;
991 // Keep track of cycles where SMT is active
992 if (activeThreads
.size() > 1) {
998 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1000 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1003 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1005 // Be sure to signal that there's some activity so the CPU doesn't
1006 // deschedule itself.
1007 activityRec
.activity();
1013 InOrderCPU::activateNextReadyContext(int delay
)
1015 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1017 // NOTE: Add 5 to the event priority so that we always activate
1018 // threads after we've finished deactivating, squashing,etc.
1020 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1023 // Be sure to signal that there's some activity so the CPU doesn't
1024 // deschedule itself.
1025 activityRec
.activity();
1031 InOrderCPU::haltContext(ThreadID tid
, int delay
)
1033 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1035 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1037 activityRec
.activity();
1041 InOrderCPU::haltThread(ThreadID tid
)
1043 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1044 deactivateThread(tid
);
1045 squashThreadInPipeline(tid
);
1046 haltedThreads
.push_back(tid
);
1048 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1050 if (threadModel
== SwitchOnCacheMiss
) {
1051 activateNextReadyContext();
1056 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
1058 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1062 InOrderCPU::suspendThread(ThreadID tid
)
1064 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1066 deactivateThread(tid
);
1067 suspendedThreads
.push_back(tid
);
1068 thread
[tid
]->lastSuspend
= curTick();
1070 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1074 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1076 //Squash all instructions in each stage
1077 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1078 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1083 InOrderCPU::getPipeStage(int stage_num
)
1085 return pipelineStage
[stage_num
];
1089 InOrderCPU::readIntReg(int reg_idx
, ThreadID tid
)
1091 return intRegs
[tid
][reg_idx
];
1095 InOrderCPU::readFloatReg(int reg_idx
, ThreadID tid
)
1097 return floatRegs
.f
[tid
][reg_idx
];
1101 InOrderCPU::readFloatRegBits(int reg_idx
, ThreadID tid
)
1103 return floatRegs
.i
[tid
][reg_idx
];
1107 InOrderCPU::setIntReg(int reg_idx
, uint64_t val
, ThreadID tid
)
1109 intRegs
[tid
][reg_idx
] = val
;
1114 InOrderCPU::setFloatReg(int reg_idx
, FloatReg val
, ThreadID tid
)
1116 floatRegs
.f
[tid
][reg_idx
] = val
;
1121 InOrderCPU::setFloatRegBits(int reg_idx
, FloatRegBits val
, ThreadID tid
)
1123 floatRegs
.i
[tid
][reg_idx
] = val
;
1127 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1129 // If Default value is set, then retrieve target thread
1130 if (tid
== InvalidThreadID
) {
1131 tid
= TheISA::getTargetThread(tcBase(tid
));
1134 if (reg_idx
< FP_Base_DepTag
) {
1135 // Integer Register File
1136 return readIntReg(reg_idx
, tid
);
1137 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1138 // Float Register File
1139 reg_idx
-= FP_Base_DepTag
;
1140 return readFloatRegBits(reg_idx
, tid
);
1142 reg_idx
-= Ctrl_Base_DepTag
;
1143 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1147 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1150 // If Default value is set, then retrieve target thread
1151 if (tid
== InvalidThreadID
) {
1152 tid
= TheISA::getTargetThread(tcBase(tid
));
1155 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1156 setIntReg(reg_idx
, val
, tid
);
1157 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1158 reg_idx
-= FP_Base_DepTag
;
1159 setFloatRegBits(reg_idx
, val
, tid
);
1161 reg_idx
-= Ctrl_Base_DepTag
;
1162 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1167 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1169 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1173 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1175 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1179 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1181 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1185 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1187 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1192 InOrderCPU::addInst(DynInstPtr
&inst
)
1194 ThreadID tid
= inst
->readTid();
1196 instList
[tid
].push_back(inst
);
1198 return --(instList
[tid
].end());
1202 InOrderCPU::updateContextSwitchStats()
1204 // Set Average Stat Here, then reset to 0
1205 instsPerCtxtSwitch
= instsPerSwitch
;
1211 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1213 // Set the CPU's PCs - This contributes to the precise state of the CPU
1214 // which can be used when restoring a thread to the CPU after after any
1215 // type of context switching activity (fork, exception, etc.)
1216 pcState(inst
->pcState(), tid
);
1218 if (inst
->isControl()) {
1219 thread
[tid
]->lastGradIsBranch
= true;
1220 thread
[tid
]->lastBranchPC
= inst
->pcState();
1221 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1223 thread
[tid
]->lastGradIsBranch
= false;
1227 // Finalize Trace Data For Instruction
1228 if (inst
->traceData
) {
1229 //inst->traceData->setCycle(curTick());
1230 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1231 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1232 inst
->traceData
->dump();
1233 delete inst
->traceData
;
1234 inst
->traceData
= NULL
;
1237 // Increment active thread's instruction count
1240 // Increment thread-state's instruction count
1241 thread
[tid
]->numInst
++;
1243 // Increment thread-state's instruction stats
1244 thread
[tid
]->numInsts
++;
1246 // Count committed insts per thread stats
1247 committedInsts
[tid
]++;
1249 // Count total insts committed stat
1250 totalCommittedInsts
++;
1252 // Count SMT-committed insts per thread stat
1253 if (numActiveThreads() > 1) {
1254 smtCommittedInsts
[tid
]++;
1257 // Instruction-Mix Stats
1258 if (inst
->isLoad()) {
1260 } else if (inst
->isStore()) {
1262 } else if (inst
->isControl()) {
1264 } else if (inst
->isNop()) {
1266 } else if (inst
->isNonSpeculative()) {
1268 } else if (inst
->isInteger()) {
1270 } else if (inst
->isFloating()) {
1274 // Check for instruction-count-based events.
1275 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1277 // Broadcast to other resources an instruction
1278 // has been completed
1279 resPool
->scheduleEvent((CPUEventType
)ResourcePool::InstGraduated
, inst
,
1282 // Finally, remove instruction from CPU
1286 // currently unused function, but substitute repetitive code w/this function
1289 InOrderCPU::addToRemoveList(DynInstPtr
&inst
)
1291 removeInstsThisCycle
= true;
1292 if (!inst
->isRemoveList()) {
1293 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1294 "[sn:%lli] to remove list\n",
1295 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1296 inst
->setRemoveList();
1297 removeList
.push(inst
->getInstListIt());
1299 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1300 "[sn:%lli], already remove list\n",
1301 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1307 InOrderCPU::removeInst(DynInstPtr
&inst
)
1309 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1311 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1313 removeInstsThisCycle
= true;
1315 // Remove the instruction.
1316 if (!inst
->isRemoveList()) {
1317 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1318 "[sn:%lli] to remove list\n",
1319 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1320 inst
->setRemoveList();
1321 removeList
.push(inst
->getInstListIt());
1323 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1324 "[sn:%lli], already on remove list\n",
1325 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1331 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1333 //assert(!instList[tid].empty());
1335 removeInstsThisCycle
= true;
1337 ListIt inst_iter
= instList
[tid
].end();
1341 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1342 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1343 tid
, seq_num
, (*inst_iter
)->seqNum
);
1345 while ((*inst_iter
)->seqNum
> seq_num
) {
1347 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1349 squashInstIt(inst_iter
, tid
);
1360 InOrderCPU::squashInstIt(const ListIt
&instIt
, ThreadID tid
)
1362 if ((*instIt
)->threadNumber
== tid
) {
1363 DPRINTF(InOrderCPU
, "Squashing instruction, "
1364 "[tid:%i] [sn:%lli] PC %s\n",
1365 (*instIt
)->threadNumber
,
1367 (*instIt
)->pcState());
1369 (*instIt
)->setSquashed();
1371 if (!(*instIt
)->isRemoveList()) {
1372 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1373 "[sn:%lli] to remove list\n",
1374 (*instIt
)->threadNumber
, (*instIt
)->pcState(),
1376 (*instIt
)->setRemoveList();
1377 removeList
.push(instIt
);
1379 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1380 " PC %s [sn:%lli], already on remove list\n",
1381 (*instIt
)->threadNumber
, (*instIt
)->pcState(),
1391 InOrderCPU::cleanUpRemovedInsts()
1393 while (!removeList
.empty()) {
1394 DPRINTF(InOrderCPU
, "Removing instruction, "
1395 "[tid:%i] [sn:%lli] PC %s\n",
1396 (*removeList
.front())->threadNumber
,
1397 (*removeList
.front())->seqNum
,
1398 (*removeList
.front())->pcState());
1400 DynInstPtr inst
= *removeList
.front();
1401 ThreadID tid
= inst
->threadNumber
;
1403 // Make Sure Resource Schedule Is Emptied Out
1404 ThePipeline::ResSchedule
*inst_sched
= &inst
->resSched
;
1405 while (!inst_sched
->empty()) {
1406 ScheduleEntry
* sch_entry
= inst_sched
->top();
1411 // Remove From Register Dependency Map, If Necessary
1412 archRegDepMap
[(*removeList
.front())->threadNumber
].
1413 remove((*removeList
.front()));
1416 // Clear if Non-Speculative
1417 if (inst
->staticInst
&&
1418 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1419 nonSpecInstActive
[tid
] == true) {
1420 nonSpecInstActive
[tid
] = false;
1423 instList
[tid
].erase(removeList
.front());
1428 removeInstsThisCycle
= false;
1432 InOrderCPU::cleanUpRemovedReqs()
1434 while (!reqRemoveList
.empty()) {
1435 ResourceRequest
*res_req
= reqRemoveList
.front();
1437 DPRINTF(RefCount
, "[tid:%i] [sn:%lli]: Removing Request "
1438 "[stage_num:%i] [res:%s] [slot:%i] [completed:%i].\n",
1439 res_req
->inst
->threadNumber
,
1440 res_req
->inst
->seqNum
,
1441 res_req
->getStageNum(),
1442 res_req
->res
->name(),
1443 (res_req
->isCompleted()) ?
1444 res_req
->getComplSlot() : res_req
->getSlot(),
1445 res_req
->isCompleted());
1447 reqRemoveList
.pop();
1454 InOrderCPU::cleanUpRemovedEvents()
1456 while (!cpuEventRemoveList
.empty()) {
1457 Event
*cpu_event
= cpuEventRemoveList
.front();
1458 cpuEventRemoveList
.pop();
1465 InOrderCPU::dumpInsts()
1469 ListIt inst_list_it
= instList
[0].begin();
1471 cprintf("Dumping Instruction List\n");
1473 while (inst_list_it
!= instList
[0].end()) {
1474 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1476 num
, (*inst_list_it
)->pcState(),
1477 (*inst_list_it
)->threadNumber
,
1478 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1479 (*inst_list_it
)->isSquashed());
1486 InOrderCPU::wakeCPU()
1488 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1489 DPRINTF(Activity
, "CPU already running.\n");
1493 DPRINTF(Activity
, "Waking up CPU\n");
1495 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1497 idleCycles
+= extra_cycles
;
1498 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1499 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1502 numCycles
+= extra_cycles
;
1504 schedule(&tickEvent
, nextCycle(curTick()));
1510 InOrderCPU::wakeup()
1512 if (thread
[0]->status() != ThreadContext::Suspended
)
1517 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1518 threadContexts
[0]->activate();
1524 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1526 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1528 DPRINTF(Activity
,"Activity: syscall() called.\n");
1530 // Temporarily increase this by one to account for the syscall
1532 ++(this->thread
[tid
]->funcExeInst
);
1534 // Execute the actual syscall.
1535 this->thread
[tid
]->syscall(callnum
);
1537 // Decrease funcExeInst by one as the normal commit will handle
1539 --(this->thread
[tid
]->funcExeInst
);
1541 // Clear Non-Speculative Block Variable
1542 nonSpecInstActive
[tid
] = false;
1547 InOrderCPU::getITBPtr()
1549 CacheUnit
*itb_res
=
1550 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1551 return itb_res
->tlb();
1556 InOrderCPU::getDTBPtr()
1558 CacheUnit
*dtb_res
=
1559 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1560 return dtb_res
->tlb();
1564 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1565 uint8_t *data
, unsigned size
, unsigned flags
)
1567 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1568 // you want to run w/out caches?
1569 CacheUnit
*cache_res
=
1570 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1572 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1576 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1577 Addr addr
, unsigned flags
, uint64_t *write_res
)
1579 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1580 // you want to run w/out caches?
1581 CacheUnit
*cache_res
=
1582 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1583 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);