2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "config/full_system.hh"
36 #include "config/the_isa.hh"
37 #include "cpu/activity.hh"
38 #include "cpu/base.hh"
39 #include "cpu/exetrace.hh"
40 #include "cpu/inorder/cpu.hh"
41 #include "cpu/inorder/first_stage.hh"
42 #include "cpu/inorder/inorder_dyn_inst.hh"
43 #include "cpu/inorder/pipeline_traits.hh"
44 #include "cpu/inorder/resource_pool.hh"
45 #include "cpu/inorder/resources/resource_list.hh"
46 #include "cpu/inorder/thread_context.hh"
47 #include "cpu/inorder/thread_state.hh"
48 #include "cpu/simple_thread.hh"
49 #include "cpu/thread_context.hh"
50 #include "mem/translating_port.hh"
51 #include "params/InOrderCPU.hh"
52 #include "sim/process.hh"
53 #include "sim/stat_control.hh"
56 #include "cpu/quiesce_event.hh"
57 #include "sim/system.hh"
60 #if THE_ISA == ALPHA_ISA
61 #include "arch/alpha/osfpal.hh"
65 using namespace TheISA
;
66 using namespace ThePipeline
;
68 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
69 : Event(CPU_Tick_Pri
), cpu(c
)
74 InOrderCPU::TickEvent::process()
81 InOrderCPU::TickEvent::description()
83 return "InOrderCPU tick event";
86 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
87 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
88 unsigned event_pri_offset
)
89 : Event(Event::Priority((unsigned int)CPU_Tick_Pri
+ event_pri_offset
)),
92 setEvent(e_type
, fault
, _tid
, inst
);
96 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
99 "ActivateNextReadyThread",
105 "SquashFromMemStall",
110 InOrderCPU::CPUEvent::process()
112 switch (cpuEventType
)
115 cpu
->activateThread(tid
);
118 case ActivateNextReadyThread
:
119 cpu
->activateNextReadyThread();
122 case DeactivateThread
:
123 cpu
->deactivateThread(tid
);
127 cpu
->haltThread(tid
);
131 cpu
->suspendThread(tid
);
134 case SquashFromMemStall
:
135 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
139 cpu
->trapCPU(fault
, tid
);
143 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
146 cpu
->cpuEventRemoveList
.push(this);
152 InOrderCPU::CPUEvent::description()
154 return "InOrderCPU event";
158 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
161 mainEventQueue
.reschedule(this, cpu
->nextCycle(curTick
+
163 else if (!scheduled())
164 mainEventQueue
.schedule(this, cpu
->nextCycle(curTick
+
169 InOrderCPU::CPUEvent::unscheduleEvent()
175 InOrderCPU::InOrderCPU(Params
*params
)
177 cpu_id(params
->cpu_id
),
182 removeInstsThisCycle(false),
183 activityRec(params
->name
, NumStages
, 10, params
->activity
),
185 system(params
->system
),
186 physmem(system
->physmem
),
187 #endif // FULL_SYSTEM
193 deferRegistration(false/*params->deferRegistration*/),
194 stageTracing(params
->stageTracing
),
197 ThreadID active_threads
;
200 resPool
= new ResourcePool(this, params
);
202 // Resize for Multithreading CPUs
203 thread
.resize(numThreads
);
208 active_threads
= params
->workload
.size();
210 if (active_threads
> MaxThreads
) {
211 panic("Workload Size too large. Increase the 'MaxThreads'"
212 "in your InOrder implementation or "
213 "edit your workload size.");
217 if (active_threads
> 1) {
218 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
220 if (threadModel
== SMT
) {
221 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
222 } else if (threadModel
== SwitchOnCacheMiss
) {
223 DPRINTF(InOrderCPU
, "Setting Thread Model to "
224 "Switch On Cache Miss\n");
228 threadModel
= Single
;
235 // Bind the fetch & data ports from the resource pool.
236 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
237 if (fetchPortIdx
== 0) {
238 fatal("Unable to find port to fetch instructions from.\n");
241 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
242 if (dataPortIdx
== 0) {
243 fatal("Unable to find port for data.\n");
246 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
248 // SMT is not supported in FS mode yet.
249 assert(numThreads
== 1);
250 thread
[tid
] = new Thread(this, 0);
252 if (tid
< (ThreadID
)params
->workload
.size()) {
253 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
254 tid
, params
->workload
[tid
]->prog_fname
);
256 new Thread(this, tid
, params
->workload
[tid
]);
258 //Allocate Empty thread so M5 can use later
259 //when scheduling threads to CPU
260 Process
* dummy_proc
= params
->workload
[0];
261 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
264 // Eventually set this with parameters...
268 // Setup the TC that will serve as the interface to the threads/CPU.
269 InOrderThreadContext
*tc
= new InOrderThreadContext
;
271 tc
->thread
= thread
[tid
];
273 // Give the thread the TC.
274 thread
[tid
]->tc
= tc
;
275 thread
[tid
]->setFuncExeInst(0);
276 globalSeqNum
[tid
] = 1;
278 // Add the TC to the CPU's list of TC's.
279 this->threadContexts
.push_back(tc
);
282 // Initialize TimeBuffer Stage Queues
283 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
284 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
285 stageQueue
[stNum
]->id(stNum
);
289 // Set Up Pipeline Stages
290 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
292 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
294 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
296 pipelineStage
[stNum
]->setCPU(this);
297 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
298 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
300 // Take Care of 1st/Nth stages
302 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
303 if (stNum
< NumStages
- 1)
304 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
307 // Initialize thread specific variables
308 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
309 archRegDepMap
[tid
].setCPU(this);
311 nonSpecInstActive
[tid
] = false;
312 nonSpecSeqNum
[tid
] = 0;
314 squashSeqNum
[tid
] = MaxAddr
;
315 lastSquashCycle
[tid
] = 0;
317 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
318 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
321 isa
[tid
].expandForMultithreading(numThreads
, 1/*numVirtProcs*/);
323 // Define dummy instructions and resource requests to be used.
324 dummyInst
[tid
] = new InOrderDynInst(this,
330 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0),
338 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
339 dummyReqInst
->setSquashed();
341 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
342 dummyBufferInst
->setSquashed();
344 lastRunningCycle
= curTick
;
346 // Reset CPU to reset state.
348 Fault resetFault
= new ResetFault();
349 resetFault
->invoke(tcBase());
354 dummyBufferInst
->resetInstCount();
356 // Schedule First Tick Event, CPU will reschedule itself from here on out.
357 scheduleTickEvent(0);
360 InOrderCPU::~InOrderCPU()
367 InOrderCPU::regStats()
369 /* Register the Resource Pool's stats here.*/
372 /* Register for each Pipeline Stage */
373 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
374 pipelineStage
[stage_num
]->regStats();
377 /* Register any of the InOrderCPU's stats here.*/
379 .name(name() + ".instsPerContextSwitch")
380 .desc("Instructions Committed Per Context Switch")
381 .prereq(instsPerCtxtSwitch
);
384 .name(name() + ".contextSwitches")
385 .desc("Number of context switches");
388 .name(name() + ".comLoads")
389 .desc("Number of Load instructions committed");
392 .name(name() + ".comStores")
393 .desc("Number of Store instructions committed");
396 .name(name() + ".comBranches")
397 .desc("Number of Branches instructions committed");
400 .name(name() + ".comNops")
401 .desc("Number of Nop instructions committed");
404 .name(name() + ".comNonSpec")
405 .desc("Number of Non-Speculative instructions committed");
408 .name(name() + ".comInts")
409 .desc("Number of Integer instructions committed");
412 .name(name() + ".comFloats")
413 .desc("Number of Floating Point instructions committed");
416 .name(name() + ".timesIdled")
417 .desc("Number of times that the entire CPU went into an idle state and"
418 " unscheduled itself")
422 .name(name() + ".idleCycles")
423 .desc("Number of cycles cpu's stages were not processed");
426 .name(name() + ".runCycles")
427 .desc("Number of cycles cpu stages are processed.");
430 .name(name() + ".activity")
431 .desc("Percentage of cycles cpu is active")
433 activity
= (runCycles
/ numCycles
) * 100;
437 .name(name() + ".threadCycles")
438 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
441 .name(name() + ".smtCycles")
442 .desc("Total number of cycles that the CPU was in SMT-mode");
446 .name(name() + ".committedInsts")
447 .desc("Number of Instructions Simulated (Per-Thread)");
451 .name(name() + ".smtCommittedInsts")
452 .desc("Number of SMT Instructions Simulated (Per-Thread)");
455 .name(name() + ".committedInsts_total")
456 .desc("Number of Instructions Simulated (Total)");
459 .name(name() + ".cpi")
460 .desc("CPI: Cycles Per Instruction (Per-Thread)")
462 cpi
= numCycles
/ committedInsts
;
465 .name(name() + ".smt_cpi")
466 .desc("CPI: Total SMT-CPI")
468 smtCpi
= smtCycles
/ smtCommittedInsts
;
471 .name(name() + ".cpi_total")
472 .desc("CPI: Total CPI of All Threads")
474 totalCpi
= numCycles
/ totalCommittedInsts
;
477 .name(name() + ".ipc")
478 .desc("IPC: Instructions Per Cycle (Per-Thread)")
480 ipc
= committedInsts
/ numCycles
;
483 .name(name() + ".smt_ipc")
484 .desc("IPC: Total SMT-IPC")
486 smtIpc
= smtCommittedInsts
/ smtCycles
;
489 .name(name() + ".ipc_total")
490 .desc("IPC: Total IPC of All Threads")
492 totalIpc
= totalCommittedInsts
/ numCycles
;
501 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
505 bool pipes_idle
= true;
507 //Tick each of the stages
508 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
509 pipelineStage
[stNum
]->tick();
511 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
519 // Now advance the time buffers one tick
520 timeBuffer
.advance();
521 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
522 stageQueue
[sqNum
]->advance();
524 activityRec
.advance();
526 // Any squashed requests, events, or insts then remove them now
527 cleanUpRemovedReqs();
528 cleanUpRemovedEvents();
529 cleanUpRemovedInsts();
531 // Re-schedule CPU for this cycle
532 if (!tickEvent
.scheduled()) {
533 if (_status
== SwitchedOut
) {
535 lastRunningCycle
= curTick
;
536 } else if (!activityRec
.active()) {
537 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
538 lastRunningCycle
= curTick
;
541 //Tick next_tick = curTick + cycles(1);
542 //tickEvent.schedule(next_tick);
543 mainEventQueue
.schedule(&tickEvent
, nextCycle(curTick
+ 1));
544 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
545 nextCycle(curTick
+ 1));
550 updateThreadPriority();
557 if (!deferRegistration
) {
558 registerThreadContexts();
561 // Set inSyscall so that the CPU doesn't squash when initially
562 // setting up registers.
563 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
564 thread
[tid
]->inSyscall
= true;
567 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
568 ThreadContext
*src_tc
= threadContexts
[tid
];
569 TheISA::initCPU(src_tc
, src_tc
->contextId());
574 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
575 thread
[tid
]->inSyscall
= false;
577 // Call Initializiation Routine for Resource Pool
584 for (int i
= 0; i
< numThreads
; i
++) {
585 isa
[i
].reset(coreType
, numThreads
,
586 1/*numVirtProcs*/, dynamic_cast<BaseCPU
*>(this));
591 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
593 return resPool
->getPort(if_name
, idx
);
598 InOrderCPU::hwrei(ThreadID tid
)
600 panic("hwrei: Unimplemented");
607 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
609 panic("simPalCheck: Unimplemented");
616 InOrderCPU::getInterrupts()
618 // Check if there are any outstanding interrupts
619 return this->interrupts
->getInterrupt(this->threadContexts
[0]);
624 InOrderCPU::processInterrupts(Fault interrupt
)
626 // Check for interrupts here. For now can copy the code that
627 // exists within isa_fullsys_traits.hh. Also assume that thread 0
628 // is the one that handles the interrupts.
629 // @todo: Possibly consolidate the interrupt checking code.
630 // @todo: Allow other threads to handle interrupts.
632 assert(interrupt
!= NoFault
);
633 this->interrupts
->updateIntrInfo(this->threadContexts
[0]);
635 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
636 this->trap(interrupt
, 0);
641 InOrderCPU::updateMemPorts()
643 // Update all ThreadContext's memory ports (Functional/Virtual
645 ThreadID size
= thread
.size();
646 for (ThreadID i
= 0; i
< size
; ++i
)
647 thread
[i
]->connectMemPorts(thread
[i
]->getTC());
652 InOrderCPU::trap(Fault fault
, ThreadID tid
, int delay
)
654 //@ Squash Pipeline during TRAP
655 scheduleCpuEvent(Trap
, fault
, tid
, dummyInst
[tid
], delay
);
659 InOrderCPU::trapCPU(Fault fault
, ThreadID tid
)
661 fault
->invoke(tcBase(tid
));
665 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
667 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
672 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
675 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
677 // Squash all instructions in each stage including
678 // instruction that caused the squash (seq_num - 1)
679 // NOTE: The stage bandwidth needs to be cleared so thats why
680 // the stalling instruction is squashed as well. The stalled
681 // instruction is previously placed in another intermediate buffer
682 // while it's stall is being handled.
683 InstSeqNum squash_seq_num
= seq_num
- 1;
685 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
686 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
691 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
692 ThreadID tid
, DynInstPtr inst
,
693 unsigned delay
, unsigned event_pri_offset
)
695 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
698 Tick sked_tick
= nextCycle(curTick
+ ticks(delay
));
700 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
701 eventNames
[c_event
], curTick
+ delay
, tid
);
702 mainEventQueue
.schedule(cpu_event
, sked_tick
);
704 cpu_event
->process();
705 cpuEventRemoveList
.push(cpu_event
);
708 // Broadcast event to the Resource Pool
709 // Need to reset tid just in case this is a dummy instruction
711 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
715 InOrderCPU::isThreadActive(ThreadID tid
)
717 list
<ThreadID
>::iterator isActive
=
718 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
720 return (isActive
!= activeThreads
.end());
724 InOrderCPU::isThreadReady(ThreadID tid
)
726 list
<ThreadID
>::iterator isReady
=
727 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
729 return (isReady
!= readyThreads
.end());
733 InOrderCPU::isThreadSuspended(ThreadID tid
)
735 list
<ThreadID
>::iterator isSuspended
=
736 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
738 return (isSuspended
!= suspendedThreads
.end());
742 InOrderCPU::activateNextReadyThread()
744 if (readyThreads
.size() >= 1) {
745 ThreadID ready_tid
= readyThreads
.front();
747 // Activate in Pipeline
748 activateThread(ready_tid
);
750 // Activate in Resource Pool
751 resPool
->activateAll(ready_tid
);
753 list
<ThreadID
>::iterator ready_it
=
754 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
755 readyThreads
.erase(ready_it
);
758 "Attempting to activate new thread, but No Ready Threads to"
761 "Unable to switch to next active thread.\n");
766 InOrderCPU::activateThread(ThreadID tid
)
768 if (isThreadSuspended(tid
)) {
770 "Removing [tid:%i] from suspended threads list.\n", tid
);
772 list
<ThreadID
>::iterator susp_it
=
773 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
775 suspendedThreads
.erase(susp_it
);
778 if (threadModel
== SwitchOnCacheMiss
&&
779 numActiveThreads() == 1) {
781 "Ignoring activation of [tid:%i], since [tid:%i] is "
782 "already running.\n", tid
, activeThreadId());
784 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
787 readyThreads
.push_back(tid
);
789 } else if (!isThreadActive(tid
)) {
791 "Adding [tid:%i] to active threads list.\n", tid
);
792 activeThreads
.push_back(tid
);
794 activateThreadInPipeline(tid
);
796 thread
[tid
]->lastActivate
= curTick
;
798 tcBase(tid
)->setStatus(ThreadContext::Active
);
807 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
809 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
810 pipelineStage
[stNum
]->activateThread(tid
);
815 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
817 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
819 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
821 // Be sure to signal that there's some activity so the CPU doesn't
822 // deschedule itself.
823 activityRec
.activity();
829 InOrderCPU::deactivateThread(ThreadID tid
)
831 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
833 if (isThreadActive(tid
)) {
834 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
836 list
<ThreadID
>::iterator thread_it
=
837 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
839 removePipelineStalls(*thread_it
);
841 activeThreads
.erase(thread_it
);
843 // Ideally, this should be triggered from the
844 // suspendContext/Thread functions
845 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
848 assert(!isThreadActive(tid
));
852 InOrderCPU::removePipelineStalls(ThreadID tid
)
854 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
857 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
858 pipelineStage
[stNum
]->removeStalls(tid
);
864 InOrderCPU::updateThreadPriority()
866 if (activeThreads
.size() > 1)
868 //DEFAULT TO ROUND ROBIN SCHEME
869 //e.g. Move highest priority to end of thread list
870 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
871 list
<ThreadID
>::iterator list_end
= activeThreads
.end();
873 unsigned high_thread
= *list_begin
;
875 activeThreads
.erase(list_begin
);
877 activeThreads
.push_back(high_thread
);
882 InOrderCPU::tickThreadStats()
884 /** Keep track of cycles that each thread is active */
885 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
886 while (thread_it
!= activeThreads
.end()) {
887 threadCycles
[*thread_it
]++;
891 // Keep track of cycles where SMT is active
892 if (activeThreads
.size() > 1) {
898 InOrderCPU::activateContext(ThreadID tid
, int delay
)
900 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
903 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
905 // Be sure to signal that there's some activity so the CPU doesn't
906 // deschedule itself.
907 activityRec
.activity();
913 InOrderCPU::activateNextReadyContext(int delay
)
915 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
917 // NOTE: Add 5 to the event priority so that we always activate
918 // threads after we've finished deactivating, squashing,etc.
920 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
923 // Be sure to signal that there's some activity so the CPU doesn't
924 // deschedule itself.
925 activityRec
.activity();
931 InOrderCPU::haltContext(ThreadID tid
, int delay
)
933 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
935 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
937 activityRec
.activity();
941 InOrderCPU::haltThread(ThreadID tid
)
943 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
944 deactivateThread(tid
);
945 squashThreadInPipeline(tid
);
946 haltedThreads
.push_back(tid
);
948 tcBase(tid
)->setStatus(ThreadContext::Halted
);
950 if (threadModel
== SwitchOnCacheMiss
) {
951 activateNextReadyContext();
956 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
958 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
962 InOrderCPU::suspendThread(ThreadID tid
)
964 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
966 deactivateThread(tid
);
967 suspendedThreads
.push_back(tid
);
968 thread
[tid
]->lastSuspend
= curTick
;
970 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
974 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
976 //Squash all instructions in each stage
977 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
978 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
983 InOrderCPU::getPipeStage(int stage_num
)
985 return pipelineStage
[stage_num
];
989 InOrderCPU::readPC(ThreadID tid
)
996 InOrderCPU::setPC(Addr new_PC
, ThreadID tid
)
1003 InOrderCPU::readNextPC(ThreadID tid
)
1010 InOrderCPU::setNextPC(uint64_t new_NPC
, ThreadID tid
)
1012 nextPC
[tid
] = new_NPC
;
1017 InOrderCPU::readNextNPC(ThreadID tid
)
1019 return nextNPC
[tid
];
1024 InOrderCPU::setNextNPC(uint64_t new_NNPC
, ThreadID tid
)
1026 nextNPC
[tid
] = new_NNPC
;
1030 InOrderCPU::readIntReg(int reg_idx
, ThreadID tid
)
1032 return intRegs
[tid
][reg_idx
];
1036 InOrderCPU::readFloatReg(int reg_idx
, ThreadID tid
)
1038 return floatRegs
.f
[tid
][reg_idx
];
1042 InOrderCPU::readFloatRegBits(int reg_idx
, ThreadID tid
)
1044 return floatRegs
.i
[tid
][reg_idx
];
1048 InOrderCPU::setIntReg(int reg_idx
, uint64_t val
, ThreadID tid
)
1050 intRegs
[tid
][reg_idx
] = val
;
1055 InOrderCPU::setFloatReg(int reg_idx
, FloatReg val
, ThreadID tid
)
1057 floatRegs
.f
[tid
][reg_idx
] = val
;
1062 InOrderCPU::setFloatRegBits(int reg_idx
, FloatRegBits val
, ThreadID tid
)
1064 floatRegs
.i
[tid
][reg_idx
] = val
;
1068 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1070 // If Default value is set, then retrieve target thread
1071 if (tid
== InvalidThreadID
) {
1072 tid
= TheISA::getTargetThread(tcBase(tid
));
1075 if (reg_idx
< FP_Base_DepTag
) {
1076 // Integer Register File
1077 return readIntReg(reg_idx
, tid
);
1078 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1079 // Float Register File
1080 reg_idx
-= FP_Base_DepTag
;
1081 return readFloatRegBits(reg_idx
, tid
);
1083 reg_idx
-= Ctrl_Base_DepTag
;
1084 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1088 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1091 // If Default value is set, then retrieve target thread
1092 if (tid
== InvalidThreadID
) {
1093 tid
= TheISA::getTargetThread(tcBase(tid
));
1096 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1097 setIntReg(reg_idx
, val
, tid
);
1098 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1099 reg_idx
-= FP_Base_DepTag
;
1100 setFloatRegBits(reg_idx
, val
, tid
);
1102 reg_idx
-= Ctrl_Base_DepTag
;
1103 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1108 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1110 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1114 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1116 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1120 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1122 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1126 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1128 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1133 InOrderCPU::addInst(DynInstPtr
&inst
)
1135 ThreadID tid
= inst
->readTid();
1137 instList
[tid
].push_back(inst
);
1139 return --(instList
[tid
].end());
1143 InOrderCPU::updateContextSwitchStats()
1145 // Set Average Stat Here, then reset to 0
1146 instsPerCtxtSwitch
= instsPerSwitch
;
1152 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1154 // Set the CPU's PCs - This contributes to the precise state of the CPU
1155 // which can be used when restoring a thread to the CPU after after any
1156 // type of context switching activity (fork, exception, etc.)
1157 setPC(inst
->readPC(), tid
);
1158 setNextPC(inst
->readNextPC(), tid
);
1159 setNextNPC(inst
->readNextNPC(), tid
);
1161 if (inst
->isControl()) {
1162 thread
[tid
]->lastGradIsBranch
= true;
1163 thread
[tid
]->lastBranchPC
= inst
->readPC();
1164 thread
[tid
]->lastBranchNextPC
= inst
->readNextPC();
1165 thread
[tid
]->lastBranchNextNPC
= inst
->readNextNPC();
1167 thread
[tid
]->lastGradIsBranch
= false;
1171 // Finalize Trace Data For Instruction
1172 if (inst
->traceData
) {
1173 //inst->traceData->setCycle(curTick);
1174 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1175 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1176 inst
->traceData
->dump();
1177 delete inst
->traceData
;
1178 inst
->traceData
= NULL
;
1181 // Increment active thread's instruction count
1184 // Increment thread-state's instruction count
1185 thread
[tid
]->numInst
++;
1187 // Increment thread-state's instruction stats
1188 thread
[tid
]->numInsts
++;
1190 // Count committed insts per thread stats
1191 committedInsts
[tid
]++;
1193 // Count total insts committed stat
1194 totalCommittedInsts
++;
1196 // Count SMT-committed insts per thread stat
1197 if (numActiveThreads() > 1) {
1198 smtCommittedInsts
[tid
]++;
1201 // Instruction-Mix Stats
1202 if (inst
->isLoad()) {
1204 } else if (inst
->isStore()) {
1206 } else if (inst
->isControl()) {
1208 } else if (inst
->isNop()) {
1210 } else if (inst
->isNonSpeculative()) {
1212 } else if (inst
->isInteger()) {
1214 } else if (inst
->isFloating()) {
1218 // Check for instruction-count-based events.
1219 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1221 // Broadcast to other resources an instruction
1222 // has been completed
1223 resPool
->scheduleEvent((CPUEventType
)ResourcePool::InstGraduated
, inst
,
1226 // Finally, remove instruction from CPU
1230 // currently unused function, but substitute repetitive code w/this function
1233 InOrderCPU::addToRemoveList(DynInstPtr
&inst
)
1235 removeInstsThisCycle
= true;
1236 if (!inst
->isRemoveList()) {
1237 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %#x "
1238 "[sn:%lli] to remove list\n",
1239 inst
->threadNumber
, inst
->readPC(), inst
->seqNum
);
1240 inst
->setRemoveList();
1241 removeList
.push(inst
->getInstListIt());
1243 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %#x "
1244 "[sn:%lli], already remove list\n",
1245 inst
->threadNumber
, inst
->readPC(), inst
->seqNum
);
1251 InOrderCPU::removeInst(DynInstPtr
&inst
)
1253 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %#x "
1255 inst
->threadNumber
, inst
->readPC(), inst
->seqNum
);
1257 removeInstsThisCycle
= true;
1259 // Remove the instruction.
1260 if (!inst
->isRemoveList()) {
1261 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %#x "
1262 "[sn:%lli] to remove list\n",
1263 inst
->threadNumber
, inst
->readPC(), inst
->seqNum
);
1264 inst
->setRemoveList();
1265 removeList
.push(inst
->getInstListIt());
1267 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %#x "
1268 "[sn:%lli], already on remove list\n",
1269 inst
->threadNumber
, inst
->readPC(), inst
->seqNum
);
1275 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1277 //assert(!instList[tid].empty());
1279 removeInstsThisCycle
= true;
1281 ListIt inst_iter
= instList
[tid
].end();
1285 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1286 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1287 tid
, seq_num
, (*inst_iter
)->seqNum
);
1289 while ((*inst_iter
)->seqNum
> seq_num
) {
1291 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1293 squashInstIt(inst_iter
, tid
);
1304 InOrderCPU::squashInstIt(const ListIt
&instIt
, ThreadID tid
)
1306 if ((*instIt
)->threadNumber
== tid
) {
1307 DPRINTF(InOrderCPU
, "Squashing instruction, "
1308 "[tid:%i] [sn:%lli] PC %#x\n",
1309 (*instIt
)->threadNumber
,
1311 (*instIt
)->readPC());
1313 (*instIt
)->setSquashed();
1315 if (!(*instIt
)->isRemoveList()) {
1316 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %#x "
1317 "[sn:%lli] to remove list\n",
1318 (*instIt
)->threadNumber
, (*instIt
)->readPC(),
1320 (*instIt
)->setRemoveList();
1321 removeList
.push(instIt
);
1323 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1324 " PC %#x [sn:%lli], already on remove list\n",
1325 (*instIt
)->threadNumber
, (*instIt
)->readPC(),
1335 InOrderCPU::cleanUpRemovedInsts()
1337 while (!removeList
.empty()) {
1338 DPRINTF(InOrderCPU
, "Removing instruction, "
1339 "[tid:%i] [sn:%lli] PC %#x\n",
1340 (*removeList
.front())->threadNumber
,
1341 (*removeList
.front())->seqNum
,
1342 (*removeList
.front())->readPC());
1344 DynInstPtr inst
= *removeList
.front();
1345 ThreadID tid
= inst
->threadNumber
;
1347 // Make Sure Resource Schedule Is Emptied Out
1348 ThePipeline::ResSchedule
*inst_sched
= &inst
->resSched
;
1349 while (!inst_sched
->empty()) {
1350 ScheduleEntry
* sch_entry
= inst_sched
->top();
1355 // Remove From Register Dependency Map, If Necessary
1356 archRegDepMap
[(*removeList
.front())->threadNumber
].
1357 remove((*removeList
.front()));
1360 // Clear if Non-Speculative
1361 if (inst
->staticInst
&&
1362 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1363 nonSpecInstActive
[tid
] == true) {
1364 nonSpecInstActive
[tid
] = false;
1367 instList
[tid
].erase(removeList
.front());
1372 removeInstsThisCycle
= false;
1376 InOrderCPU::cleanUpRemovedReqs()
1378 while (!reqRemoveList
.empty()) {
1379 ResourceRequest
*res_req
= reqRemoveList
.front();
1381 DPRINTF(RefCount
, "[tid:%i] [sn:%lli]: Removing Request "
1382 "[stage_num:%i] [res:%s] [slot:%i] [completed:%i].\n",
1383 res_req
->inst
->threadNumber
,
1384 res_req
->inst
->seqNum
,
1385 res_req
->getStageNum(),
1386 res_req
->res
->name(),
1387 (res_req
->isCompleted()) ?
1388 res_req
->getComplSlot() : res_req
->getSlot(),
1389 res_req
->isCompleted());
1391 reqRemoveList
.pop();
1398 InOrderCPU::cleanUpRemovedEvents()
1400 while (!cpuEventRemoveList
.empty()) {
1401 Event
*cpu_event
= cpuEventRemoveList
.front();
1402 cpuEventRemoveList
.pop();
1409 InOrderCPU::dumpInsts()
1413 ListIt inst_list_it
= instList
[0].begin();
1415 cprintf("Dumping Instruction List\n");
1417 while (inst_list_it
!= instList
[0].end()) {
1418 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1420 num
, (*inst_list_it
)->readPC(), (*inst_list_it
)->threadNumber
,
1421 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1422 (*inst_list_it
)->isSquashed());
1429 InOrderCPU::wakeCPU()
1431 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1432 DPRINTF(Activity
, "CPU already running.\n");
1436 DPRINTF(Activity
, "Waking up CPU\n");
1438 Tick extra_cycles
= tickToCycles((curTick
- 1) - lastRunningCycle
);
1440 idleCycles
+= extra_cycles
;
1441 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1442 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1445 numCycles
+= extra_cycles
;
1447 mainEventQueue
.schedule(&tickEvent
, nextCycle(curTick
));
1453 InOrderCPU::wakeup()
1455 if (this->thread
[0]->status() != ThreadContext::Suspended
)
1460 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1461 this->threadContexts
[0]->activate();
1467 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1469 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1471 DPRINTF(Activity
,"Activity: syscall() called.\n");
1473 // Temporarily increase this by one to account for the syscall
1475 ++(this->thread
[tid
]->funcExeInst
);
1477 // Execute the actual syscall.
1478 this->thread
[tid
]->syscall(callnum
);
1480 // Decrease funcExeInst by one as the normal commit will handle
1482 --(this->thread
[tid
]->funcExeInst
);
1484 // Clear Non-Speculative Block Variable
1485 nonSpecInstActive
[tid
] = false;
1490 InOrderCPU::prefetch(DynInstPtr inst
)
1492 Resource
*mem_res
= resPool
->getResource(dataPortIdx
);
1493 return mem_res
->prefetch(inst
);
1497 InOrderCPU::writeHint(DynInstPtr inst
)
1499 Resource
*mem_res
= resPool
->getResource(dataPortIdx
);
1500 return mem_res
->writeHint(inst
);
1505 InOrderCPU::getITBPtr()
1507 CacheUnit
*itb_res
=
1508 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1509 return itb_res
->tlb();
1514 InOrderCPU::getDTBPtr()
1516 CacheUnit
*dtb_res
=
1517 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1518 return dtb_res
->tlb();
1522 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1523 uint8_t *data
, unsigned size
, unsigned flags
)
1525 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1526 // you want to run w/out caches?
1527 CacheUnit
*cache_res
=
1528 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1530 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1534 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1535 Addr addr
, unsigned flags
, uint64_t *write_res
)
1537 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1538 // you want to run w/out caches?
1539 CacheUnit
*cache_res
=
1540 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1541 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);