2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "config/full_system.hh"
36 #include "config/the_isa.hh"
37 #include "cpu/activity.hh"
38 #include "cpu/base.hh"
39 #include "cpu/exetrace.hh"
40 #include "cpu/inorder/cpu.hh"
41 #include "cpu/inorder/first_stage.hh"
42 #include "cpu/inorder/inorder_dyn_inst.hh"
43 #include "cpu/inorder/pipeline_traits.hh"
44 #include "cpu/inorder/resource_pool.hh"
45 #include "cpu/inorder/resources/resource_list.hh"
46 #include "cpu/inorder/thread_context.hh"
47 #include "cpu/inorder/thread_state.hh"
48 #include "cpu/simple_thread.hh"
49 #include "cpu/thread_context.hh"
50 #include "mem/translating_port.hh"
51 #include "params/InOrderCPU.hh"
52 #include "sim/process.hh"
53 #include "sim/stat_control.hh"
56 #include "cpu/quiesce_event.hh"
57 #include "sim/system.hh"
60 #if THE_ISA == ALPHA_ISA
61 #include "arch/alpha/osfpal.hh"
65 using namespace TheISA
;
66 using namespace ThePipeline
;
68 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
69 : Event(CPU_Tick_Pri
), cpu(c
)
74 InOrderCPU::TickEvent::process()
81 InOrderCPU::TickEvent::description()
83 return "InOrderCPU tick event";
86 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
87 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
88 unsigned event_pri_offset
)
89 : Event(Event::Priority((unsigned int)CPU_Tick_Pri
+ event_pri_offset
)),
92 setEvent(e_type
, fault
, _tid
, inst
);
96 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
99 "ActivateNextReadyThread",
105 "SquashFromMemStall",
110 InOrderCPU::CPUEvent::process()
112 switch (cpuEventType
)
115 cpu
->activateThread(tid
);
118 case ActivateNextReadyThread
:
119 cpu
->activateNextReadyThread();
122 case DeactivateThread
:
123 cpu
->deactivateThread(tid
);
127 cpu
->haltThread(tid
);
131 cpu
->suspendThread(tid
);
134 case SquashFromMemStall
:
135 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
139 cpu
->trapCPU(fault
, tid
, inst
);
143 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
146 cpu
->cpuEventRemoveList
.push(this);
152 InOrderCPU::CPUEvent::description()
154 return "InOrderCPU event";
158 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
160 assert(!scheduled() || squashed());
161 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
165 InOrderCPU::CPUEvent::unscheduleEvent()
171 InOrderCPU::InOrderCPU(Params
*params
)
173 cpu_id(params
->cpu_id
),
177 stageWidth(params
->stageWidth
),
179 removeInstsThisCycle(false),
180 activityRec(params
->name
, NumStages
, 10, params
->activity
),
182 system(params
->system
),
183 physmem(system
->physmem
),
184 #endif // FULL_SYSTEM
190 deferRegistration(false/*params->deferRegistration*/),
191 stageTracing(params
->stageTracing
),
194 ThreadID active_threads
;
197 resPool
= new ResourcePool(this, params
);
199 // Resize for Multithreading CPUs
200 thread
.resize(numThreads
);
205 active_threads
= params
->workload
.size();
207 if (active_threads
> MaxThreads
) {
208 panic("Workload Size too large. Increase the 'MaxThreads'"
209 "in your InOrder implementation or "
210 "edit your workload size.");
214 if (active_threads
> 1) {
215 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
217 if (threadModel
== SMT
) {
218 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
219 } else if (threadModel
== SwitchOnCacheMiss
) {
220 DPRINTF(InOrderCPU
, "Setting Thread Model to "
221 "Switch On Cache Miss\n");
225 threadModel
= Single
;
232 // Bind the fetch & data ports from the resource pool.
233 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
234 if (fetchPortIdx
== 0) {
235 fatal("Unable to find port to fetch instructions from.\n");
238 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
239 if (dataPortIdx
== 0) {
240 fatal("Unable to find port for data.\n");
243 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
245 // SMT is not supported in FS mode yet.
246 assert(numThreads
== 1);
247 thread
[tid
] = new Thread(this, 0);
249 if (tid
< (ThreadID
)params
->workload
.size()) {
250 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
251 tid
, params
->workload
[tid
]->prog_fname
);
253 new Thread(this, tid
, params
->workload
[tid
]);
255 //Allocate Empty thread so M5 can use later
256 //when scheduling threads to CPU
257 Process
* dummy_proc
= params
->workload
[0];
258 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
261 // Eventually set this with parameters...
265 // Setup the TC that will serve as the interface to the threads/CPU.
266 InOrderThreadContext
*tc
= new InOrderThreadContext
;
268 tc
->thread
= thread
[tid
];
270 // Give the thread the TC.
271 thread
[tid
]->tc
= tc
;
272 thread
[tid
]->setFuncExeInst(0);
273 globalSeqNum
[tid
] = 1;
275 // Add the TC to the CPU's list of TC's.
276 this->threadContexts
.push_back(tc
);
279 // Initialize TimeBuffer Stage Queues
280 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
281 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
282 stageQueue
[stNum
]->id(stNum
);
286 // Set Up Pipeline Stages
287 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
289 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
291 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
293 pipelineStage
[stNum
]->setCPU(this);
294 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
295 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
297 // Take Care of 1st/Nth stages
299 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
300 if (stNum
< NumStages
- 1)
301 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
304 // Initialize thread specific variables
305 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
306 archRegDepMap
[tid
].setCPU(this);
308 nonSpecInstActive
[tid
] = false;
309 nonSpecSeqNum
[tid
] = 0;
311 squashSeqNum
[tid
] = MaxAddr
;
312 lastSquashCycle
[tid
] = 0;
314 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
315 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
318 isa
[tid
].expandForMultithreading(numThreads
, 1/*numVirtProcs*/);
320 // Define dummy instructions and resource requests to be used.
321 dummyInst
[tid
] = new InOrderDynInst(this,
327 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
330 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
331 dummyReqInst
->setSquashed();
332 dummyReqInst
->resetInstCount();
334 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
335 dummyBufferInst
->setSquashed();
336 dummyBufferInst
->resetInstCount();
338 endOfSkedIt
= skedCache
.end();
339 frontEndSked
= createFrontEndSked();
341 lastRunningCycle
= curTick();
343 // Reset CPU to reset state.
345 Fault resetFault
= new ResetFault();
346 resetFault
->invoke(tcBase());
352 // Schedule First Tick Event, CPU will reschedule itself from here on out.
353 scheduleTickEvent(0);
356 InOrderCPU::~InOrderCPU()
360 std::map
<SkedID
, ThePipeline::RSkedPtr
>::iterator sked_it
=
362 std::map
<SkedID
, ThePipeline::RSkedPtr
>::iterator sked_end
=
365 while (sked_it
!= sked_end
) {
366 delete (*sked_it
).second
;
372 std::map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
375 InOrderCPU::createFrontEndSked()
377 RSkedPtr res_sked
= new ResourceSked();
379 StageScheduler
F(res_sked
, stage_num
++);
380 StageScheduler
D(res_sked
, stage_num
++);
383 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
384 F
.needs(ICache
, FetchUnit::InitiateFetch
);
387 D
.needs(ICache
, FetchUnit::CompleteFetch
);
388 D
.needs(Decode
, DecodeUnit::DecodeInst
);
389 D
.needs(BPred
, BranchPredictor::PredictBranch
);
390 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
393 DPRINTF(SkedCache
, "Resource Sked created for instruction \"front_end\"\n");
399 InOrderCPU::createBackEndSked(DynInstPtr inst
)
401 RSkedPtr res_sked
= lookupSked(inst
);
402 if (res_sked
!= NULL
) {
403 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
407 res_sked
= new ResourceSked();
410 int stage_num
= ThePipeline::BackEndStartStage
;
411 StageScheduler
X(res_sked
, stage_num
++);
412 StageScheduler
M(res_sked
, stage_num
++);
413 StageScheduler
W(res_sked
, stage_num
++);
415 if (!inst
->staticInst
) {
416 warn_once("Static Instruction Object Not Set. Can't Create"
417 " Back End Schedule");
422 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
423 if (!idx
|| !inst
->isStore()) {
424 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
428 if ( inst
->isNonSpeculative() ) {
429 // skip execution of non speculative insts until later
430 } else if ( inst
->isMemRef() ) {
431 if ( inst
->isLoad() ) {
432 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
434 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
435 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
437 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
440 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
441 X
.needs(MDU
, MultDivUnit::EndMultDiv
);
445 if ( inst
->isLoad() ) {
446 M
.needs(DCache
, CacheUnit::InitiateReadData
);
447 } else if ( inst
->isStore() ) {
448 if ( inst
->numSrcRegs() >= 2 ) {
449 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
451 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
452 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
457 if ( inst
->isLoad() ) {
458 W
.needs(DCache
, CacheUnit::CompleteReadData
);
459 } else if ( inst
->isStore() ) {
460 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
463 if ( inst
->isNonSpeculative() ) {
464 if ( inst
->isMemRef() ) fatal("Non-Speculative Memory Instruction");
465 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
468 W
.needs(Grad
, GraduationUnit::GraduateInst
);
470 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
471 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
474 // Insert Back Schedule into our cache of
475 // resource schedules
476 addToSkedCache(inst
, res_sked
);
478 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
479 inst
->instName(), inst
->getMachInst());
486 InOrderCPU::regStats()
488 /* Register the Resource Pool's stats here.*/
491 /* Register for each Pipeline Stage */
492 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
493 pipelineStage
[stage_num
]->regStats();
496 /* Register any of the InOrderCPU's stats here.*/
498 .name(name() + ".instsPerContextSwitch")
499 .desc("Instructions Committed Per Context Switch")
500 .prereq(instsPerCtxtSwitch
);
503 .name(name() + ".contextSwitches")
504 .desc("Number of context switches");
507 .name(name() + ".comLoads")
508 .desc("Number of Load instructions committed");
511 .name(name() + ".comStores")
512 .desc("Number of Store instructions committed");
515 .name(name() + ".comBranches")
516 .desc("Number of Branches instructions committed");
519 .name(name() + ".comNops")
520 .desc("Number of Nop instructions committed");
523 .name(name() + ".comNonSpec")
524 .desc("Number of Non-Speculative instructions committed");
527 .name(name() + ".comInts")
528 .desc("Number of Integer instructions committed");
531 .name(name() + ".comFloats")
532 .desc("Number of Floating Point instructions committed");
535 .name(name() + ".timesIdled")
536 .desc("Number of times that the entire CPU went into an idle state and"
537 " unscheduled itself")
541 .name(name() + ".idleCycles")
542 .desc("Number of cycles cpu's stages were not processed");
545 .name(name() + ".runCycles")
546 .desc("Number of cycles cpu stages are processed.");
549 .name(name() + ".activity")
550 .desc("Percentage of cycles cpu is active")
552 activity
= (runCycles
/ numCycles
) * 100;
556 .name(name() + ".threadCycles")
557 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
560 .name(name() + ".smtCycles")
561 .desc("Total number of cycles that the CPU was in SMT-mode");
565 .name(name() + ".committedInsts")
566 .desc("Number of Instructions Simulated (Per-Thread)");
570 .name(name() + ".smtCommittedInsts")
571 .desc("Number of SMT Instructions Simulated (Per-Thread)");
574 .name(name() + ".committedInsts_total")
575 .desc("Number of Instructions Simulated (Total)");
578 .name(name() + ".cpi")
579 .desc("CPI: Cycles Per Instruction (Per-Thread)")
581 cpi
= numCycles
/ committedInsts
;
584 .name(name() + ".smt_cpi")
585 .desc("CPI: Total SMT-CPI")
587 smtCpi
= smtCycles
/ smtCommittedInsts
;
590 .name(name() + ".cpi_total")
591 .desc("CPI: Total CPI of All Threads")
593 totalCpi
= numCycles
/ totalCommittedInsts
;
596 .name(name() + ".ipc")
597 .desc("IPC: Instructions Per Cycle (Per-Thread)")
599 ipc
= committedInsts
/ numCycles
;
602 .name(name() + ".smt_ipc")
603 .desc("IPC: Total SMT-IPC")
605 smtIpc
= smtCommittedInsts
/ smtCycles
;
608 .name(name() + ".ipc_total")
609 .desc("IPC: Total IPC of All Threads")
611 totalIpc
= totalCommittedInsts
/ numCycles
;
620 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
624 bool pipes_idle
= true;
626 //Tick each of the stages
627 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
628 pipelineStage
[stNum
]->tick();
630 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
638 // Now advance the time buffers one tick
639 timeBuffer
.advance();
640 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
641 stageQueue
[sqNum
]->advance();
643 activityRec
.advance();
645 // Any squashed events, or insts then remove them now
646 cleanUpRemovedEvents();
647 cleanUpRemovedInsts();
649 // Re-schedule CPU for this cycle
650 if (!tickEvent
.scheduled()) {
651 if (_status
== SwitchedOut
) {
653 lastRunningCycle
= curTick();
654 } else if (!activityRec
.active()) {
655 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
656 lastRunningCycle
= curTick();
659 //Tick next_tick = curTick() + cycles(1);
660 //tickEvent.schedule(next_tick);
661 schedule(&tickEvent
, nextCycle(curTick() + 1));
662 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
663 nextCycle(curTick() + 1));
668 updateThreadPriority();
675 if (!deferRegistration
) {
676 registerThreadContexts();
679 // Set inSyscall so that the CPU doesn't squash when initially
680 // setting up registers.
681 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
682 thread
[tid
]->inSyscall
= true;
685 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
686 ThreadContext
*src_tc
= threadContexts
[tid
];
687 TheISA::initCPU(src_tc
, src_tc
->contextId());
692 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
693 thread
[tid
]->inSyscall
= false;
695 // Call Initializiation Routine for Resource Pool
702 for (int i
= 0; i
< numThreads
; i
++) {
703 isa
[i
].reset(coreType
, numThreads
,
704 1/*numVirtProcs*/, dynamic_cast<BaseCPU
*>(this));
709 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
711 return resPool
->getPort(if_name
, idx
);
716 InOrderCPU::hwrei(ThreadID tid
)
718 panic("hwrei: Unimplemented");
725 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
727 panic("simPalCheck: Unimplemented");
734 InOrderCPU::getInterrupts()
736 // Check if there are any outstanding interrupts
737 return interrupts
->getInterrupt(threadContexts
[0]);
742 InOrderCPU::processInterrupts(Fault interrupt
)
744 // Check for interrupts here. For now can copy the code that
745 // exists within isa_fullsys_traits.hh. Also assume that thread 0
746 // is the one that handles the interrupts.
747 // @todo: Possibly consolidate the interrupt checking code.
748 // @todo: Allow other threads to handle interrupts.
750 assert(interrupt
!= NoFault
);
751 interrupts
->updateIntrInfo(threadContexts
[0]);
753 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
755 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
756 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
761 InOrderCPU::updateMemPorts()
763 // Update all ThreadContext's memory ports (Functional/Virtual
765 ThreadID size
= thread
.size();
766 for (ThreadID i
= 0; i
< size
; ++i
)
767 thread
[i
]->connectMemPorts(thread
[i
]->getTC());
772 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
774 //@ Squash Pipeline during TRAP
775 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
779 InOrderCPU::trapCPU(Fault fault
, ThreadID tid
, DynInstPtr inst
)
781 fault
->invoke(tcBase(tid
), inst
->staticInst
);
785 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
787 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
792 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
795 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
797 // Squash all instructions in each stage including
798 // instruction that caused the squash (seq_num - 1)
799 // NOTE: The stage bandwidth needs to be cleared so thats why
800 // the stalling instruction is squashed as well. The stalled
801 // instruction is previously placed in another intermediate buffer
802 // while it's stall is being handled.
803 InstSeqNum squash_seq_num
= seq_num
- 1;
805 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
806 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
811 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
812 ThreadID tid
, DynInstPtr inst
,
813 unsigned delay
, unsigned event_pri_offset
)
815 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
818 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
820 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
821 eventNames
[c_event
], curTick() + delay
, tid
);
822 schedule(cpu_event
, sked_tick
);
824 cpu_event
->process();
825 cpuEventRemoveList
.push(cpu_event
);
828 // Broadcast event to the Resource Pool
829 // Need to reset tid just in case this is a dummy instruction
831 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
835 InOrderCPU::isThreadActive(ThreadID tid
)
837 list
<ThreadID
>::iterator isActive
=
838 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
840 return (isActive
!= activeThreads
.end());
844 InOrderCPU::isThreadReady(ThreadID tid
)
846 list
<ThreadID
>::iterator isReady
=
847 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
849 return (isReady
!= readyThreads
.end());
853 InOrderCPU::isThreadSuspended(ThreadID tid
)
855 list
<ThreadID
>::iterator isSuspended
=
856 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
858 return (isSuspended
!= suspendedThreads
.end());
862 InOrderCPU::activateNextReadyThread()
864 if (readyThreads
.size() >= 1) {
865 ThreadID ready_tid
= readyThreads
.front();
867 // Activate in Pipeline
868 activateThread(ready_tid
);
870 // Activate in Resource Pool
871 resPool
->activateAll(ready_tid
);
873 list
<ThreadID
>::iterator ready_it
=
874 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
875 readyThreads
.erase(ready_it
);
878 "Attempting to activate new thread, but No Ready Threads to"
881 "Unable to switch to next active thread.\n");
886 InOrderCPU::activateThread(ThreadID tid
)
888 if (isThreadSuspended(tid
)) {
890 "Removing [tid:%i] from suspended threads list.\n", tid
);
892 list
<ThreadID
>::iterator susp_it
=
893 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
895 suspendedThreads
.erase(susp_it
);
898 if (threadModel
== SwitchOnCacheMiss
&&
899 numActiveThreads() == 1) {
901 "Ignoring activation of [tid:%i], since [tid:%i] is "
902 "already running.\n", tid
, activeThreadId());
904 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
907 readyThreads
.push_back(tid
);
909 } else if (!isThreadActive(tid
)) {
911 "Adding [tid:%i] to active threads list.\n", tid
);
912 activeThreads
.push_back(tid
);
914 activateThreadInPipeline(tid
);
916 thread
[tid
]->lastActivate
= curTick();
918 tcBase(tid
)->setStatus(ThreadContext::Active
);
927 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
929 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
930 pipelineStage
[stNum
]->activateThread(tid
);
935 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
937 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
939 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
941 // Be sure to signal that there's some activity so the CPU doesn't
942 // deschedule itself.
943 activityRec
.activity();
949 InOrderCPU::deactivateThread(ThreadID tid
)
951 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
953 if (isThreadActive(tid
)) {
954 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
956 list
<ThreadID
>::iterator thread_it
=
957 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
959 removePipelineStalls(*thread_it
);
961 activeThreads
.erase(thread_it
);
963 // Ideally, this should be triggered from the
964 // suspendContext/Thread functions
965 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
968 assert(!isThreadActive(tid
));
972 InOrderCPU::removePipelineStalls(ThreadID tid
)
974 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
977 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
978 pipelineStage
[stNum
]->removeStalls(tid
);
984 InOrderCPU::updateThreadPriority()
986 if (activeThreads
.size() > 1)
988 //DEFAULT TO ROUND ROBIN SCHEME
989 //e.g. Move highest priority to end of thread list
990 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
991 list
<ThreadID
>::iterator list_end
= activeThreads
.end();
993 unsigned high_thread
= *list_begin
;
995 activeThreads
.erase(list_begin
);
997 activeThreads
.push_back(high_thread
);
1002 InOrderCPU::tickThreadStats()
1004 /** Keep track of cycles that each thread is active */
1005 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1006 while (thread_it
!= activeThreads
.end()) {
1007 threadCycles
[*thread_it
]++;
1011 // Keep track of cycles where SMT is active
1012 if (activeThreads
.size() > 1) {
1018 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1020 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1023 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1025 // Be sure to signal that there's some activity so the CPU doesn't
1026 // deschedule itself.
1027 activityRec
.activity();
1033 InOrderCPU::activateNextReadyContext(int delay
)
1035 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1037 // NOTE: Add 5 to the event priority so that we always activate
1038 // threads after we've finished deactivating, squashing,etc.
1040 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1043 // Be sure to signal that there's some activity so the CPU doesn't
1044 // deschedule itself.
1045 activityRec
.activity();
1051 InOrderCPU::haltContext(ThreadID tid
, int delay
)
1053 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1055 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1057 activityRec
.activity();
1061 InOrderCPU::haltThread(ThreadID tid
)
1063 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1064 deactivateThread(tid
);
1065 squashThreadInPipeline(tid
);
1066 haltedThreads
.push_back(tid
);
1068 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1070 if (threadModel
== SwitchOnCacheMiss
) {
1071 activateNextReadyContext();
1076 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
1078 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1082 InOrderCPU::suspendThread(ThreadID tid
)
1084 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1086 deactivateThread(tid
);
1087 suspendedThreads
.push_back(tid
);
1088 thread
[tid
]->lastSuspend
= curTick();
1090 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1094 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1096 //Squash all instructions in each stage
1097 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1098 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1103 InOrderCPU::getPipeStage(int stage_num
)
1105 return pipelineStage
[stage_num
];
1109 InOrderCPU::readIntReg(int reg_idx
, ThreadID tid
)
1111 return intRegs
[tid
][reg_idx
];
1115 InOrderCPU::readFloatReg(int reg_idx
, ThreadID tid
)
1117 return floatRegs
.f
[tid
][reg_idx
];
1121 InOrderCPU::readFloatRegBits(int reg_idx
, ThreadID tid
)
1123 return floatRegs
.i
[tid
][reg_idx
];
1127 InOrderCPU::setIntReg(int reg_idx
, uint64_t val
, ThreadID tid
)
1129 intRegs
[tid
][reg_idx
] = val
;
1134 InOrderCPU::setFloatReg(int reg_idx
, FloatReg val
, ThreadID tid
)
1136 floatRegs
.f
[tid
][reg_idx
] = val
;
1141 InOrderCPU::setFloatRegBits(int reg_idx
, FloatRegBits val
, ThreadID tid
)
1143 floatRegs
.i
[tid
][reg_idx
] = val
;
1147 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1149 // If Default value is set, then retrieve target thread
1150 if (tid
== InvalidThreadID
) {
1151 tid
= TheISA::getTargetThread(tcBase(tid
));
1154 if (reg_idx
< FP_Base_DepTag
) {
1155 // Integer Register File
1156 return readIntReg(reg_idx
, tid
);
1157 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1158 // Float Register File
1159 reg_idx
-= FP_Base_DepTag
;
1160 return readFloatRegBits(reg_idx
, tid
);
1162 reg_idx
-= Ctrl_Base_DepTag
;
1163 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1167 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1170 // If Default value is set, then retrieve target thread
1171 if (tid
== InvalidThreadID
) {
1172 tid
= TheISA::getTargetThread(tcBase(tid
));
1175 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1176 setIntReg(reg_idx
, val
, tid
);
1177 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1178 reg_idx
-= FP_Base_DepTag
;
1179 setFloatRegBits(reg_idx
, val
, tid
);
1181 reg_idx
-= Ctrl_Base_DepTag
;
1182 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1187 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1189 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1193 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1195 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1199 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1201 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1205 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1207 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1212 InOrderCPU::addInst(DynInstPtr
&inst
)
1214 ThreadID tid
= inst
->readTid();
1216 instList
[tid
].push_back(inst
);
1218 return --(instList
[tid
].end());
1222 InOrderCPU::updateContextSwitchStats()
1224 // Set Average Stat Here, then reset to 0
1225 instsPerCtxtSwitch
= instsPerSwitch
;
1231 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1233 // Set the CPU's PCs - This contributes to the precise state of the CPU
1234 // which can be used when restoring a thread to the CPU after after any
1235 // type of context switching activity (fork, exception, etc.)
1236 pcState(inst
->pcState(), tid
);
1238 if (inst
->isControl()) {
1239 thread
[tid
]->lastGradIsBranch
= true;
1240 thread
[tid
]->lastBranchPC
= inst
->pcState();
1241 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1243 thread
[tid
]->lastGradIsBranch
= false;
1247 // Finalize Trace Data For Instruction
1248 if (inst
->traceData
) {
1249 //inst->traceData->setCycle(curTick());
1250 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1251 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1252 inst
->traceData
->dump();
1253 delete inst
->traceData
;
1254 inst
->traceData
= NULL
;
1257 // Increment active thread's instruction count
1260 // Increment thread-state's instruction count
1261 thread
[tid
]->numInst
++;
1263 // Increment thread-state's instruction stats
1264 thread
[tid
]->numInsts
++;
1266 // Count committed insts per thread stats
1267 committedInsts
[tid
]++;
1269 // Count total insts committed stat
1270 totalCommittedInsts
++;
1272 // Count SMT-committed insts per thread stat
1273 if (numActiveThreads() > 1) {
1274 smtCommittedInsts
[tid
]++;
1277 // Instruction-Mix Stats
1278 if (inst
->isLoad()) {
1280 } else if (inst
->isStore()) {
1282 } else if (inst
->isControl()) {
1284 } else if (inst
->isNop()) {
1286 } else if (inst
->isNonSpeculative()) {
1288 } else if (inst
->isInteger()) {
1290 } else if (inst
->isFloating()) {
1294 // Check for instruction-count-based events.
1295 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1297 // Broadcast to other resources an instruction
1298 // has been completed
1299 resPool
->scheduleEvent((CPUEventType
)ResourcePool::InstGraduated
, inst
,
1302 // Finally, remove instruction from CPU
1306 // currently unused function, but substitute repetitive code w/this function
1309 InOrderCPU::addToRemoveList(DynInstPtr
&inst
)
1311 removeInstsThisCycle
= true;
1312 if (!inst
->isRemoveList()) {
1313 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1314 "[sn:%lli] to remove list\n",
1315 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1316 inst
->setRemoveList();
1317 removeList
.push(inst
->getInstListIt());
1319 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1320 "[sn:%lli], already remove list\n",
1321 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1327 InOrderCPU::removeInst(DynInstPtr
&inst
)
1329 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1331 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1333 removeInstsThisCycle
= true;
1335 // Remove the instruction.
1336 if (!inst
->isRemoveList()) {
1337 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1338 "[sn:%lli] to remove list\n",
1339 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1340 inst
->setRemoveList();
1341 removeList
.push(inst
->getInstListIt());
1343 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1344 "[sn:%lli], already on remove list\n",
1345 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1351 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1353 //assert(!instList[tid].empty());
1355 removeInstsThisCycle
= true;
1357 ListIt inst_iter
= instList
[tid
].end();
1361 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1362 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1363 tid
, seq_num
, (*inst_iter
)->seqNum
);
1365 while ((*inst_iter
)->seqNum
> seq_num
) {
1367 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1369 squashInstIt(inst_iter
, tid
);
1380 InOrderCPU::squashInstIt(const ListIt
&instIt
, ThreadID tid
)
1382 if ((*instIt
)->threadNumber
== tid
) {
1383 DPRINTF(InOrderCPU
, "Squashing instruction, "
1384 "[tid:%i] [sn:%lli] PC %s\n",
1385 (*instIt
)->threadNumber
,
1387 (*instIt
)->pcState());
1389 (*instIt
)->setSquashed();
1391 if (!(*instIt
)->isRemoveList()) {
1392 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1393 "[sn:%lli] to remove list\n",
1394 (*instIt
)->threadNumber
, (*instIt
)->pcState(),
1396 (*instIt
)->setRemoveList();
1397 removeList
.push(instIt
);
1399 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1400 " PC %s [sn:%lli], already on remove list\n",
1401 (*instIt
)->threadNumber
, (*instIt
)->pcState(),
1411 InOrderCPU::cleanUpRemovedInsts()
1413 while (!removeList
.empty()) {
1414 DPRINTF(InOrderCPU
, "Removing instruction, "
1415 "[tid:%i] [sn:%lli] PC %s\n",
1416 (*removeList
.front())->threadNumber
,
1417 (*removeList
.front())->seqNum
,
1418 (*removeList
.front())->pcState());
1420 DynInstPtr inst
= *removeList
.front();
1421 ThreadID tid
= inst
->threadNumber
;
1423 // Remove From Register Dependency Map, If Necessary
1424 archRegDepMap
[(*removeList
.front())->threadNumber
].
1425 remove((*removeList
.front()));
1428 // Clear if Non-Speculative
1429 if (inst
->staticInst
&&
1430 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1431 nonSpecInstActive
[tid
] == true) {
1432 nonSpecInstActive
[tid
] = false;
1435 instList
[tid
].erase(removeList
.front());
1440 removeInstsThisCycle
= false;
1444 InOrderCPU::cleanUpRemovedEvents()
1446 while (!cpuEventRemoveList
.empty()) {
1447 Event
*cpu_event
= cpuEventRemoveList
.front();
1448 cpuEventRemoveList
.pop();
1455 InOrderCPU::dumpInsts()
1459 ListIt inst_list_it
= instList
[0].begin();
1461 cprintf("Dumping Instruction List\n");
1463 while (inst_list_it
!= instList
[0].end()) {
1464 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1466 num
, (*inst_list_it
)->pcState(),
1467 (*inst_list_it
)->threadNumber
,
1468 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1469 (*inst_list_it
)->isSquashed());
1476 InOrderCPU::wakeCPU()
1478 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1479 DPRINTF(Activity
, "CPU already running.\n");
1483 DPRINTF(Activity
, "Waking up CPU\n");
1485 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1487 idleCycles
+= extra_cycles
;
1488 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1489 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1492 numCycles
+= extra_cycles
;
1494 schedule(&tickEvent
, nextCycle(curTick()));
1500 InOrderCPU::wakeup()
1502 if (thread
[0]->status() != ThreadContext::Suspended
)
1507 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1508 threadContexts
[0]->activate();
1514 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1516 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1518 DPRINTF(Activity
,"Activity: syscall() called.\n");
1520 // Temporarily increase this by one to account for the syscall
1522 ++(this->thread
[tid
]->funcExeInst
);
1524 // Execute the actual syscall.
1525 this->thread
[tid
]->syscall(callnum
);
1527 // Decrease funcExeInst by one as the normal commit will handle
1529 --(this->thread
[tid
]->funcExeInst
);
1531 // Clear Non-Speculative Block Variable
1532 nonSpecInstActive
[tid
] = false;
1537 InOrderCPU::getITBPtr()
1539 CacheUnit
*itb_res
=
1540 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1541 return itb_res
->tlb();
1546 InOrderCPU::getDTBPtr()
1548 CacheUnit
*dtb_res
=
1549 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1550 return dtb_res
->tlb();
1554 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1555 uint8_t *data
, unsigned size
, unsigned flags
)
1557 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1558 // you want to run w/out caches?
1559 CacheUnit
*cache_res
=
1560 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1562 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1566 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1567 Addr addr
, unsigned flags
, uint64_t *write_res
)
1569 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1570 // you want to run w/out caches?
1571 CacheUnit
*cache_res
=
1572 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1573 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);