2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "base/bigint.hh"
36 #include "config/full_system.hh"
37 #include "config/the_isa.hh"
38 #include "cpu/inorder/resources/resource_list.hh"
39 #include "cpu/inorder/cpu.hh"
40 #include "cpu/inorder/first_stage.hh"
41 #include "cpu/inorder/inorder_dyn_inst.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/resource_pool.hh"
44 #include "cpu/inorder/thread_context.hh"
45 #include "cpu/inorder/thread_state.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/base.hh"
48 #include "cpu/exetrace.hh"
49 #include "cpu/simple_thread.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/Activity.hh"
52 #include "debug/InOrderCPU.hh"
53 #include "debug/RefCount.hh"
54 #include "debug/SkedCache.hh"
55 #include "debug/Quiesce.hh"
56 #include "mem/translating_port.hh"
57 #include "params/InOrderCPU.hh"
58 #include "sim/process.hh"
59 #include "sim/stat_control.hh"
62 #include "cpu/quiesce_event.hh"
63 #include "sim/system.hh"
66 #if THE_ISA == ALPHA_ISA
67 #include "arch/alpha/osfpal.hh"
71 using namespace TheISA
;
72 using namespace ThePipeline
;
74 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
75 : Event(CPU_Tick_Pri
), cpu(c
)
80 InOrderCPU::TickEvent::process()
87 InOrderCPU::TickEvent::description()
89 return "InOrderCPU tick event";
92 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
93 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
94 CPUEventPri event_pri
)
95 : Event(event_pri
), cpu(_cpu
)
97 setEvent(e_type
, fault
, _tid
, inst
);
101 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
104 "ActivateNextReadyThread",
110 "SquashFromMemStall",
115 InOrderCPU::CPUEvent::process()
117 switch (cpuEventType
)
120 cpu
->activateThread(tid
);
121 cpu
->resPool
->activateThread(tid
);
124 case ActivateNextReadyThread
:
125 cpu
->activateNextReadyThread();
128 case DeactivateThread
:
129 cpu
->deactivateThread(tid
);
130 cpu
->resPool
->deactivateThread(tid
);
134 cpu
->haltThread(tid
);
135 cpu
->resPool
->deactivateThread(tid
);
139 cpu
->suspendThread(tid
);
140 cpu
->resPool
->suspendThread(tid
);
143 case SquashFromMemStall
:
144 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
145 cpu
->resPool
->squashDueToMemStall(inst
, inst
->squashingStage
,
150 DPRINTF(InOrderCPU
, "Trapping CPU\n");
151 cpu
->trap(fault
, tid
, inst
);
152 cpu
->resPool
->trap(fault
, tid
, inst
);
153 cpu
->trapPending
[tid
] = false;
158 cpu
->syscall(inst
->syscallNum
, tid
);
159 cpu
->resPool
->trap(fault
, tid
, inst
);
163 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
166 cpu
->cpuEventRemoveList
.push(this);
172 InOrderCPU::CPUEvent::description()
174 return "InOrderCPU event";
178 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
180 assert(!scheduled() || squashed());
181 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
185 InOrderCPU::CPUEvent::unscheduleEvent()
191 InOrderCPU::InOrderCPU(Params
*params
)
193 cpu_id(params
->cpu_id
),
197 stageWidth(params
->stageWidth
),
199 removeInstsThisCycle(false),
200 activityRec(params
->name
, NumStages
, 10, params
->activity
),
202 system(params
->system
),
203 #endif // FULL_SYSTEM
209 deferRegistration(false/*params->deferRegistration*/),
210 stageTracing(params
->stageTracing
),
216 resPool
= new ResourcePool(this, params
);
218 // Resize for Multithreading CPUs
219 thread
.resize(numThreads
);
222 ThreadID active_threads
= params
->workload
.size();
224 if (active_threads
> MaxThreads
) {
225 panic("Workload Size too large. Increase the 'MaxThreads'"
226 "in your InOrder implementation or "
227 "edit your workload size.");
231 if (active_threads
> 1) {
232 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
234 if (threadModel
== SMT
) {
235 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
236 } else if (threadModel
== SwitchOnCacheMiss
) {
237 DPRINTF(InOrderCPU
, "Setting Thread Model to "
238 "Switch On Cache Miss\n");
242 threadModel
= Single
;
249 // Bind the fetch & data ports from the resource pool.
250 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
251 if (fetchPortIdx
== 0) {
252 fatal("Unable to find port to fetch instructions from.\n");
255 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
256 if (dataPortIdx
== 0) {
257 fatal("Unable to find port for data.\n");
260 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
262 lastCommittedPC
[tid
].set(0);
265 // SMT is not supported in FS mode yet.
266 assert(numThreads
== 1);
267 thread
[tid
] = new Thread(this, 0);
269 if (tid
< (ThreadID
)params
->workload
.size()) {
270 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
271 tid
, params
->workload
[tid
]->prog_fname
);
273 new Thread(this, tid
, params
->workload
[tid
]);
275 //Allocate Empty thread so M5 can use later
276 //when scheduling threads to CPU
277 Process
* dummy_proc
= params
->workload
[0];
278 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
281 // Eventually set this with parameters...
285 // Setup the TC that will serve as the interface to the threads/CPU.
286 InOrderThreadContext
*tc
= new InOrderThreadContext
;
288 tc
->thread
= thread
[tid
];
291 // Setup quiesce event.
292 this->thread
[tid
]->quiesceEvent
= new EndQuiesceEvent(tc
);
295 // Give the thread the TC.
296 thread
[tid
]->tc
= tc
;
297 thread
[tid
]->setFuncExeInst(0);
298 globalSeqNum
[tid
] = 1;
300 // Add the TC to the CPU's list of TC's.
301 this->threadContexts
.push_back(tc
);
304 // Initialize TimeBuffer Stage Queues
305 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
306 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
307 stageQueue
[stNum
]->id(stNum
);
311 // Set Up Pipeline Stages
312 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
314 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
316 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
318 pipelineStage
[stNum
]->setCPU(this);
319 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
320 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
322 // Take Care of 1st/Nth stages
324 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
325 if (stNum
< NumStages
- 1)
326 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
329 // Initialize thread specific variables
330 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
331 archRegDepMap
[tid
].setCPU(this);
333 nonSpecInstActive
[tid
] = false;
334 nonSpecSeqNum
[tid
] = 0;
336 squashSeqNum
[tid
] = MaxAddr
;
337 lastSquashCycle
[tid
] = 0;
339 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
340 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
343 // Define dummy instructions and resource requests to be used.
344 dummyInst
[tid
] = new InOrderDynInst(this,
350 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
353 // Use this dummy inst to force squashing behind every instruction
355 dummyTrapInst
[tid
] = new InOrderDynInst(this, NULL
, 0, 0, 0);
356 dummyTrapInst
[tid
]->seqNum
= 0;
357 dummyTrapInst
[tid
]->squashSeqNum
= 0;
358 dummyTrapInst
[tid
]->setTid(tid
);
361 trapPending
[tid
] = false;
365 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
366 dummyReqInst
->setSquashed();
367 dummyReqInst
->resetInstCount();
369 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
370 dummyBufferInst
->setSquashed();
371 dummyBufferInst
->resetInstCount();
373 endOfSkedIt
= skedCache
.end();
374 frontEndSked
= createFrontEndSked();
375 faultSked
= createFaultSked();
377 lastRunningCycle
= curTick();
382 // Schedule First Tick Event, CPU will reschedule itself from here on out.
383 scheduleTickEvent(0);
386 InOrderCPU::~InOrderCPU()
390 SkedCacheIt sked_it
= skedCache
.begin();
391 SkedCacheIt sked_end
= skedCache
.end();
393 while (sked_it
!= sked_end
) {
394 delete (*sked_it
).second
;
400 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
403 InOrderCPU::createFrontEndSked()
405 RSkedPtr res_sked
= new ResourceSked();
407 StageScheduler
F(res_sked
, stage_num
++);
408 StageScheduler
D(res_sked
, stage_num
++);
411 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
412 F
.needs(ICache
, FetchUnit::InitiateFetch
);
415 D
.needs(ICache
, FetchUnit::CompleteFetch
);
416 D
.needs(Decode
, DecodeUnit::DecodeInst
);
417 D
.needs(BPred
, BranchPredictor::PredictBranch
);
418 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
421 DPRINTF(SkedCache
, "Resource Sked created for instruction Front End\n");
427 InOrderCPU::createFaultSked()
429 RSkedPtr res_sked
= new ResourceSked();
430 StageScheduler
W(res_sked
, NumStages
- 1);
431 W
.needs(Grad
, GraduationUnit::CheckFault
);
432 DPRINTF(SkedCache
, "Resource Sked created for instruction Faults\n");
437 InOrderCPU::createBackEndSked(DynInstPtr inst
)
439 RSkedPtr res_sked
= lookupSked(inst
);
440 if (res_sked
!= NULL
) {
441 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
445 res_sked
= new ResourceSked();
448 int stage_num
= ThePipeline::BackEndStartStage
;
449 StageScheduler
X(res_sked
, stage_num
++);
450 StageScheduler
M(res_sked
, stage_num
++);
451 StageScheduler
W(res_sked
, stage_num
++);
453 if (!inst
->staticInst
) {
454 warn_once("Static Instruction Object Not Set. Can't Create"
455 " Back End Schedule");
460 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
461 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
462 if (!idx
|| !inst
->isStore()) {
463 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
467 //@todo: schedule non-spec insts to operate on this cycle
468 // as long as all previous insts are done
469 if ( inst
->isNonSpeculative() ) {
470 // skip execution of non speculative insts until later
471 } else if ( inst
->isMemRef() ) {
472 if ( inst
->isLoad() ) {
473 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
475 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
476 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
478 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
482 if (!inst
->isNonSpeculative()) {
483 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
484 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
487 if ( inst
->isLoad() ) {
488 M
.needs(DCache
, CacheUnit::InitiateReadData
);
490 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
491 } else if ( inst
->isStore() ) {
492 for (int i
= 1; i
< inst
->numSrcRegs(); i
++ ) {
493 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, i
);
495 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
496 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
498 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
503 if (!inst
->isNonSpeculative()) {
504 if ( inst
->isLoad() ) {
505 W
.needs(DCache
, CacheUnit::CompleteReadData
);
507 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
508 } else if ( inst
->isStore() ) {
509 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
511 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
514 // Finally, Execute Speculative Data
515 if (inst
->isMemRef()) {
516 if (inst
->isLoad()) {
517 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
518 W
.needs(DCache
, CacheUnit::InitiateReadData
);
520 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
521 W
.needs(DCache
, CacheUnit::CompleteReadData
);
523 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
524 } else if (inst
->isStore()) {
525 if ( inst
->numSrcRegs() >= 2 ) {
526 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
528 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
529 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
531 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
532 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
534 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
537 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
541 W
.needs(Grad
, GraduationUnit::CheckFault
);
543 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
544 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
547 if (inst
->isControl())
548 W
.needs(BPred
, BranchPredictor::UpdatePredictor
);
550 W
.needs(Grad
, GraduationUnit::GraduateInst
);
552 // Insert Back Schedule into our cache of
553 // resource schedules
554 addToSkedCache(inst
, res_sked
);
556 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
557 inst
->instName(), inst
->getMachInst());
564 InOrderCPU::regStats()
566 /* Register the Resource Pool's stats here.*/
569 /* Register for each Pipeline Stage */
570 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
571 pipelineStage
[stage_num
]->regStats();
574 /* Register any of the InOrderCPU's stats here.*/
576 .name(name() + ".instsPerContextSwitch")
577 .desc("Instructions Committed Per Context Switch")
578 .prereq(instsPerCtxtSwitch
);
581 .name(name() + ".contextSwitches")
582 .desc("Number of context switches");
585 .name(name() + ".comLoads")
586 .desc("Number of Load instructions committed");
589 .name(name() + ".comStores")
590 .desc("Number of Store instructions committed");
593 .name(name() + ".comBranches")
594 .desc("Number of Branches instructions committed");
597 .name(name() + ".comNops")
598 .desc("Number of Nop instructions committed");
601 .name(name() + ".comNonSpec")
602 .desc("Number of Non-Speculative instructions committed");
605 .name(name() + ".comInts")
606 .desc("Number of Integer instructions committed");
609 .name(name() + ".comFloats")
610 .desc("Number of Floating Point instructions committed");
613 .name(name() + ".timesIdled")
614 .desc("Number of times that the entire CPU went into an idle state and"
615 " unscheduled itself")
619 .name(name() + ".idleCycles")
620 .desc("Number of cycles cpu's stages were not processed");
623 .name(name() + ".runCycles")
624 .desc("Number of cycles cpu stages are processed.");
627 .name(name() + ".activity")
628 .desc("Percentage of cycles cpu is active")
630 activity
= (runCycles
/ numCycles
) * 100;
634 .name(name() + ".threadCycles")
635 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
638 .name(name() + ".smtCycles")
639 .desc("Total number of cycles that the CPU was in SMT-mode");
643 .name(name() + ".committedInsts")
644 .desc("Number of Instructions Simulated (Per-Thread)");
648 .name(name() + ".smtCommittedInsts")
649 .desc("Number of SMT Instructions Simulated (Per-Thread)");
652 .name(name() + ".committedInsts_total")
653 .desc("Number of Instructions Simulated (Total)");
656 .name(name() + ".cpi")
657 .desc("CPI: Cycles Per Instruction (Per-Thread)")
659 cpi
= numCycles
/ committedInsts
;
662 .name(name() + ".smt_cpi")
663 .desc("CPI: Total SMT-CPI")
665 smtCpi
= smtCycles
/ smtCommittedInsts
;
668 .name(name() + ".cpi_total")
669 .desc("CPI: Total CPI of All Threads")
671 totalCpi
= numCycles
/ totalCommittedInsts
;
674 .name(name() + ".ipc")
675 .desc("IPC: Instructions Per Cycle (Per-Thread)")
677 ipc
= committedInsts
/ numCycles
;
680 .name(name() + ".smt_ipc")
681 .desc("IPC: Total SMT-IPC")
683 smtIpc
= smtCommittedInsts
/ smtCycles
;
686 .name(name() + ".ipc_total")
687 .desc("IPC: Total IPC of All Threads")
689 totalIpc
= totalCommittedInsts
/ numCycles
;
698 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
703 checkForInterrupts();
706 bool pipes_idle
= true;
707 //Tick each of the stages
708 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
709 pipelineStage
[stNum
]->tick();
711 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
719 // Now advance the time buffers one tick
720 timeBuffer
.advance();
721 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
722 stageQueue
[sqNum
]->advance();
724 activityRec
.advance();
726 // Any squashed events, or insts then remove them now
727 cleanUpRemovedEvents();
728 cleanUpRemovedInsts();
730 // Re-schedule CPU for this cycle
731 if (!tickEvent
.scheduled()) {
732 if (_status
== SwitchedOut
) {
734 lastRunningCycle
= curTick();
735 } else if (!activityRec
.active()) {
736 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
737 lastRunningCycle
= curTick();
740 //Tick next_tick = curTick() + cycles(1);
741 //tickEvent.schedule(next_tick);
742 schedule(&tickEvent
, nextCycle(curTick() + 1));
743 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
744 nextCycle(curTick() + 1));
749 updateThreadPriority();
756 if (!deferRegistration
) {
757 registerThreadContexts();
760 // Set inSyscall so that the CPU doesn't squash when initially
761 // setting up registers.
762 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
763 thread
[tid
]->inSyscall
= true;
766 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
767 ThreadContext
*src_tc
= threadContexts
[tid
];
768 TheISA::initCPU(src_tc
, src_tc
->contextId());
773 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
774 thread
[tid
]->inSyscall
= false;
776 // Call Initializiation Routine for Resource Pool
781 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
783 return resPool
->getPort(if_name
, idx
);
788 InOrderCPU::hwrei(ThreadID tid
)
790 #if THE_ISA == ALPHA_ISA
791 // Need to clear the lock flag upon returning from an interrupt.
792 setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG
, false, tid
);
794 thread
[tid
]->kernelStats
->hwrei();
795 // FIXME: XXX check for interrupts? XXX
803 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
805 #if THE_ISA == ALPHA_ISA
806 if (this->thread
[tid
]->kernelStats
)
807 this->thread
[tid
]->kernelStats
->callpal(palFunc
,
808 this->threadContexts
[tid
]);
813 if (--System::numSystemsRunning
== 0)
814 exitSimLoop("all cpus halted");
819 if (this->system
->breakpoint())
828 InOrderCPU::checkForInterrupts()
830 for (int i
= 0; i
< threadContexts
.size(); i
++) {
831 ThreadContext
*tc
= threadContexts
[i
];
833 if (interrupts
->checkInterrupts(tc
)) {
834 Fault interrupt
= interrupts
->getInterrupt(tc
);
836 if (interrupt
!= NoFault
) {
837 DPRINTF(Interrupt
, "Processing Intterupt for [tid:%i].\n",
840 ThreadID tid
= tc
->threadId();
841 interrupts
->updateIntrInfo(tc
);
843 // Squash from Last Stage in Pipeline
844 unsigned last_stage
= NumStages
- 1;
845 dummyTrapInst
[tid
]->squashingStage
= last_stage
;
846 pipelineStage
[last_stage
]->setupSquash(dummyTrapInst
[tid
],
849 // By default, setupSquash will always squash from stage + 1
850 pipelineStage
[BackEndStartStage
- 1]->setupSquash(dummyTrapInst
[tid
],
853 // Schedule Squash Through-out Resource Pool
854 resPool
->scheduleEvent(
855 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
,
856 dummyTrapInst
[tid
], 0);
858 // Finally, Setup Trap to happen at end of cycle
859 trapContext(interrupt
, tid
, dummyTrapInst
[tid
]);
866 InOrderCPU::getInterrupts()
868 // Check if there are any outstanding interrupts
869 return interrupts
->getInterrupt(threadContexts
[0]);
874 InOrderCPU::processInterrupts(Fault interrupt
)
876 // Check for interrupts here. For now can copy the code that
877 // exists within isa_fullsys_traits.hh. Also assume that thread 0
878 // is the one that handles the interrupts.
879 // @todo: Possibly consolidate the interrupt checking code.
880 // @todo: Allow other threads to handle interrupts.
882 assert(interrupt
!= NoFault
);
883 interrupts
->updateIntrInfo(threadContexts
[0]);
885 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
887 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
888 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
893 InOrderCPU::updateMemPorts()
895 // Update all ThreadContext's memory ports (Functional/Virtual
897 ThreadID size
= thread
.size();
898 for (ThreadID i
= 0; i
< size
; ++i
)
899 thread
[i
]->connectMemPorts(thread
[i
]->getTC());
904 InOrderCPU::trapContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
906 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
907 trapPending
[tid
] = true;
911 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
913 fault
->invoke(tcBase(tid
), inst
->staticInst
);
914 removePipelineStalls(tid
);
918 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
920 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
925 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
928 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
930 // Squash all instructions in each stage including
931 // instruction that caused the squash (seq_num - 1)
932 // NOTE: The stage bandwidth needs to be cleared so thats why
933 // the stalling instruction is squashed as well. The stalled
934 // instruction is previously placed in another intermediate buffer
935 // while it's stall is being handled.
936 InstSeqNum squash_seq_num
= seq_num
- 1;
938 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
939 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
944 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
945 ThreadID tid
, DynInstPtr inst
,
946 unsigned delay
, CPUEventPri event_pri
)
948 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
951 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
953 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
954 eventNames
[c_event
], curTick() + delay
, tid
);
955 schedule(cpu_event
, sked_tick
);
957 cpu_event
->process();
958 cpuEventRemoveList
.push(cpu_event
);
961 // Broadcast event to the Resource Pool
962 // Need to reset tid just in case this is a dummy instruction
964 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
968 InOrderCPU::isThreadActive(ThreadID tid
)
970 list
<ThreadID
>::iterator isActive
=
971 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
973 return (isActive
!= activeThreads
.end());
977 InOrderCPU::isThreadReady(ThreadID tid
)
979 list
<ThreadID
>::iterator isReady
=
980 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
982 return (isReady
!= readyThreads
.end());
986 InOrderCPU::isThreadSuspended(ThreadID tid
)
988 list
<ThreadID
>::iterator isSuspended
=
989 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
991 return (isSuspended
!= suspendedThreads
.end());
995 InOrderCPU::activateNextReadyThread()
997 if (readyThreads
.size() >= 1) {
998 ThreadID ready_tid
= readyThreads
.front();
1000 // Activate in Pipeline
1001 activateThread(ready_tid
);
1003 // Activate in Resource Pool
1004 resPool
->activateThread(ready_tid
);
1006 list
<ThreadID
>::iterator ready_it
=
1007 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
1008 readyThreads
.erase(ready_it
);
1011 "Attempting to activate new thread, but No Ready Threads to"
1014 "Unable to switch to next active thread.\n");
1019 InOrderCPU::activateThread(ThreadID tid
)
1021 if (isThreadSuspended(tid
)) {
1023 "Removing [tid:%i] from suspended threads list.\n", tid
);
1025 list
<ThreadID
>::iterator susp_it
=
1026 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
1028 suspendedThreads
.erase(susp_it
);
1031 if (threadModel
== SwitchOnCacheMiss
&&
1032 numActiveThreads() == 1) {
1034 "Ignoring activation of [tid:%i], since [tid:%i] is "
1035 "already running.\n", tid
, activeThreadId());
1037 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
1040 readyThreads
.push_back(tid
);
1042 } else if (!isThreadActive(tid
)) {
1044 "Adding [tid:%i] to active threads list.\n", tid
);
1045 activeThreads
.push_back(tid
);
1047 activateThreadInPipeline(tid
);
1049 thread
[tid
]->lastActivate
= curTick();
1051 tcBase(tid
)->setStatus(ThreadContext::Active
);
1060 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
1062 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
1063 pipelineStage
[stNum
]->activateThread(tid
);
1068 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
1070 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
1072 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1074 // Be sure to signal that there's some activity so the CPU doesn't
1075 // deschedule itself.
1076 activityRec
.activity();
1082 InOrderCPU::deactivateThread(ThreadID tid
)
1084 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
1086 if (isThreadActive(tid
)) {
1087 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
1089 list
<ThreadID
>::iterator thread_it
=
1090 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
1092 removePipelineStalls(*thread_it
);
1094 activeThreads
.erase(thread_it
);
1096 // Ideally, this should be triggered from the
1097 // suspendContext/Thread functions
1098 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1101 assert(!isThreadActive(tid
));
1105 InOrderCPU::removePipelineStalls(ThreadID tid
)
1107 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1110 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1111 pipelineStage
[stNum
]->removeStalls(tid
);
1117 InOrderCPU::updateThreadPriority()
1119 if (activeThreads
.size() > 1)
1121 //DEFAULT TO ROUND ROBIN SCHEME
1122 //e.g. Move highest priority to end of thread list
1123 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1125 unsigned high_thread
= *list_begin
;
1127 activeThreads
.erase(list_begin
);
1129 activeThreads
.push_back(high_thread
);
1134 InOrderCPU::tickThreadStats()
1136 /** Keep track of cycles that each thread is active */
1137 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1138 while (thread_it
!= activeThreads
.end()) {
1139 threadCycles
[*thread_it
]++;
1143 // Keep track of cycles where SMT is active
1144 if (activeThreads
.size() > 1) {
1150 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1152 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1155 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1157 // Be sure to signal that there's some activity so the CPU doesn't
1158 // deschedule itself.
1159 activityRec
.activity();
1165 InOrderCPU::activateNextReadyContext(int delay
)
1167 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1169 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1170 delay
, ActivateNextReadyThread_Pri
);
1172 // Be sure to signal that there's some activity so the CPU doesn't
1173 // deschedule itself.
1174 activityRec
.activity();
1180 InOrderCPU::haltContext(ThreadID tid
, int delay
)
1182 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1184 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1186 activityRec
.activity();
1190 InOrderCPU::haltThread(ThreadID tid
)
1192 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1193 deactivateThread(tid
);
1194 squashThreadInPipeline(tid
);
1195 haltedThreads
.push_back(tid
);
1197 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1199 if (threadModel
== SwitchOnCacheMiss
) {
1200 activateNextReadyContext();
1205 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
1207 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1211 InOrderCPU::suspendThread(ThreadID tid
)
1213 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1215 deactivateThread(tid
);
1216 suspendedThreads
.push_back(tid
);
1217 thread
[tid
]->lastSuspend
= curTick();
1219 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1223 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1225 //Squash all instructions in each stage
1226 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1227 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1232 InOrderCPU::getPipeStage(int stage_num
)
1234 return pipelineStage
[stage_num
];
1239 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1241 if (reg_idx
< FP_Base_DepTag
) {
1243 return isa
[tid
].flattenIntIndex(reg_idx
);
1244 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1245 reg_type
= FloatType
;
1246 reg_idx
-= FP_Base_DepTag
;
1247 return isa
[tid
].flattenFloatIndex(reg_idx
);
1249 reg_type
= MiscType
;
1250 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1255 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1257 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1258 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1260 return intRegs
[tid
][reg_idx
];
1264 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1266 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1267 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1269 return floatRegs
.f
[tid
][reg_idx
];
1273 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1275 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1276 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1278 return floatRegs
.i
[tid
][reg_idx
];
1282 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1284 if (reg_idx
== TheISA::ZeroReg
) {
1285 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1286 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1289 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1292 intRegs
[tid
][reg_idx
] = val
;
1298 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1300 floatRegs
.f
[tid
][reg_idx
] = val
;
1301 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1304 floatRegs
.i
[tid
][reg_idx
],
1305 floatRegs
.f
[tid
][reg_idx
]);
1310 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1312 floatRegs
.i
[tid
][reg_idx
] = val
;
1313 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1316 floatRegs
.i
[tid
][reg_idx
],
1317 floatRegs
.f
[tid
][reg_idx
]);
1321 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1323 // If Default value is set, then retrieve target thread
1324 if (tid
== InvalidThreadID
) {
1325 tid
= TheISA::getTargetThread(tcBase(tid
));
1328 if (reg_idx
< FP_Base_DepTag
) {
1329 // Integer Register File
1330 return readIntReg(reg_idx
, tid
);
1331 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1332 // Float Register File
1333 reg_idx
-= FP_Base_DepTag
;
1334 return readFloatRegBits(reg_idx
, tid
);
1336 reg_idx
-= Ctrl_Base_DepTag
;
1337 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1341 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1344 // If Default value is set, then retrieve target thread
1345 if (tid
== InvalidThreadID
) {
1346 tid
= TheISA::getTargetThread(tcBase(tid
));
1349 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1350 setIntReg(reg_idx
, val
, tid
);
1351 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1352 reg_idx
-= FP_Base_DepTag
;
1353 setFloatRegBits(reg_idx
, val
, tid
);
1355 reg_idx
-= Ctrl_Base_DepTag
;
1356 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1361 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1363 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1367 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1369 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1373 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1375 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1379 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1381 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1386 InOrderCPU::addInst(DynInstPtr inst
)
1388 ThreadID tid
= inst
->readTid();
1390 instList
[tid
].push_back(inst
);
1392 return --(instList
[tid
].end());
1396 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1398 ListIt it
= instList
[tid
].begin();
1399 ListIt end
= instList
[tid
].end();
1402 if ((*it
)->seqNum
== seq_num
)
1404 else if ((*it
)->seqNum
> seq_num
)
1410 return instList
[tid
].end();
1414 InOrderCPU::updateContextSwitchStats()
1416 // Set Average Stat Here, then reset to 0
1417 instsPerCtxtSwitch
= instsPerSwitch
;
1423 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1425 // Set the nextPC to be fetched if this is the last instruction
1428 // This contributes to the precise state of the CPU
1429 // which can be used when restoring a thread to the CPU after after any
1430 // type of context switching activity (fork, exception, etc.)
1431 TheISA::PCState comm_pc
= inst
->pcState();
1432 lastCommittedPC
[tid
] = comm_pc
;
1433 TheISA::advancePC(comm_pc
, inst
->staticInst
);
1434 pcState(comm_pc
, tid
);
1436 //@todo: may be unnecessary with new-ISA-specific branch handling code
1437 if (inst
->isControl()) {
1438 thread
[tid
]->lastGradIsBranch
= true;
1439 thread
[tid
]->lastBranchPC
= inst
->pcState();
1440 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1442 thread
[tid
]->lastGradIsBranch
= false;
1446 // Finalize Trace Data For Instruction
1447 if (inst
->traceData
) {
1448 //inst->traceData->setCycle(curTick());
1449 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1450 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1451 inst
->traceData
->dump();
1452 delete inst
->traceData
;
1453 inst
->traceData
= NULL
;
1456 // Increment active thread's instruction count
1459 // Increment thread-state's instruction count
1460 thread
[tid
]->numInst
++;
1462 // Increment thread-state's instruction stats
1463 thread
[tid
]->numInsts
++;
1465 // Count committed insts per thread stats
1466 committedInsts
[tid
]++;
1468 // Count total insts committed stat
1469 totalCommittedInsts
++;
1471 // Count SMT-committed insts per thread stat
1472 if (numActiveThreads() > 1) {
1473 smtCommittedInsts
[tid
]++;
1476 // Instruction-Mix Stats
1477 if (inst
->isLoad()) {
1479 } else if (inst
->isStore()) {
1481 } else if (inst
->isControl()) {
1483 } else if (inst
->isNop()) {
1485 } else if (inst
->isNonSpeculative()) {
1487 } else if (inst
->isInteger()) {
1489 } else if (inst
->isFloating()) {
1493 // Check for instruction-count-based events.
1494 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1496 // Finally, remove instruction from CPU
1500 // currently unused function, but substitute repetitive code w/this function
1503 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1505 removeInstsThisCycle
= true;
1506 if (!inst
->isRemoveList()) {
1507 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1508 "[sn:%lli] to remove list\n",
1509 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1510 inst
->setRemoveList();
1511 removeList
.push(inst
->getInstListIt());
1513 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1514 "[sn:%lli], already remove list\n",
1515 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1521 InOrderCPU::removeInst(DynInstPtr inst
)
1523 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1525 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1527 removeInstsThisCycle
= true;
1529 // Remove the instruction.
1530 if (!inst
->isRemoveList()) {
1531 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1532 "[sn:%lli] to remove list\n",
1533 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1534 inst
->setRemoveList();
1535 removeList
.push(inst
->getInstListIt());
1537 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1538 "[sn:%lli], already on remove list\n",
1539 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1545 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1547 //assert(!instList[tid].empty());
1549 removeInstsThisCycle
= true;
1551 ListIt inst_iter
= instList
[tid
].end();
1555 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1556 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1557 tid
, seq_num
, (*inst_iter
)->seqNum
);
1559 while ((*inst_iter
)->seqNum
> seq_num
) {
1561 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1563 squashInstIt(inst_iter
, tid
);
1574 InOrderCPU::squashInstIt(const ListIt inst_it
, ThreadID tid
)
1576 DynInstPtr inst
= (*inst_it
);
1577 if (inst
->threadNumber
== tid
) {
1578 DPRINTF(InOrderCPU
, "Squashing instruction, "
1579 "[tid:%i] [sn:%lli] PC %s\n",
1584 inst
->setSquashed();
1585 archRegDepMap
[tid
].remove(inst
);
1587 if (!inst
->isRemoveList()) {
1588 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1589 "[sn:%lli] to remove list\n",
1590 inst
->threadNumber
, inst
->pcState(),
1592 inst
->setRemoveList();
1593 removeList
.push(inst_it
);
1595 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1596 " PC %s [sn:%lli], already on remove list\n",
1597 inst
->threadNumber
, inst
->pcState(),
1607 InOrderCPU::cleanUpRemovedInsts()
1609 while (!removeList
.empty()) {
1610 DPRINTF(InOrderCPU
, "Removing instruction, "
1611 "[tid:%i] [sn:%lli] PC %s\n",
1612 (*removeList
.front())->threadNumber
,
1613 (*removeList
.front())->seqNum
,
1614 (*removeList
.front())->pcState());
1616 DynInstPtr inst
= *removeList
.front();
1617 ThreadID tid
= inst
->threadNumber
;
1619 // Remove From Register Dependency Map, If Necessary
1620 // archRegDepMap[tid].remove(inst);
1622 // Clear if Non-Speculative
1623 if (inst
->staticInst
&&
1624 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1625 nonSpecInstActive
[tid
] == true) {
1626 nonSpecInstActive
[tid
] = false;
1629 inst
->onInstList
= false;
1631 instList
[tid
].erase(removeList
.front());
1636 removeInstsThisCycle
= false;
1640 InOrderCPU::cleanUpRemovedEvents()
1642 while (!cpuEventRemoveList
.empty()) {
1643 Event
*cpu_event
= cpuEventRemoveList
.front();
1644 cpuEventRemoveList
.pop();
1651 InOrderCPU::dumpInsts()
1655 ListIt inst_list_it
= instList
[0].begin();
1657 cprintf("Dumping Instruction List\n");
1659 while (inst_list_it
!= instList
[0].end()) {
1660 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1662 num
, (*inst_list_it
)->pcState(),
1663 (*inst_list_it
)->threadNumber
,
1664 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1665 (*inst_list_it
)->isSquashed());
1672 InOrderCPU::wakeCPU()
1674 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1675 DPRINTF(Activity
, "CPU already running.\n");
1679 DPRINTF(Activity
, "Waking up CPU\n");
1681 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1683 idleCycles
+= extra_cycles
;
1684 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1685 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1688 numCycles
+= extra_cycles
;
1690 schedule(&tickEvent
, nextCycle(curTick()));
1694 // Lots of copied full system code...place into BaseCPU class?
1696 InOrderCPU::wakeup()
1698 if (thread
[0]->status() != ThreadContext::Suspended
)
1703 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1704 threadContexts
[0]->activate();
1710 InOrderCPU::syscallContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
1712 // Syscall must be non-speculative, so squash from last stage
1713 unsigned squash_stage
= NumStages
- 1;
1714 inst
->setSquashInfo(squash_stage
);
1716 // Squash In Pipeline Stage
1717 pipelineStage
[squash_stage
]->setupSquash(inst
, tid
);
1719 // Schedule Squash Through-out Resource Pool
1720 resPool
->scheduleEvent(
1721 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
, inst
, 0);
1722 scheduleCpuEvent(Syscall
, fault
, tid
, inst
, delay
, Syscall_Pri
);
1726 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1728 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1730 DPRINTF(Activity
,"Activity: syscall() called.\n");
1732 // Temporarily increase this by one to account for the syscall
1734 ++(this->thread
[tid
]->funcExeInst
);
1736 // Execute the actual syscall.
1737 this->thread
[tid
]->syscall(callnum
);
1739 // Decrease funcExeInst by one as the normal commit will handle
1741 --(this->thread
[tid
]->funcExeInst
);
1743 // Clear Non-Speculative Block Variable
1744 nonSpecInstActive
[tid
] = false;
1749 InOrderCPU::getITBPtr()
1751 CacheUnit
*itb_res
=
1752 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1753 return itb_res
->tlb();
1758 InOrderCPU::getDTBPtr()
1760 CacheUnit
*dtb_res
=
1761 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1762 return dtb_res
->tlb();
1766 InOrderCPU::getDecoderPtr()
1768 FetchUnit
*fetch_res
=
1769 dynamic_cast<FetchUnit
*>(resPool
->getResource(fetchPortIdx
));
1770 return &fetch_res
->decoder
;
1774 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1775 uint8_t *data
, unsigned size
, unsigned flags
)
1777 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1778 // you want to run w/out caches?
1779 CacheUnit
*cache_res
=
1780 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1782 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1786 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1787 Addr addr
, unsigned flags
, uint64_t *write_res
)
1789 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1790 // you want to run w/out caches?
1791 CacheUnit
*cache_res
=
1792 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1793 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);