2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "base/bigint.hh"
36 #include "config/full_system.hh"
37 #include "config/the_isa.hh"
38 #include "cpu/inorder/resources/resource_list.hh"
39 #include "cpu/inorder/cpu.hh"
40 #include "cpu/inorder/first_stage.hh"
41 #include "cpu/inorder/inorder_dyn_inst.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/resource_pool.hh"
44 #include "cpu/inorder/thread_context.hh"
45 #include "cpu/inorder/thread_state.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/base.hh"
48 #include "cpu/exetrace.hh"
49 #include "cpu/simple_thread.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/Activity.hh"
52 #include "debug/InOrderCPU.hh"
53 #include "debug/RefCount.hh"
54 #include "debug/SkedCache.hh"
55 #include "mem/translating_port.hh"
56 #include "params/InOrderCPU.hh"
57 #include "sim/process.hh"
58 #include "sim/stat_control.hh"
61 #include "cpu/quiesce_event.hh"
62 #include "sim/system.hh"
65 #if THE_ISA == ALPHA_ISA
66 #include "arch/alpha/osfpal.hh"
70 using namespace TheISA
;
71 using namespace ThePipeline
;
73 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
74 : Event(CPU_Tick_Pri
), cpu(c
)
79 InOrderCPU::TickEvent::process()
86 InOrderCPU::TickEvent::description()
88 return "InOrderCPU tick event";
91 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
92 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
93 unsigned event_pri_offset
)
94 : Event(Event::Priority((unsigned int)CPU_Tick_Pri
+ event_pri_offset
)),
97 setEvent(e_type
, fault
, _tid
, inst
);
101 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
104 "ActivateNextReadyThread",
110 "SquashFromMemStall",
115 InOrderCPU::CPUEvent::process()
117 switch (cpuEventType
)
120 cpu
->activateThread(tid
);
123 case ActivateNextReadyThread
:
124 cpu
->activateNextReadyThread();
127 case DeactivateThread
:
128 cpu
->deactivateThread(tid
);
132 cpu
->haltThread(tid
);
136 cpu
->suspendThread(tid
);
139 case SquashFromMemStall
:
140 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
144 DPRINTF(InOrderCPU
, "Trapping CPU\n");
145 cpu
->trapCPU(fault
, tid
, inst
);
149 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
152 cpu
->cpuEventRemoveList
.push(this);
158 InOrderCPU::CPUEvent::description()
160 return "InOrderCPU event";
164 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
166 assert(!scheduled() || squashed());
167 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
171 InOrderCPU::CPUEvent::unscheduleEvent()
177 InOrderCPU::InOrderCPU(Params
*params
)
179 cpu_id(params
->cpu_id
),
183 stageWidth(params
->stageWidth
),
185 removeInstsThisCycle(false),
186 activityRec(params
->name
, NumStages
, 10, params
->activity
),
188 system(params
->system
),
189 physmem(system
->physmem
),
190 #endif // FULL_SYSTEM
196 deferRegistration(false/*params->deferRegistration*/),
197 stageTracing(params
->stageTracing
),
200 ThreadID active_threads
;
203 resPool
= new ResourcePool(this, params
);
205 // Resize for Multithreading CPUs
206 thread
.resize(numThreads
);
211 active_threads
= params
->workload
.size();
213 if (active_threads
> MaxThreads
) {
214 panic("Workload Size too large. Increase the 'MaxThreads'"
215 "in your InOrder implementation or "
216 "edit your workload size.");
220 if (active_threads
> 1) {
221 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
223 if (threadModel
== SMT
) {
224 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
225 } else if (threadModel
== SwitchOnCacheMiss
) {
226 DPRINTF(InOrderCPU
, "Setting Thread Model to "
227 "Switch On Cache Miss\n");
231 threadModel
= Single
;
238 // Bind the fetch & data ports from the resource pool.
239 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
240 if (fetchPortIdx
== 0) {
241 fatal("Unable to find port to fetch instructions from.\n");
244 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
245 if (dataPortIdx
== 0) {
246 fatal("Unable to find port for data.\n");
249 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
251 // SMT is not supported in FS mode yet.
252 assert(numThreads
== 1);
253 thread
[tid
] = new Thread(this, 0);
255 if (tid
< (ThreadID
)params
->workload
.size()) {
256 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
257 tid
, params
->workload
[tid
]->prog_fname
);
259 new Thread(this, tid
, params
->workload
[tid
]);
261 //Allocate Empty thread so M5 can use later
262 //when scheduling threads to CPU
263 Process
* dummy_proc
= params
->workload
[0];
264 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
267 // Eventually set this with parameters...
271 // Setup the TC that will serve as the interface to the threads/CPU.
272 InOrderThreadContext
*tc
= new InOrderThreadContext
;
274 tc
->thread
= thread
[tid
];
276 // Give the thread the TC.
277 thread
[tid
]->tc
= tc
;
278 thread
[tid
]->setFuncExeInst(0);
279 globalSeqNum
[tid
] = 1;
281 // Add the TC to the CPU's list of TC's.
282 this->threadContexts
.push_back(tc
);
285 // Initialize TimeBuffer Stage Queues
286 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
287 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
288 stageQueue
[stNum
]->id(stNum
);
292 // Set Up Pipeline Stages
293 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
295 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
297 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
299 pipelineStage
[stNum
]->setCPU(this);
300 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
301 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
303 // Take Care of 1st/Nth stages
305 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
306 if (stNum
< NumStages
- 1)
307 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
310 // Initialize thread specific variables
311 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
312 archRegDepMap
[tid
].setCPU(this);
314 nonSpecInstActive
[tid
] = false;
315 nonSpecSeqNum
[tid
] = 0;
317 squashSeqNum
[tid
] = MaxAddr
;
318 lastSquashCycle
[tid
] = 0;
320 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
321 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
324 // Define dummy instructions and resource requests to be used.
325 dummyInst
[tid
] = new InOrderDynInst(this,
331 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
334 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
335 dummyReqInst
->setSquashed();
336 dummyReqInst
->resetInstCount();
338 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
339 dummyBufferInst
->setSquashed();
340 dummyBufferInst
->resetInstCount();
342 endOfSkedIt
= skedCache
.end();
343 frontEndSked
= createFrontEndSked();
345 lastRunningCycle
= curTick();
347 // Reset CPU to reset state.
349 Fault resetFault
= new ResetFault();
350 resetFault
->invoke(tcBase());
354 // Schedule First Tick Event, CPU will reschedule itself from here on out.
355 scheduleTickEvent(0);
358 InOrderCPU::~InOrderCPU()
362 SkedCacheIt sked_it
= skedCache
.begin();
363 SkedCacheIt sked_end
= skedCache
.end();
365 while (sked_it
!= sked_end
) {
366 delete (*sked_it
).second
;
372 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
375 InOrderCPU::createFrontEndSked()
377 RSkedPtr res_sked
= new ResourceSked();
379 StageScheduler
F(res_sked
, stage_num
++);
380 StageScheduler
D(res_sked
, stage_num
++);
383 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
384 F
.needs(ICache
, FetchUnit::InitiateFetch
);
387 D
.needs(ICache
, FetchUnit::CompleteFetch
);
388 D
.needs(Decode
, DecodeUnit::DecodeInst
);
389 D
.needs(BPred
, BranchPredictor::PredictBranch
);
390 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
393 DPRINTF(SkedCache
, "Resource Sked created for instruction \"front_end\"\n");
399 InOrderCPU::createBackEndSked(DynInstPtr inst
)
401 RSkedPtr res_sked
= lookupSked(inst
);
402 if (res_sked
!= NULL
) {
403 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
407 res_sked
= new ResourceSked();
410 int stage_num
= ThePipeline::BackEndStartStage
;
411 StageScheduler
X(res_sked
, stage_num
++);
412 StageScheduler
M(res_sked
, stage_num
++);
413 StageScheduler
W(res_sked
, stage_num
++);
415 if (!inst
->staticInst
) {
416 warn_once("Static Instruction Object Not Set. Can't Create"
417 " Back End Schedule");
422 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
423 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
424 if (!idx
|| !inst
->isStore()) {
425 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
429 //@todo: schedule non-spec insts to operate on this cycle
430 // as long as all previous insts are done
431 if ( inst
->isNonSpeculative() ) {
432 // skip execution of non speculative insts until later
433 } else if ( inst
->isMemRef() ) {
434 if ( inst
->isLoad() ) {
435 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
437 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
438 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
440 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
444 if (!inst
->isNonSpeculative()) {
445 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
446 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
449 if ( inst
->isLoad() ) {
450 M
.needs(DCache
, CacheUnit::InitiateReadData
);
452 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
453 } else if ( inst
->isStore() ) {
454 if ( inst
->numSrcRegs() >= 2 ) {
455 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
457 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
458 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
460 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
465 if (!inst
->isNonSpeculative()) {
466 if ( inst
->isLoad() ) {
467 W
.needs(DCache
, CacheUnit::CompleteReadData
);
469 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
470 } else if ( inst
->isStore() ) {
471 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
473 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
476 // Finally, Execute Speculative Data
477 if (inst
->isMemRef()) {
478 if (inst
->isLoad()) {
479 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
480 W
.needs(DCache
, CacheUnit::InitiateReadData
);
482 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
483 W
.needs(DCache
, CacheUnit::CompleteReadData
);
485 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
486 } else if (inst
->isStore()) {
487 if ( inst
->numSrcRegs() >= 2 ) {
488 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
490 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
491 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
493 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
494 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
496 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
499 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
503 W
.needs(Grad
, GraduationUnit::GraduateInst
);
505 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
506 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
509 // Insert Back Schedule into our cache of
510 // resource schedules
511 addToSkedCache(inst
, res_sked
);
513 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
514 inst
->instName(), inst
->getMachInst());
521 InOrderCPU::regStats()
523 /* Register the Resource Pool's stats here.*/
526 /* Register for each Pipeline Stage */
527 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
528 pipelineStage
[stage_num
]->regStats();
531 /* Register any of the InOrderCPU's stats here.*/
533 .name(name() + ".instsPerContextSwitch")
534 .desc("Instructions Committed Per Context Switch")
535 .prereq(instsPerCtxtSwitch
);
538 .name(name() + ".contextSwitches")
539 .desc("Number of context switches");
542 .name(name() + ".comLoads")
543 .desc("Number of Load instructions committed");
546 .name(name() + ".comStores")
547 .desc("Number of Store instructions committed");
550 .name(name() + ".comBranches")
551 .desc("Number of Branches instructions committed");
554 .name(name() + ".comNops")
555 .desc("Number of Nop instructions committed");
558 .name(name() + ".comNonSpec")
559 .desc("Number of Non-Speculative instructions committed");
562 .name(name() + ".comInts")
563 .desc("Number of Integer instructions committed");
566 .name(name() + ".comFloats")
567 .desc("Number of Floating Point instructions committed");
570 .name(name() + ".timesIdled")
571 .desc("Number of times that the entire CPU went into an idle state and"
572 " unscheduled itself")
576 .name(name() + ".idleCycles")
577 .desc("Number of cycles cpu's stages were not processed");
580 .name(name() + ".runCycles")
581 .desc("Number of cycles cpu stages are processed.");
584 .name(name() + ".activity")
585 .desc("Percentage of cycles cpu is active")
587 activity
= (runCycles
/ numCycles
) * 100;
591 .name(name() + ".threadCycles")
592 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
595 .name(name() + ".smtCycles")
596 .desc("Total number of cycles that the CPU was in SMT-mode");
600 .name(name() + ".committedInsts")
601 .desc("Number of Instructions Simulated (Per-Thread)");
605 .name(name() + ".smtCommittedInsts")
606 .desc("Number of SMT Instructions Simulated (Per-Thread)");
609 .name(name() + ".committedInsts_total")
610 .desc("Number of Instructions Simulated (Total)");
613 .name(name() + ".cpi")
614 .desc("CPI: Cycles Per Instruction (Per-Thread)")
616 cpi
= numCycles
/ committedInsts
;
619 .name(name() + ".smt_cpi")
620 .desc("CPI: Total SMT-CPI")
622 smtCpi
= smtCycles
/ smtCommittedInsts
;
625 .name(name() + ".cpi_total")
626 .desc("CPI: Total CPI of All Threads")
628 totalCpi
= numCycles
/ totalCommittedInsts
;
631 .name(name() + ".ipc")
632 .desc("IPC: Instructions Per Cycle (Per-Thread)")
634 ipc
= committedInsts
/ numCycles
;
637 .name(name() + ".smt_ipc")
638 .desc("IPC: Total SMT-IPC")
640 smtIpc
= smtCommittedInsts
/ smtCycles
;
643 .name(name() + ".ipc_total")
644 .desc("IPC: Total IPC of All Threads")
646 totalIpc
= totalCommittedInsts
/ numCycles
;
655 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
659 bool pipes_idle
= true;
661 //Tick each of the stages
662 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
663 pipelineStage
[stNum
]->tick();
665 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
673 // Now advance the time buffers one tick
674 timeBuffer
.advance();
675 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
676 stageQueue
[sqNum
]->advance();
678 activityRec
.advance();
680 // Any squashed events, or insts then remove them now
681 cleanUpRemovedEvents();
682 cleanUpRemovedInsts();
684 // Re-schedule CPU for this cycle
685 if (!tickEvent
.scheduled()) {
686 if (_status
== SwitchedOut
) {
688 lastRunningCycle
= curTick();
689 } else if (!activityRec
.active()) {
690 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
691 lastRunningCycle
= curTick();
694 //Tick next_tick = curTick() + cycles(1);
695 //tickEvent.schedule(next_tick);
696 schedule(&tickEvent
, nextCycle(curTick() + 1));
697 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
698 nextCycle(curTick() + 1));
703 updateThreadPriority();
710 if (!deferRegistration
) {
711 registerThreadContexts();
714 // Set inSyscall so that the CPU doesn't squash when initially
715 // setting up registers.
716 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
717 thread
[tid
]->inSyscall
= true;
720 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
721 ThreadContext
*src_tc
= threadContexts
[tid
];
722 TheISA::initCPU(src_tc
, src_tc
->contextId());
727 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
728 thread
[tid
]->inSyscall
= false;
730 // Call Initializiation Routine for Resource Pool
735 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
737 return resPool
->getPort(if_name
, idx
);
742 InOrderCPU::hwrei(ThreadID tid
)
744 panic("hwrei: Unimplemented");
751 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
753 panic("simPalCheck: Unimplemented");
760 InOrderCPU::getInterrupts()
762 // Check if there are any outstanding interrupts
763 return interrupts
->getInterrupt(threadContexts
[0]);
768 InOrderCPU::processInterrupts(Fault interrupt
)
770 // Check for interrupts here. For now can copy the code that
771 // exists within isa_fullsys_traits.hh. Also assume that thread 0
772 // is the one that handles the interrupts.
773 // @todo: Possibly consolidate the interrupt checking code.
774 // @todo: Allow other threads to handle interrupts.
776 assert(interrupt
!= NoFault
);
777 interrupts
->updateIntrInfo(threadContexts
[0]);
779 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
781 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
782 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
787 InOrderCPU::updateMemPorts()
789 // Update all ThreadContext's memory ports (Functional/Virtual
791 ThreadID size
= thread
.size();
792 for (ThreadID i
= 0; i
< size
; ++i
)
793 thread
[i
]->connectMemPorts(thread
[i
]->getTC());
798 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
800 //@ Squash Pipeline during TRAP
801 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
805 InOrderCPU::trapCPU(Fault fault
, ThreadID tid
, DynInstPtr inst
)
807 fault
->invoke(tcBase(tid
), inst
->staticInst
);
811 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
813 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
818 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
821 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
823 // Squash all instructions in each stage including
824 // instruction that caused the squash (seq_num - 1)
825 // NOTE: The stage bandwidth needs to be cleared so thats why
826 // the stalling instruction is squashed as well. The stalled
827 // instruction is previously placed in another intermediate buffer
828 // while it's stall is being handled.
829 InstSeqNum squash_seq_num
= seq_num
- 1;
831 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
832 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
837 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
838 ThreadID tid
, DynInstPtr inst
,
839 unsigned delay
, unsigned event_pri_offset
)
841 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
844 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
846 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
847 eventNames
[c_event
], curTick() + delay
, tid
);
848 schedule(cpu_event
, sked_tick
);
850 cpu_event
->process();
851 cpuEventRemoveList
.push(cpu_event
);
854 // Broadcast event to the Resource Pool
855 // Need to reset tid just in case this is a dummy instruction
857 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
861 InOrderCPU::isThreadActive(ThreadID tid
)
863 list
<ThreadID
>::iterator isActive
=
864 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
866 return (isActive
!= activeThreads
.end());
870 InOrderCPU::isThreadReady(ThreadID tid
)
872 list
<ThreadID
>::iterator isReady
=
873 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
875 return (isReady
!= readyThreads
.end());
879 InOrderCPU::isThreadSuspended(ThreadID tid
)
881 list
<ThreadID
>::iterator isSuspended
=
882 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
884 return (isSuspended
!= suspendedThreads
.end());
888 InOrderCPU::activateNextReadyThread()
890 if (readyThreads
.size() >= 1) {
891 ThreadID ready_tid
= readyThreads
.front();
893 // Activate in Pipeline
894 activateThread(ready_tid
);
896 // Activate in Resource Pool
897 resPool
->activateAll(ready_tid
);
899 list
<ThreadID
>::iterator ready_it
=
900 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
901 readyThreads
.erase(ready_it
);
904 "Attempting to activate new thread, but No Ready Threads to"
907 "Unable to switch to next active thread.\n");
912 InOrderCPU::activateThread(ThreadID tid
)
914 if (isThreadSuspended(tid
)) {
916 "Removing [tid:%i] from suspended threads list.\n", tid
);
918 list
<ThreadID
>::iterator susp_it
=
919 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
921 suspendedThreads
.erase(susp_it
);
924 if (threadModel
== SwitchOnCacheMiss
&&
925 numActiveThreads() == 1) {
927 "Ignoring activation of [tid:%i], since [tid:%i] is "
928 "already running.\n", tid
, activeThreadId());
930 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
933 readyThreads
.push_back(tid
);
935 } else if (!isThreadActive(tid
)) {
937 "Adding [tid:%i] to active threads list.\n", tid
);
938 activeThreads
.push_back(tid
);
940 activateThreadInPipeline(tid
);
942 thread
[tid
]->lastActivate
= curTick();
944 tcBase(tid
)->setStatus(ThreadContext::Active
);
953 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
955 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
956 pipelineStage
[stNum
]->activateThread(tid
);
961 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
963 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
965 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
967 // Be sure to signal that there's some activity so the CPU doesn't
968 // deschedule itself.
969 activityRec
.activity();
975 InOrderCPU::deactivateThread(ThreadID tid
)
977 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
979 if (isThreadActive(tid
)) {
980 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
982 list
<ThreadID
>::iterator thread_it
=
983 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
985 removePipelineStalls(*thread_it
);
987 activeThreads
.erase(thread_it
);
989 // Ideally, this should be triggered from the
990 // suspendContext/Thread functions
991 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
994 assert(!isThreadActive(tid
));
998 InOrderCPU::removePipelineStalls(ThreadID tid
)
1000 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1003 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1004 pipelineStage
[stNum
]->removeStalls(tid
);
1010 InOrderCPU::updateThreadPriority()
1012 if (activeThreads
.size() > 1)
1014 //DEFAULT TO ROUND ROBIN SCHEME
1015 //e.g. Move highest priority to end of thread list
1016 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1017 list
<ThreadID
>::iterator list_end
= activeThreads
.end();
1019 unsigned high_thread
= *list_begin
;
1021 activeThreads
.erase(list_begin
);
1023 activeThreads
.push_back(high_thread
);
1028 InOrderCPU::tickThreadStats()
1030 /** Keep track of cycles that each thread is active */
1031 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1032 while (thread_it
!= activeThreads
.end()) {
1033 threadCycles
[*thread_it
]++;
1037 // Keep track of cycles where SMT is active
1038 if (activeThreads
.size() > 1) {
1044 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1046 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1049 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1051 // Be sure to signal that there's some activity so the CPU doesn't
1052 // deschedule itself.
1053 activityRec
.activity();
1059 InOrderCPU::activateNextReadyContext(int delay
)
1061 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1063 // NOTE: Add 5 to the event priority so that we always activate
1064 // threads after we've finished deactivating, squashing,etc.
1066 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1069 // Be sure to signal that there's some activity so the CPU doesn't
1070 // deschedule itself.
1071 activityRec
.activity();
1077 InOrderCPU::haltContext(ThreadID tid
, int delay
)
1079 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1081 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1083 activityRec
.activity();
1087 InOrderCPU::haltThread(ThreadID tid
)
1089 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1090 deactivateThread(tid
);
1091 squashThreadInPipeline(tid
);
1092 haltedThreads
.push_back(tid
);
1094 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1096 if (threadModel
== SwitchOnCacheMiss
) {
1097 activateNextReadyContext();
1102 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
1104 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1108 InOrderCPU::suspendThread(ThreadID tid
)
1110 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1112 deactivateThread(tid
);
1113 suspendedThreads
.push_back(tid
);
1114 thread
[tid
]->lastSuspend
= curTick();
1116 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1120 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1122 //Squash all instructions in each stage
1123 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1124 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1129 InOrderCPU::getPipeStage(int stage_num
)
1131 return pipelineStage
[stage_num
];
1135 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1137 if (reg_idx
< FP_Base_DepTag
) {
1139 return isa
[tid
].flattenIntIndex(reg_idx
);
1140 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1141 reg_type
= FloatType
;
1142 reg_idx
-= FP_Base_DepTag
;
1143 return isa
[tid
].flattenFloatIndex(reg_idx
);
1145 reg_type
= MiscType
;
1146 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1151 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1153 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1154 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1156 return intRegs
[tid
][reg_idx
];
1160 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1162 return floatRegs
.f
[tid
][reg_idx
];
1166 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1168 return floatRegs
.i
[tid
][reg_idx
];
1172 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1174 if (reg_idx
== TheISA::ZeroReg
) {
1175 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1176 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1179 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1182 intRegs
[tid
][reg_idx
] = val
;
1188 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1190 floatRegs
.f
[tid
][reg_idx
] = val
;
1195 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1197 floatRegs
.i
[tid
][reg_idx
] = val
;
1201 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1203 // If Default value is set, then retrieve target thread
1204 if (tid
== InvalidThreadID
) {
1205 tid
= TheISA::getTargetThread(tcBase(tid
));
1208 if (reg_idx
< FP_Base_DepTag
) {
1209 // Integer Register File
1210 return readIntReg(reg_idx
, tid
);
1211 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1212 // Float Register File
1213 reg_idx
-= FP_Base_DepTag
;
1214 return readFloatRegBits(reg_idx
, tid
);
1216 reg_idx
-= Ctrl_Base_DepTag
;
1217 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1221 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1224 // If Default value is set, then retrieve target thread
1225 if (tid
== InvalidThreadID
) {
1226 tid
= TheISA::getTargetThread(tcBase(tid
));
1229 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1230 setIntReg(reg_idx
, val
, tid
);
1231 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1232 reg_idx
-= FP_Base_DepTag
;
1233 setFloatRegBits(reg_idx
, val
, tid
);
1235 reg_idx
-= Ctrl_Base_DepTag
;
1236 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1241 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1243 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1247 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1249 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1253 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1255 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1259 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1261 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1266 InOrderCPU::addInst(DynInstPtr inst
)
1268 ThreadID tid
= inst
->readTid();
1270 instList
[tid
].push_back(inst
);
1272 return --(instList
[tid
].end());
1276 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1278 ListIt it
= instList
[tid
].begin();
1279 ListIt end
= instList
[tid
].end();
1282 if ((*it
)->seqNum
== seq_num
)
1284 else if ((*it
)->seqNum
> seq_num
)
1290 return instList
[tid
].end();
1294 InOrderCPU::updateContextSwitchStats()
1296 // Set Average Stat Here, then reset to 0
1297 instsPerCtxtSwitch
= instsPerSwitch
;
1303 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1305 // Set the CPU's PCs - This contributes to the precise state of the CPU
1306 // which can be used when restoring a thread to the CPU after after any
1307 // type of context switching activity (fork, exception, etc.)
1308 pcState(inst
->pcState(), tid
);
1310 if (inst
->isControl()) {
1311 thread
[tid
]->lastGradIsBranch
= true;
1312 thread
[tid
]->lastBranchPC
= inst
->pcState();
1313 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1315 thread
[tid
]->lastGradIsBranch
= false;
1319 // Finalize Trace Data For Instruction
1320 if (inst
->traceData
) {
1321 //inst->traceData->setCycle(curTick());
1322 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1323 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1324 inst
->traceData
->dump();
1325 delete inst
->traceData
;
1326 inst
->traceData
= NULL
;
1329 // Increment active thread's instruction count
1332 // Increment thread-state's instruction count
1333 thread
[tid
]->numInst
++;
1335 // Increment thread-state's instruction stats
1336 thread
[tid
]->numInsts
++;
1338 // Count committed insts per thread stats
1339 committedInsts
[tid
]++;
1341 // Count total insts committed stat
1342 totalCommittedInsts
++;
1344 // Count SMT-committed insts per thread stat
1345 if (numActiveThreads() > 1) {
1346 smtCommittedInsts
[tid
]++;
1349 // Instruction-Mix Stats
1350 if (inst
->isLoad()) {
1352 } else if (inst
->isStore()) {
1354 } else if (inst
->isControl()) {
1356 } else if (inst
->isNop()) {
1358 } else if (inst
->isNonSpeculative()) {
1360 } else if (inst
->isInteger()) {
1362 } else if (inst
->isFloating()) {
1366 // Check for instruction-count-based events.
1367 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1369 // Broadcast to other resources an instruction
1370 // has been completed
1371 resPool
->scheduleEvent((CPUEventType
)ResourcePool::InstGraduated
, inst
,
1374 // Finally, remove instruction from CPU
1378 // currently unused function, but substitute repetitive code w/this function
1381 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1383 removeInstsThisCycle
= true;
1384 if (!inst
->isRemoveList()) {
1385 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1386 "[sn:%lli] to remove list\n",
1387 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1388 inst
->setRemoveList();
1389 removeList
.push(inst
->getInstListIt());
1391 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1392 "[sn:%lli], already remove list\n",
1393 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1399 InOrderCPU::removeInst(DynInstPtr inst
)
1401 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1403 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1405 removeInstsThisCycle
= true;
1407 // Remove the instruction.
1408 if (!inst
->isRemoveList()) {
1409 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1410 "[sn:%lli] to remove list\n",
1411 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1412 inst
->setRemoveList();
1413 removeList
.push(inst
->getInstListIt());
1415 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1416 "[sn:%lli], already on remove list\n",
1417 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1423 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1425 //assert(!instList[tid].empty());
1427 removeInstsThisCycle
= true;
1429 ListIt inst_iter
= instList
[tid
].end();
1433 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1434 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1435 tid
, seq_num
, (*inst_iter
)->seqNum
);
1437 while ((*inst_iter
)->seqNum
> seq_num
) {
1439 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1441 squashInstIt(inst_iter
, tid
);
1452 InOrderCPU::squashInstIt(const ListIt
&instIt
, ThreadID tid
)
1454 if ((*instIt
)->threadNumber
== tid
) {
1455 DPRINTF(InOrderCPU
, "Squashing instruction, "
1456 "[tid:%i] [sn:%lli] PC %s\n",
1457 (*instIt
)->threadNumber
,
1459 (*instIt
)->pcState());
1461 (*instIt
)->setSquashed();
1463 if (!(*instIt
)->isRemoveList()) {
1464 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1465 "[sn:%lli] to remove list\n",
1466 (*instIt
)->threadNumber
, (*instIt
)->pcState(),
1468 (*instIt
)->setRemoveList();
1469 removeList
.push(instIt
);
1471 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1472 " PC %s [sn:%lli], already on remove list\n",
1473 (*instIt
)->threadNumber
, (*instIt
)->pcState(),
1483 InOrderCPU::cleanUpRemovedInsts()
1485 while (!removeList
.empty()) {
1486 DPRINTF(InOrderCPU
, "Removing instruction, "
1487 "[tid:%i] [sn:%lli] PC %s\n",
1488 (*removeList
.front())->threadNumber
,
1489 (*removeList
.front())->seqNum
,
1490 (*removeList
.front())->pcState());
1492 DynInstPtr inst
= *removeList
.front();
1493 ThreadID tid
= inst
->threadNumber
;
1495 // Remove From Register Dependency Map, If Necessary
1496 archRegDepMap
[tid
].remove(inst
);
1498 // Clear if Non-Speculative
1499 if (inst
->staticInst
&&
1500 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1501 nonSpecInstActive
[tid
] == true) {
1502 nonSpecInstActive
[tid
] = false;
1505 inst
->onInstList
= false;
1507 instList
[tid
].erase(removeList
.front());
1512 removeInstsThisCycle
= false;
1516 InOrderCPU::cleanUpRemovedEvents()
1518 while (!cpuEventRemoveList
.empty()) {
1519 Event
*cpu_event
= cpuEventRemoveList
.front();
1520 cpuEventRemoveList
.pop();
1527 InOrderCPU::dumpInsts()
1531 ListIt inst_list_it
= instList
[0].begin();
1533 cprintf("Dumping Instruction List\n");
1535 while (inst_list_it
!= instList
[0].end()) {
1536 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1538 num
, (*inst_list_it
)->pcState(),
1539 (*inst_list_it
)->threadNumber
,
1540 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1541 (*inst_list_it
)->isSquashed());
1548 InOrderCPU::wakeCPU()
1550 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1551 DPRINTF(Activity
, "CPU already running.\n");
1555 DPRINTF(Activity
, "Waking up CPU\n");
1557 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1559 idleCycles
+= extra_cycles
;
1560 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1561 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1564 numCycles
+= extra_cycles
;
1566 schedule(&tickEvent
, nextCycle(curTick()));
1572 InOrderCPU::wakeup()
1574 if (thread
[0]->status() != ThreadContext::Suspended
)
1579 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1580 threadContexts
[0]->activate();
1586 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1588 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1590 DPRINTF(Activity
,"Activity: syscall() called.\n");
1592 // Temporarily increase this by one to account for the syscall
1594 ++(this->thread
[tid
]->funcExeInst
);
1596 // Execute the actual syscall.
1597 this->thread
[tid
]->syscall(callnum
);
1599 // Decrease funcExeInst by one as the normal commit will handle
1601 --(this->thread
[tid
]->funcExeInst
);
1603 // Clear Non-Speculative Block Variable
1604 nonSpecInstActive
[tid
] = false;
1609 InOrderCPU::getITBPtr()
1611 CacheUnit
*itb_res
=
1612 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1613 return itb_res
->tlb();
1618 InOrderCPU::getDTBPtr()
1620 CacheUnit
*dtb_res
=
1621 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1622 return dtb_res
->tlb();
1626 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1627 uint8_t *data
, unsigned size
, unsigned flags
)
1629 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1630 // you want to run w/out caches?
1631 CacheUnit
*cache_res
=
1632 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1634 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1638 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1639 Addr addr
, unsigned flags
, uint64_t *write_res
)
1641 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1642 // you want to run w/out caches?
1643 CacheUnit
*cache_res
=
1644 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1645 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);