2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 MIPS Technologies, Inc.
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Korey Sewell
46 #include "arch/utility.hh"
47 #include "base/bigint.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/inorder/resources/cache_unit.hh"
50 #include "cpu/inorder/resources/resource_list.hh"
51 #include "cpu/inorder/cpu.hh"
52 #include "cpu/inorder/first_stage.hh"
53 #include "cpu/inorder/inorder_dyn_inst.hh"
54 #include "cpu/inorder/pipeline_traits.hh"
55 #include "cpu/inorder/resource_pool.hh"
56 #include "cpu/inorder/thread_context.hh"
57 #include "cpu/inorder/thread_state.hh"
58 #include "cpu/activity.hh"
59 #include "cpu/base.hh"
60 #include "cpu/exetrace.hh"
61 #include "cpu/quiesce_event.hh"
62 #include "cpu/simple_thread.hh"
63 #include "cpu/thread_context.hh"
64 #include "debug/Activity.hh"
65 #include "debug/InOrderCPU.hh"
66 #include "debug/InOrderCachePort.hh"
67 #include "debug/Interrupt.hh"
68 #include "debug/Quiesce.hh"
69 #include "debug/RefCount.hh"
70 #include "debug/SkedCache.hh"
71 #include "params/InOrderCPU.hh"
72 #include "sim/full_system.hh"
73 #include "sim/process.hh"
74 #include "sim/stat_control.hh"
75 #include "sim/system.hh"
77 #if THE_ISA == ALPHA_ISA
78 #include "arch/alpha/osfpal.hh"
82 using namespace TheISA
;
83 using namespace ThePipeline
;
85 InOrderCPU::CachePort::CachePort(CacheUnit
*_cacheUnit
,
86 const std::string
& name
) :
87 CpuPort(_cacheUnit
->name() + name
, _cacheUnit
->cpu
),
92 InOrderCPU::CachePort::recvTimingResp(Packet
*pkt
)
95 DPRINTF(InOrderCachePort
, "Got error packet back for address: %x\n",
98 cacheUnit
->processCacheCompletion(pkt
);
104 InOrderCPU::CachePort::recvRetry()
106 cacheUnit
->recvRetry();
109 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
110 : Event(CPU_Tick_Pri
), cpu(c
)
115 InOrderCPU::TickEvent::process()
122 InOrderCPU::TickEvent::description() const
124 return "InOrderCPU tick event";
127 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
128 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
129 CPUEventPri event_pri
)
130 : Event(event_pri
), cpu(_cpu
)
132 setEvent(e_type
, fault
, _tid
, inst
);
136 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
139 "ActivateNextReadyThread",
145 "SquashFromMemStall",
150 InOrderCPU::CPUEvent::process()
152 switch (cpuEventType
)
155 cpu
->activateThread(tid
);
156 cpu
->resPool
->activateThread(tid
);
159 case ActivateNextReadyThread
:
160 cpu
->activateNextReadyThread();
163 case DeactivateThread
:
164 cpu
->deactivateThread(tid
);
165 cpu
->resPool
->deactivateThread(tid
);
169 cpu
->haltThread(tid
);
170 cpu
->resPool
->deactivateThread(tid
);
174 cpu
->suspendThread(tid
);
175 cpu
->resPool
->suspendThread(tid
);
178 case SquashFromMemStall
:
179 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
180 cpu
->resPool
->squashDueToMemStall(inst
, inst
->squashingStage
,
185 DPRINTF(InOrderCPU
, "Trapping CPU\n");
186 cpu
->trap(fault
, tid
, inst
);
187 cpu
->resPool
->trap(fault
, tid
, inst
);
188 cpu
->trapPending
[tid
] = false;
192 cpu
->syscall(inst
->syscallNum
, tid
);
193 cpu
->resPool
->trap(fault
, tid
, inst
);
197 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
200 cpu
->cpuEventRemoveList
.push(this);
206 InOrderCPU::CPUEvent::description() const
208 return "InOrderCPU event";
212 InOrderCPU::CPUEvent::scheduleEvent(Cycles delay
)
214 assert(!scheduled() || squashed());
215 cpu
->reschedule(this, cpu
->clockEdge(delay
), true);
219 InOrderCPU::CPUEvent::unscheduleEvent()
225 InOrderCPU::InOrderCPU(Params
*params
)
227 cpu_id(params
->cpu_id
),
231 stageWidth(params
->stageWidth
),
232 resPool(new ResourcePool(this, params
)),
233 isa(numThreads
, NULL
),
235 dataPort(resPool
->getDataUnit(), ".dcache_port"),
236 instPort(resPool
->getInstUnit(), ".icache_port"),
237 removeInstsThisCycle(false),
238 activityRec(params
->name
, NumStages
, 10, params
->activity
),
239 system(params
->system
),
245 deferRegistration(false/*params->deferRegistration*/),
246 stageTracing(params
->stageTracing
),
252 // Resize for Multithreading CPUs
253 thread
.resize(numThreads
);
255 ThreadID active_threads
= params
->workload
.size();
259 active_threads
= params
->workload
.size();
261 if (active_threads
> MaxThreads
) {
262 panic("Workload Size too large. Increase the 'MaxThreads'"
263 "in your InOrder implementation or "
264 "edit your workload size.");
268 if (active_threads
> 1) {
269 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
271 if (threadModel
== SMT
) {
272 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
273 } else if (threadModel
== SwitchOnCacheMiss
) {
274 DPRINTF(InOrderCPU
, "Setting Thread Model to "
275 "Switch On Cache Miss\n");
279 threadModel
= Single
;
283 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
284 isa
[tid
] = params
->isa
[tid
];
286 lastCommittedPC
[tid
].set(0);
289 // SMT is not supported in FS mode yet.
290 assert(numThreads
== 1);
291 thread
[tid
] = new Thread(this, 0, NULL
);
293 if (tid
< (ThreadID
)params
->workload
.size()) {
294 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
295 tid
, params
->workload
[tid
]->progName());
297 new Thread(this, tid
, params
->workload
[tid
]);
299 //Allocate Empty thread so M5 can use later
300 //when scheduling threads to CPU
301 Process
* dummy_proc
= params
->workload
[0];
302 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
305 // Eventually set this with parameters...
309 // Setup the TC that will serve as the interface to the threads/CPU.
310 InOrderThreadContext
*tc
= new InOrderThreadContext
;
312 tc
->thread
= thread
[tid
];
314 // Setup quiesce event.
315 this->thread
[tid
]->quiesceEvent
= new EndQuiesceEvent(tc
);
317 // Give the thread the TC.
318 thread
[tid
]->tc
= tc
;
319 thread
[tid
]->setFuncExeInst(0);
320 globalSeqNum
[tid
] = 1;
322 // Add the TC to the CPU's list of TC's.
323 this->threadContexts
.push_back(tc
);
326 // Initialize TimeBuffer Stage Queues
327 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
328 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
329 stageQueue
[stNum
]->id(stNum
);
333 // Set Up Pipeline Stages
334 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
336 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
338 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
340 pipelineStage
[stNum
]->setCPU(this);
341 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
342 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
344 // Take Care of 1st/Nth stages
346 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
347 if (stNum
< NumStages
- 1)
348 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
351 // Initialize thread specific variables
352 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
353 archRegDepMap
[tid
].setCPU(this);
355 nonSpecInstActive
[tid
] = false;
356 nonSpecSeqNum
[tid
] = 0;
358 squashSeqNum
[tid
] = MaxAddr
;
359 lastSquashCycle
[tid
] = 0;
361 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
362 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
365 // Define dummy instructions and resource requests to be used.
366 dummyInst
[tid
] = new InOrderDynInst(this,
372 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
376 // Use this dummy inst to force squashing behind every instruction
378 dummyTrapInst
[tid
] = new InOrderDynInst(this, NULL
, 0, 0, 0);
379 dummyTrapInst
[tid
]->seqNum
= 0;
380 dummyTrapInst
[tid
]->squashSeqNum
= 0;
381 dummyTrapInst
[tid
]->setTid(tid
);
384 trapPending
[tid
] = false;
388 // InOrderCPU always requires an interrupt controller.
389 if (!params
->defer_registration
&& !interrupts
) {
390 fatal("InOrderCPU %s has no interrupt controller.\n"
391 "Ensure createInterruptController() is called.\n", name());
394 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
395 dummyReqInst
->setSquashed();
396 dummyReqInst
->resetInstCount();
398 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
399 dummyBufferInst
->setSquashed();
400 dummyBufferInst
->resetInstCount();
402 endOfSkedIt
= skedCache
.end();
403 frontEndSked
= createFrontEndSked();
404 faultSked
= createFaultSked();
406 lastRunningCycle
= curCycle();
411 // Schedule First Tick Event, CPU will reschedule itself from here on out.
412 scheduleTickEvent(Cycles(0));
415 InOrderCPU::~InOrderCPU()
419 SkedCacheIt sked_it
= skedCache
.begin();
420 SkedCacheIt sked_end
= skedCache
.end();
422 while (sked_it
!= sked_end
) {
423 delete (*sked_it
).second
;
429 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
432 InOrderCPU::createFrontEndSked()
434 RSkedPtr res_sked
= new ResourceSked();
436 StageScheduler
F(res_sked
, stage_num
++);
437 StageScheduler
D(res_sked
, stage_num
++);
440 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
441 F
.needs(ICache
, FetchUnit::InitiateFetch
);
444 D
.needs(ICache
, FetchUnit::CompleteFetch
);
445 D
.needs(Decode
, DecodeUnit::DecodeInst
);
446 D
.needs(BPred
, BranchPredictor::PredictBranch
);
447 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
450 DPRINTF(SkedCache
, "Resource Sked created for instruction Front End\n");
456 InOrderCPU::createFaultSked()
458 RSkedPtr res_sked
= new ResourceSked();
459 StageScheduler
W(res_sked
, NumStages
- 1);
460 W
.needs(Grad
, GraduationUnit::CheckFault
);
461 DPRINTF(SkedCache
, "Resource Sked created for instruction Faults\n");
466 InOrderCPU::createBackEndSked(DynInstPtr inst
)
468 RSkedPtr res_sked
= lookupSked(inst
);
469 if (res_sked
!= NULL
) {
470 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
474 res_sked
= new ResourceSked();
477 int stage_num
= ThePipeline::BackEndStartStage
;
478 StageScheduler
X(res_sked
, stage_num
++);
479 StageScheduler
M(res_sked
, stage_num
++);
480 StageScheduler
W(res_sked
, stage_num
++);
482 if (!inst
->staticInst
) {
483 warn_once("Static Instruction Object Not Set. Can't Create"
484 " Back End Schedule");
489 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
490 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
491 if (!idx
|| !inst
->isStore()) {
492 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
496 //@todo: schedule non-spec insts to operate on this cycle
497 // as long as all previous insts are done
498 if ( inst
->isNonSpeculative() ) {
499 // skip execution of non speculative insts until later
500 } else if ( inst
->isMemRef() ) {
501 if ( inst
->isLoad() ) {
502 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
504 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
505 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
507 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
511 if (!inst
->isNonSpeculative()) {
512 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
513 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
516 if ( inst
->isLoad() ) {
517 M
.needs(DCache
, CacheUnit::InitiateReadData
);
519 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
520 } else if ( inst
->isStore() ) {
521 for (int i
= 1; i
< inst
->numSrcRegs(); i
++ ) {
522 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, i
);
524 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
525 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
527 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
532 if (!inst
->isNonSpeculative()) {
533 if ( inst
->isLoad() ) {
534 W
.needs(DCache
, CacheUnit::CompleteReadData
);
536 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
537 } else if ( inst
->isStore() ) {
538 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
540 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
543 // Finally, Execute Speculative Data
544 if (inst
->isMemRef()) {
545 if (inst
->isLoad()) {
546 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
547 W
.needs(DCache
, CacheUnit::InitiateReadData
);
549 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
550 W
.needs(DCache
, CacheUnit::CompleteReadData
);
552 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
553 } else if (inst
->isStore()) {
554 if ( inst
->numSrcRegs() >= 2 ) {
555 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
557 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
558 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
560 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
561 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
563 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
566 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
570 W
.needs(Grad
, GraduationUnit::CheckFault
);
572 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
573 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
576 if (inst
->isControl())
577 W
.needs(BPred
, BranchPredictor::UpdatePredictor
);
579 W
.needs(Grad
, GraduationUnit::GraduateInst
);
581 // Insert Back Schedule into our cache of
582 // resource schedules
583 addToSkedCache(inst
, res_sked
);
585 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
586 inst
->instName(), inst
->getMachInst());
593 InOrderCPU::regStats()
595 /* Register the Resource Pool's stats here.*/
598 /* Register for each Pipeline Stage */
599 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
600 pipelineStage
[stage_num
]->regStats();
603 /* Register any of the InOrderCPU's stats here.*/
605 .name(name() + ".instsPerContextSwitch")
606 .desc("Instructions Committed Per Context Switch")
607 .prereq(instsPerCtxtSwitch
);
610 .name(name() + ".contextSwitches")
611 .desc("Number of context switches");
614 .name(name() + ".comLoads")
615 .desc("Number of Load instructions committed");
618 .name(name() + ".comStores")
619 .desc("Number of Store instructions committed");
622 .name(name() + ".comBranches")
623 .desc("Number of Branches instructions committed");
626 .name(name() + ".comNops")
627 .desc("Number of Nop instructions committed");
630 .name(name() + ".comNonSpec")
631 .desc("Number of Non-Speculative instructions committed");
634 .name(name() + ".comInts")
635 .desc("Number of Integer instructions committed");
638 .name(name() + ".comFloats")
639 .desc("Number of Floating Point instructions committed");
642 .name(name() + ".timesIdled")
643 .desc("Number of times that the entire CPU went into an idle state and"
644 " unscheduled itself")
648 .name(name() + ".idleCycles")
649 .desc("Number of cycles cpu's stages were not processed");
652 .name(name() + ".runCycles")
653 .desc("Number of cycles cpu stages are processed.");
656 .name(name() + ".activity")
657 .desc("Percentage of cycles cpu is active")
659 activity
= (runCycles
/ numCycles
) * 100;
663 .name(name() + ".threadCycles")
664 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
667 .name(name() + ".smtCycles")
668 .desc("Total number of cycles that the CPU was in SMT-mode");
672 .name(name() + ".committedInsts")
673 .desc("Number of Instructions committed (Per-Thread)");
677 .name(name() + ".committedOps")
678 .desc("Number of Ops committed (Per-Thread)");
682 .name(name() + ".smtCommittedInsts")
683 .desc("Number of SMT Instructions committed (Per-Thread)");
686 .name(name() + ".committedInsts_total")
687 .desc("Number of Instructions committed (Total)");
690 .name(name() + ".cpi")
691 .desc("CPI: Cycles Per Instruction (Per-Thread)")
693 cpi
= numCycles
/ committedInsts
;
696 .name(name() + ".smt_cpi")
697 .desc("CPI: Total SMT-CPI")
699 smtCpi
= smtCycles
/ smtCommittedInsts
;
702 .name(name() + ".cpi_total")
703 .desc("CPI: Total CPI of All Threads")
705 totalCpi
= numCycles
/ totalCommittedInsts
;
708 .name(name() + ".ipc")
709 .desc("IPC: Instructions Per Cycle (Per-Thread)")
711 ipc
= committedInsts
/ numCycles
;
714 .name(name() + ".smt_ipc")
715 .desc("IPC: Total SMT-IPC")
717 smtIpc
= smtCommittedInsts
/ smtCycles
;
720 .name(name() + ".ipc_total")
721 .desc("IPC: Total IPC of All Threads")
723 totalIpc
= totalCommittedInsts
/ numCycles
;
732 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
736 checkForInterrupts();
738 bool pipes_idle
= true;
739 //Tick each of the stages
740 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
741 pipelineStage
[stNum
]->tick();
743 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
751 // Now advance the time buffers one tick
752 timeBuffer
.advance();
753 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
754 stageQueue
[sqNum
]->advance();
756 activityRec
.advance();
758 // Any squashed events, or insts then remove them now
759 cleanUpRemovedEvents();
760 cleanUpRemovedInsts();
762 // Re-schedule CPU for this cycle
763 if (!tickEvent
.scheduled()) {
764 if (_status
== SwitchedOut
) {
766 lastRunningCycle
= curCycle();
767 } else if (!activityRec
.active()) {
768 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
769 lastRunningCycle
= curCycle();
772 //Tick next_tick = curTick() + cycles(1);
773 //tickEvent.schedule(next_tick);
774 schedule(&tickEvent
, clockEdge(Cycles(1)));
775 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
776 clockEdge(Cycles(1)));
781 updateThreadPriority();
790 if (!params()->defer_registration
&&
791 system
->getMemoryMode() != Enums::timing
) {
792 fatal("The in-order CPU requires the memory system to be in "
796 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
797 // Set noSquashFromTC so that the CPU doesn't squash when initially
798 // setting up registers.
799 thread
[tid
]->noSquashFromTC
= true;
800 // Initialise the ThreadContext's memory proxies
801 thread
[tid
]->initMemProxies(thread
[tid
]->getTC());
804 if (FullSystem
&& !params()->defer_registration
) {
805 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
806 ThreadContext
*src_tc
= threadContexts
[tid
];
807 TheISA::initCPU(src_tc
, src_tc
->contextId());
811 // Clear noSquashFromTC.
812 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
813 thread
[tid
]->noSquashFromTC
= false;
815 // Call Initializiation Routine for Resource Pool
820 InOrderCPU::hwrei(ThreadID tid
)
822 #if THE_ISA == ALPHA_ISA
823 // Need to clear the lock flag upon returning from an interrupt.
824 setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG
, false, tid
);
826 thread
[tid
]->kernelStats
->hwrei();
827 // FIXME: XXX check for interrupts? XXX
835 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
837 #if THE_ISA == ALPHA_ISA
838 if (this->thread
[tid
]->kernelStats
)
839 this->thread
[tid
]->kernelStats
->callpal(palFunc
,
840 this->threadContexts
[tid
]);
845 if (--System::numSystemsRunning
== 0)
846 exitSimLoop("all cpus halted");
851 if (this->system
->breakpoint())
860 InOrderCPU::checkForInterrupts()
862 for (int i
= 0; i
< threadContexts
.size(); i
++) {
863 ThreadContext
*tc
= threadContexts
[i
];
865 if (interrupts
->checkInterrupts(tc
)) {
866 Fault interrupt
= interrupts
->getInterrupt(tc
);
868 if (interrupt
!= NoFault
) {
869 DPRINTF(Interrupt
, "Processing Intterupt for [tid:%i].\n",
872 ThreadID tid
= tc
->threadId();
873 interrupts
->updateIntrInfo(tc
);
875 // Squash from Last Stage in Pipeline
876 unsigned last_stage
= NumStages
- 1;
877 dummyTrapInst
[tid
]->squashingStage
= last_stage
;
878 pipelineStage
[last_stage
]->setupSquash(dummyTrapInst
[tid
],
881 // By default, setupSquash will always squash from stage + 1
882 pipelineStage
[BackEndStartStage
- 1]->setupSquash(dummyTrapInst
[tid
],
885 // Schedule Squash Through-out Resource Pool
886 resPool
->scheduleEvent(
887 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
,
888 dummyTrapInst
[tid
], Cycles(0));
890 // Finally, Setup Trap to happen at end of cycle
891 trapContext(interrupt
, tid
, dummyTrapInst
[tid
]);
898 InOrderCPU::getInterrupts()
900 // Check if there are any outstanding interrupts
901 return interrupts
->getInterrupt(threadContexts
[0]);
905 InOrderCPU::processInterrupts(Fault interrupt
)
907 // Check for interrupts here. For now can copy the code that
908 // exists within isa_fullsys_traits.hh. Also assume that thread 0
909 // is the one that handles the interrupts.
910 // @todo: Possibly consolidate the interrupt checking code.
911 // @todo: Allow other threads to handle interrupts.
913 assert(interrupt
!= NoFault
);
914 interrupts
->updateIntrInfo(threadContexts
[0]);
916 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
918 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
919 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
923 InOrderCPU::trapContext(Fault fault
, ThreadID tid
, DynInstPtr inst
,
926 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
927 trapPending
[tid
] = true;
931 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
933 fault
->invoke(tcBase(tid
), inst
->staticInst
);
934 removePipelineStalls(tid
);
938 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
,
941 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
946 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
949 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
951 // Squash all instructions in each stage including
952 // instruction that caused the squash (seq_num - 1)
953 // NOTE: The stage bandwidth needs to be cleared so thats why
954 // the stalling instruction is squashed as well. The stalled
955 // instruction is previously placed in another intermediate buffer
956 // while it's stall is being handled.
957 InstSeqNum squash_seq_num
= seq_num
- 1;
959 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
960 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
965 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
966 ThreadID tid
, DynInstPtr inst
,
967 Cycles delay
, CPUEventPri event_pri
)
969 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
972 Tick sked_tick
= clockEdge(delay
);
973 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
974 eventNames
[c_event
], curTick() + delay
, tid
);
975 schedule(cpu_event
, sked_tick
);
977 // Broadcast event to the Resource Pool
978 // Need to reset tid just in case this is a dummy instruction
980 // @todo: Is this really right? Should the delay not be passed on?
981 resPool
->scheduleEvent(c_event
, inst
, Cycles(0), 0, tid
);
985 InOrderCPU::isThreadActive(ThreadID tid
)
987 list
<ThreadID
>::iterator isActive
=
988 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
990 return (isActive
!= activeThreads
.end());
994 InOrderCPU::isThreadReady(ThreadID tid
)
996 list
<ThreadID
>::iterator isReady
=
997 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
999 return (isReady
!= readyThreads
.end());
1003 InOrderCPU::isThreadSuspended(ThreadID tid
)
1005 list
<ThreadID
>::iterator isSuspended
=
1006 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
1008 return (isSuspended
!= suspendedThreads
.end());
1012 InOrderCPU::activateNextReadyThread()
1014 if (readyThreads
.size() >= 1) {
1015 ThreadID ready_tid
= readyThreads
.front();
1017 // Activate in Pipeline
1018 activateThread(ready_tid
);
1020 // Activate in Resource Pool
1021 resPool
->activateThread(ready_tid
);
1023 list
<ThreadID
>::iterator ready_it
=
1024 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
1025 readyThreads
.erase(ready_it
);
1028 "Attempting to activate new thread, but No Ready Threads to"
1031 "Unable to switch to next active thread.\n");
1036 InOrderCPU::activateThread(ThreadID tid
)
1038 if (isThreadSuspended(tid
)) {
1040 "Removing [tid:%i] from suspended threads list.\n", tid
);
1042 list
<ThreadID
>::iterator susp_it
=
1043 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
1045 suspendedThreads
.erase(susp_it
);
1048 if (threadModel
== SwitchOnCacheMiss
&&
1049 numActiveThreads() == 1) {
1051 "Ignoring activation of [tid:%i], since [tid:%i] is "
1052 "already running.\n", tid
, activeThreadId());
1054 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
1057 readyThreads
.push_back(tid
);
1059 } else if (!isThreadActive(tid
)) {
1061 "Adding [tid:%i] to active threads list.\n", tid
);
1062 activeThreads
.push_back(tid
);
1064 activateThreadInPipeline(tid
);
1066 thread
[tid
]->lastActivate
= curTick();
1068 tcBase(tid
)->setStatus(ThreadContext::Active
);
1077 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
1079 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
1080 pipelineStage
[stNum
]->activateThread(tid
);
1085 InOrderCPU::deactivateContext(ThreadID tid
, Cycles delay
)
1087 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
1089 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1091 // Be sure to signal that there's some activity so the CPU doesn't
1092 // deschedule itself.
1093 activityRec
.activity();
1099 InOrderCPU::deactivateThread(ThreadID tid
)
1101 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
1103 if (isThreadActive(tid
)) {
1104 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
1106 list
<ThreadID
>::iterator thread_it
=
1107 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
1109 removePipelineStalls(*thread_it
);
1111 activeThreads
.erase(thread_it
);
1113 // Ideally, this should be triggered from the
1114 // suspendContext/Thread functions
1115 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1118 assert(!isThreadActive(tid
));
1122 InOrderCPU::removePipelineStalls(ThreadID tid
)
1124 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1127 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1128 pipelineStage
[stNum
]->removeStalls(tid
);
1134 InOrderCPU::updateThreadPriority()
1136 if (activeThreads
.size() > 1)
1138 //DEFAULT TO ROUND ROBIN SCHEME
1139 //e.g. Move highest priority to end of thread list
1140 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1142 unsigned high_thread
= *list_begin
;
1144 activeThreads
.erase(list_begin
);
1146 activeThreads
.push_back(high_thread
);
1151 InOrderCPU::tickThreadStats()
1153 /** Keep track of cycles that each thread is active */
1154 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1155 while (thread_it
!= activeThreads
.end()) {
1156 threadCycles
[*thread_it
]++;
1160 // Keep track of cycles where SMT is active
1161 if (activeThreads
.size() > 1) {
1167 InOrderCPU::activateContext(ThreadID tid
, Cycles delay
)
1169 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1172 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1174 // Be sure to signal that there's some activity so the CPU doesn't
1175 // deschedule itself.
1176 activityRec
.activity();
1182 InOrderCPU::activateNextReadyContext(Cycles delay
)
1184 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1186 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1187 delay
, ActivateNextReadyThread_Pri
);
1189 // Be sure to signal that there's some activity so the CPU doesn't
1190 // deschedule itself.
1191 activityRec
.activity();
1197 InOrderCPU::haltContext(ThreadID tid
)
1199 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1201 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
]);
1203 activityRec
.activity();
1207 InOrderCPU::haltThread(ThreadID tid
)
1209 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1210 deactivateThread(tid
);
1211 squashThreadInPipeline(tid
);
1212 haltedThreads
.push_back(tid
);
1214 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1216 if (threadModel
== SwitchOnCacheMiss
) {
1217 activateNextReadyContext();
1222 InOrderCPU::suspendContext(ThreadID tid
)
1224 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
]);
1228 InOrderCPU::suspendThread(ThreadID tid
)
1230 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1232 deactivateThread(tid
);
1233 suspendedThreads
.push_back(tid
);
1234 thread
[tid
]->lastSuspend
= curTick();
1236 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1240 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1242 //Squash all instructions in each stage
1243 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1244 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1249 InOrderCPU::getPipeStage(int stage_num
)
1251 return pipelineStage
[stage_num
];
1256 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1258 if (reg_idx
< FP_Base_DepTag
) {
1260 return isa
[tid
]->flattenIntIndex(reg_idx
);
1261 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1262 reg_type
= FloatType
;
1263 reg_idx
-= FP_Base_DepTag
;
1264 return isa
[tid
]->flattenFloatIndex(reg_idx
);
1266 reg_type
= MiscType
;
1267 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1272 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1274 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1275 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1277 return intRegs
[tid
][reg_idx
];
1281 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1283 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1284 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1286 return floatRegs
.f
[tid
][reg_idx
];
1290 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1292 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1293 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1295 return floatRegs
.i
[tid
][reg_idx
];
1299 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1301 if (reg_idx
== TheISA::ZeroReg
) {
1302 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1303 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1306 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1309 intRegs
[tid
][reg_idx
] = val
;
1315 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1317 floatRegs
.f
[tid
][reg_idx
] = val
;
1318 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1321 floatRegs
.i
[tid
][reg_idx
],
1322 floatRegs
.f
[tid
][reg_idx
]);
1327 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1329 floatRegs
.i
[tid
][reg_idx
] = val
;
1330 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1333 floatRegs
.i
[tid
][reg_idx
],
1334 floatRegs
.f
[tid
][reg_idx
]);
1338 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1340 // If Default value is set, then retrieve target thread
1341 if (tid
== InvalidThreadID
) {
1342 tid
= TheISA::getTargetThread(tcBase(tid
));
1345 if (reg_idx
< FP_Base_DepTag
) {
1346 // Integer Register File
1347 return readIntReg(reg_idx
, tid
);
1348 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1349 // Float Register File
1350 reg_idx
-= FP_Base_DepTag
;
1351 return readFloatRegBits(reg_idx
, tid
);
1353 reg_idx
-= Ctrl_Base_DepTag
;
1354 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1358 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1361 // If Default value is set, then retrieve target thread
1362 if (tid
== InvalidThreadID
) {
1363 tid
= TheISA::getTargetThread(tcBase(tid
));
1366 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1367 setIntReg(reg_idx
, val
, tid
);
1368 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1369 reg_idx
-= FP_Base_DepTag
;
1370 setFloatRegBits(reg_idx
, val
, tid
);
1372 reg_idx
-= Ctrl_Base_DepTag
;
1373 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1378 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1380 return isa
[tid
]->readMiscRegNoEffect(misc_reg
);
1384 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1386 return isa
[tid
]->readMiscReg(misc_reg
, tcBase(tid
));
1390 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1392 isa
[tid
]->setMiscRegNoEffect(misc_reg
, val
);
1396 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1398 isa
[tid
]->setMiscReg(misc_reg
, val
, tcBase(tid
));
1403 InOrderCPU::addInst(DynInstPtr inst
)
1405 ThreadID tid
= inst
->readTid();
1407 instList
[tid
].push_back(inst
);
1409 return --(instList
[tid
].end());
1413 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1415 ListIt it
= instList
[tid
].begin();
1416 ListIt end
= instList
[tid
].end();
1419 if ((*it
)->seqNum
== seq_num
)
1421 else if ((*it
)->seqNum
> seq_num
)
1427 return instList
[tid
].end();
1431 InOrderCPU::updateContextSwitchStats()
1433 // Set Average Stat Here, then reset to 0
1434 instsPerCtxtSwitch
= instsPerSwitch
;
1440 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1442 // Set the nextPC to be fetched if this is the last instruction
1445 // This contributes to the precise state of the CPU
1446 // which can be used when restoring a thread to the CPU after after any
1447 // type of context switching activity (fork, exception, etc.)
1448 TheISA::PCState comm_pc
= inst
->pcState();
1449 lastCommittedPC
[tid
] = comm_pc
;
1450 TheISA::advancePC(comm_pc
, inst
->staticInst
);
1451 pcState(comm_pc
, tid
);
1453 //@todo: may be unnecessary with new-ISA-specific branch handling code
1454 if (inst
->isControl()) {
1455 thread
[tid
]->lastGradIsBranch
= true;
1456 thread
[tid
]->lastBranchPC
= inst
->pcState();
1457 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1459 thread
[tid
]->lastGradIsBranch
= false;
1463 // Finalize Trace Data For Instruction
1464 if (inst
->traceData
) {
1465 //inst->traceData->setCycle(curTick());
1466 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1467 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1468 inst
->traceData
->dump();
1469 delete inst
->traceData
;
1470 inst
->traceData
= NULL
;
1473 // Increment active thread's instruction count
1476 // Increment thread-state's instruction count
1477 thread
[tid
]->numInst
++;
1478 thread
[tid
]->numOp
++;
1480 // Increment thread-state's instruction stats
1481 thread
[tid
]->numInsts
++;
1482 thread
[tid
]->numOps
++;
1484 // Count committed insts per thread stats
1485 if (!inst
->isMicroop() || inst
->isLastMicroop()) {
1486 committedInsts
[tid
]++;
1488 // Count total insts committed stat
1489 totalCommittedInsts
++;
1492 committedOps
[tid
]++;
1494 // Count SMT-committed insts per thread stat
1495 if (numActiveThreads() > 1) {
1496 if (!inst
->isMicroop() || inst
->isLastMicroop())
1497 smtCommittedInsts
[tid
]++;
1500 // Instruction-Mix Stats
1501 if (inst
->isLoad()) {
1503 } else if (inst
->isStore()) {
1505 } else if (inst
->isControl()) {
1507 } else if (inst
->isNop()) {
1509 } else if (inst
->isNonSpeculative()) {
1511 } else if (inst
->isInteger()) {
1513 } else if (inst
->isFloating()) {
1517 // Check for instruction-count-based events.
1518 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numOp
);
1520 // Finally, remove instruction from CPU
1524 // currently unused function, but substitute repetitive code w/this function
1527 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1529 removeInstsThisCycle
= true;
1530 if (!inst
->isRemoveList()) {
1531 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1532 "[sn:%lli] to remove list\n",
1533 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1534 inst
->setRemoveList();
1535 removeList
.push(inst
->getInstListIt());
1537 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1538 "[sn:%lli], already remove list\n",
1539 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1545 InOrderCPU::removeInst(DynInstPtr inst
)
1547 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1549 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1551 removeInstsThisCycle
= true;
1553 // Remove the instruction.
1554 if (!inst
->isRemoveList()) {
1555 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1556 "[sn:%lli] to remove list\n",
1557 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1558 inst
->setRemoveList();
1559 removeList
.push(inst
->getInstListIt());
1561 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1562 "[sn:%lli], already on remove list\n",
1563 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1569 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1571 //assert(!instList[tid].empty());
1573 removeInstsThisCycle
= true;
1575 ListIt inst_iter
= instList
[tid
].end();
1579 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1580 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1581 tid
, seq_num
, (*inst_iter
)->seqNum
);
1583 while ((*inst_iter
)->seqNum
> seq_num
) {
1585 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1587 squashInstIt(inst_iter
, tid
);
1598 InOrderCPU::squashInstIt(const ListIt inst_it
, ThreadID tid
)
1600 DynInstPtr inst
= (*inst_it
);
1601 if (inst
->threadNumber
== tid
) {
1602 DPRINTF(InOrderCPU
, "Squashing instruction, "
1603 "[tid:%i] [sn:%lli] PC %s\n",
1608 inst
->setSquashed();
1609 archRegDepMap
[tid
].remove(inst
);
1611 if (!inst
->isRemoveList()) {
1612 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1613 "[sn:%lli] to remove list\n",
1614 inst
->threadNumber
, inst
->pcState(),
1616 inst
->setRemoveList();
1617 removeList
.push(inst_it
);
1619 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1620 " PC %s [sn:%lli], already on remove list\n",
1621 inst
->threadNumber
, inst
->pcState(),
1631 InOrderCPU::cleanUpRemovedInsts()
1633 while (!removeList
.empty()) {
1634 DPRINTF(InOrderCPU
, "Removing instruction, "
1635 "[tid:%i] [sn:%lli] PC %s\n",
1636 (*removeList
.front())->threadNumber
,
1637 (*removeList
.front())->seqNum
,
1638 (*removeList
.front())->pcState());
1640 DynInstPtr inst
= *removeList
.front();
1641 ThreadID tid
= inst
->threadNumber
;
1643 // Remove From Register Dependency Map, If Necessary
1644 // archRegDepMap[tid].remove(inst);
1646 // Clear if Non-Speculative
1647 if (inst
->staticInst
&&
1648 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1649 nonSpecInstActive
[tid
] == true) {
1650 nonSpecInstActive
[tid
] = false;
1653 inst
->onInstList
= false;
1655 instList
[tid
].erase(removeList
.front());
1660 removeInstsThisCycle
= false;
1664 InOrderCPU::cleanUpRemovedEvents()
1666 while (!cpuEventRemoveList
.empty()) {
1667 Event
*cpu_event
= cpuEventRemoveList
.front();
1668 cpuEventRemoveList
.pop();
1675 InOrderCPU::dumpInsts()
1679 ListIt inst_list_it
= instList
[0].begin();
1681 cprintf("Dumping Instruction List\n");
1683 while (inst_list_it
!= instList
[0].end()) {
1684 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1686 num
, (*inst_list_it
)->pcState(),
1687 (*inst_list_it
)->threadNumber
,
1688 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1689 (*inst_list_it
)->isSquashed());
1696 InOrderCPU::wakeCPU()
1698 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1699 DPRINTF(Activity
, "CPU already running.\n");
1703 DPRINTF(Activity
, "Waking up CPU\n");
1705 Tick extra_cycles
= curCycle() - lastRunningCycle
;
1706 if (extra_cycles
!= 0)
1709 idleCycles
+= extra_cycles
;
1710 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1711 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1714 numCycles
+= extra_cycles
;
1716 schedule(&tickEvent
, nextCycle());
1719 // Lots of copied full system code...place into BaseCPU class?
1721 InOrderCPU::wakeup()
1723 if (thread
[0]->status() != ThreadContext::Suspended
)
1728 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1729 threadContexts
[0]->activate();
1733 InOrderCPU::syscallContext(Fault fault
, ThreadID tid
, DynInstPtr inst
,
1736 // Syscall must be non-speculative, so squash from last stage
1737 unsigned squash_stage
= NumStages
- 1;
1738 inst
->setSquashInfo(squash_stage
);
1740 // Squash In Pipeline Stage
1741 pipelineStage
[squash_stage
]->setupSquash(inst
, tid
);
1743 // Schedule Squash Through-out Resource Pool
1744 resPool
->scheduleEvent(
1745 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
, inst
,
1747 scheduleCpuEvent(Syscall
, fault
, tid
, inst
, delay
, Syscall_Pri
);
1751 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1753 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1755 DPRINTF(Activity
,"Activity: syscall() called.\n");
1757 // Temporarily increase this by one to account for the syscall
1759 ++(this->thread
[tid
]->funcExeInst
);
1761 // Execute the actual syscall.
1762 this->thread
[tid
]->syscall(callnum
);
1764 // Decrease funcExeInst by one as the normal commit will handle
1766 --(this->thread
[tid
]->funcExeInst
);
1768 // Clear Non-Speculative Block Variable
1769 nonSpecInstActive
[tid
] = false;
1773 InOrderCPU::getITBPtr()
1775 CacheUnit
*itb_res
= resPool
->getInstUnit();
1776 return itb_res
->tlb();
1781 InOrderCPU::getDTBPtr()
1783 return resPool
->getDataUnit()->tlb();
1787 InOrderCPU::getDecoderPtr(unsigned tid
)
1789 return resPool
->getInstUnit()->decoder
[tid
];
1793 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1794 uint8_t *data
, unsigned size
, unsigned flags
)
1796 return resPool
->getDataUnit()->read(inst
, addr
, data
, size
, flags
);
1800 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1801 Addr addr
, unsigned flags
, uint64_t *write_res
)
1803 return resPool
->getDataUnit()->write(inst
, data
, size
, addr
, flags
,