2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/utility.hh"
35 #include "base/bigint.hh"
36 #include "config/full_system.hh"
37 #include "config/the_isa.hh"
38 #include "cpu/inorder/resources/resource_list.hh"
39 #include "cpu/inorder/cpu.hh"
40 #include "cpu/inorder/first_stage.hh"
41 #include "cpu/inorder/inorder_dyn_inst.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/resource_pool.hh"
44 #include "cpu/inorder/thread_context.hh"
45 #include "cpu/inorder/thread_state.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/base.hh"
48 #include "cpu/exetrace.hh"
49 #include "cpu/simple_thread.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/Activity.hh"
52 #include "debug/InOrderCPU.hh"
53 #include "debug/RefCount.hh"
54 #include "debug/SkedCache.hh"
55 #include "mem/translating_port.hh"
56 #include "params/InOrderCPU.hh"
57 #include "sim/process.hh"
58 #include "sim/stat_control.hh"
61 #include "cpu/quiesce_event.hh"
62 #include "sim/system.hh"
65 #if THE_ISA == ALPHA_ISA
66 #include "arch/alpha/osfpal.hh"
70 using namespace TheISA
;
71 using namespace ThePipeline
;
73 InOrderCPU::TickEvent::TickEvent(InOrderCPU
*c
)
74 : Event(CPU_Tick_Pri
), cpu(c
)
79 InOrderCPU::TickEvent::process()
86 InOrderCPU::TickEvent::description()
88 return "InOrderCPU tick event";
91 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU
*_cpu
, CPUEventType e_type
,
92 Fault fault
, ThreadID _tid
, DynInstPtr inst
,
93 CPUEventPri event_pri
)
94 : Event(event_pri
), cpu(_cpu
)
96 setEvent(e_type
, fault
, _tid
, inst
);
100 std::string
InOrderCPU::eventNames
[NumCPUEvents
] =
103 "ActivateNextReadyThread",
109 "SquashFromMemStall",
114 InOrderCPU::CPUEvent::process()
116 switch (cpuEventType
)
119 cpu
->activateThread(tid
);
120 cpu
->resPool
->activateThread(tid
);
123 case ActivateNextReadyThread
:
124 cpu
->activateNextReadyThread();
127 case DeactivateThread
:
128 cpu
->deactivateThread(tid
);
129 cpu
->resPool
->deactivateThread(tid
);
133 cpu
->haltThread(tid
);
134 cpu
->resPool
->deactivateThread(tid
);
138 cpu
->suspendThread(tid
);
139 cpu
->resPool
->suspendThread(tid
);
142 case SquashFromMemStall
:
143 cpu
->squashDueToMemStall(inst
->squashingStage
, inst
->seqNum
, tid
);
144 cpu
->resPool
->squashDueToMemStall(inst
, inst
->squashingStage
,
149 DPRINTF(InOrderCPU
, "Trapping CPU\n");
150 cpu
->trap(fault
, tid
, inst
);
151 cpu
->resPool
->trap(fault
, tid
, inst
);
156 cpu
->syscall(inst
->syscallNum
, tid
);
157 cpu
->resPool
->trap(fault
, tid
, inst
);
161 fatal("Unrecognized Event Type %s", eventNames
[cpuEventType
]);
164 cpu
->cpuEventRemoveList
.push(this);
170 InOrderCPU::CPUEvent::description()
172 return "InOrderCPU event";
176 InOrderCPU::CPUEvent::scheduleEvent(int delay
)
178 assert(!scheduled() || squashed());
179 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
183 InOrderCPU::CPUEvent::unscheduleEvent()
189 InOrderCPU::InOrderCPU(Params
*params
)
191 cpu_id(params
->cpu_id
),
195 stageWidth(params
->stageWidth
),
197 removeInstsThisCycle(false),
198 activityRec(params
->name
, NumStages
, 10, params
->activity
),
200 system(params
->system
),
201 #endif // FULL_SYSTEM
207 deferRegistration(false/*params->deferRegistration*/),
208 stageTracing(params
->stageTracing
),
212 ThreadID active_threads
;
215 resPool
= new ResourcePool(this, params
);
217 // Resize for Multithreading CPUs
218 thread
.resize(numThreads
);
223 active_threads
= params
->workload
.size();
225 if (active_threads
> MaxThreads
) {
226 panic("Workload Size too large. Increase the 'MaxThreads'"
227 "in your InOrder implementation or "
228 "edit your workload size.");
232 if (active_threads
> 1) {
233 threadModel
= (InOrderCPU::ThreadModel
) params
->threadModel
;
235 if (threadModel
== SMT
) {
236 DPRINTF(InOrderCPU
, "Setting Thread Model to SMT.\n");
237 } else if (threadModel
== SwitchOnCacheMiss
) {
238 DPRINTF(InOrderCPU
, "Setting Thread Model to "
239 "Switch On Cache Miss\n");
243 threadModel
= Single
;
250 // Bind the fetch & data ports from the resource pool.
251 fetchPortIdx
= resPool
->getPortIdx(params
->fetchMemPort
);
252 if (fetchPortIdx
== 0) {
253 fatal("Unable to find port to fetch instructions from.\n");
256 dataPortIdx
= resPool
->getPortIdx(params
->dataMemPort
);
257 if (dataPortIdx
== 0) {
258 fatal("Unable to find port for data.\n");
261 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
263 lastCommittedPC
[tid
].set(0);
266 // SMT is not supported in FS mode yet.
267 assert(numThreads
== 1);
268 thread
[tid
] = new Thread(this, 0);
270 if (tid
< (ThreadID
)params
->workload
.size()) {
271 DPRINTF(InOrderCPU
, "Workload[%i] process is %#x\n",
272 tid
, params
->workload
[tid
]->prog_fname
);
274 new Thread(this, tid
, params
->workload
[tid
]);
276 //Allocate Empty thread so M5 can use later
277 //when scheduling threads to CPU
278 Process
* dummy_proc
= params
->workload
[0];
279 thread
[tid
] = new Thread(this, tid
, dummy_proc
);
282 // Eventually set this with parameters...
286 // Setup the TC that will serve as the interface to the threads/CPU.
287 InOrderThreadContext
*tc
= new InOrderThreadContext
;
289 tc
->thread
= thread
[tid
];
292 // Setup quiesce event.
293 this->thread
[tid
]->quiesceEvent
= new EndQuiesceEvent(tc
);
296 // Give the thread the TC.
297 thread
[tid
]->tc
= tc
;
298 thread
[tid
]->setFuncExeInst(0);
299 globalSeqNum
[tid
] = 1;
301 // Add the TC to the CPU's list of TC's.
302 this->threadContexts
.push_back(tc
);
305 // Initialize TimeBuffer Stage Queues
306 for (int stNum
=0; stNum
< NumStages
- 1; stNum
++) {
307 stageQueue
[stNum
] = new StageQueue(NumStages
, NumStages
);
308 stageQueue
[stNum
]->id(stNum
);
312 // Set Up Pipeline Stages
313 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
315 pipelineStage
[stNum
] = new FirstStage(params
, stNum
);
317 pipelineStage
[stNum
] = new PipelineStage(params
, stNum
);
319 pipelineStage
[stNum
]->setCPU(this);
320 pipelineStage
[stNum
]->setActiveThreads(&activeThreads
);
321 pipelineStage
[stNum
]->setTimeBuffer(&timeBuffer
);
323 // Take Care of 1st/Nth stages
325 pipelineStage
[stNum
]->setPrevStageQueue(stageQueue
[stNum
- 1]);
326 if (stNum
< NumStages
- 1)
327 pipelineStage
[stNum
]->setNextStageQueue(stageQueue
[stNum
]);
330 // Initialize thread specific variables
331 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
332 archRegDepMap
[tid
].setCPU(this);
334 nonSpecInstActive
[tid
] = false;
335 nonSpecSeqNum
[tid
] = 0;
337 squashSeqNum
[tid
] = MaxAddr
;
338 lastSquashCycle
[tid
] = 0;
340 memset(intRegs
[tid
], 0, sizeof(intRegs
[tid
]));
341 memset(floatRegs
.i
[tid
], 0, sizeof(floatRegs
.i
[tid
]));
344 // Define dummy instructions and resource requests to be used.
345 dummyInst
[tid
] = new InOrderDynInst(this,
351 dummyReq
[tid
] = new ResourceRequest(resPool
->getResource(0));
354 // Use this dummy inst to force squashing behind every instruction
356 dummyTrapInst
[tid
] = new InOrderDynInst(this, NULL
, 0, 0, 0);
357 dummyTrapInst
[tid
]->seqNum
= 0;
358 dummyTrapInst
[tid
]->squashSeqNum
= 0;
359 dummyTrapInst
[tid
]->setTid(tid
);
364 dummyReqInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
365 dummyReqInst
->setSquashed();
366 dummyReqInst
->resetInstCount();
368 dummyBufferInst
= new InOrderDynInst(this, NULL
, 0, 0, 0);
369 dummyBufferInst
->setSquashed();
370 dummyBufferInst
->resetInstCount();
372 endOfSkedIt
= skedCache
.end();
373 frontEndSked
= createFrontEndSked();
374 faultSked
= createFaultSked();
376 lastRunningCycle
= curTick();
381 // Schedule First Tick Event, CPU will reschedule itself from here on out.
382 scheduleTickEvent(0);
385 InOrderCPU::~InOrderCPU()
389 SkedCacheIt sked_it
= skedCache
.begin();
390 SkedCacheIt sked_end
= skedCache
.end();
392 while (sked_it
!= sked_end
) {
393 delete (*sked_it
).second
;
399 m5::hash_map
<InOrderCPU::SkedID
, ThePipeline::RSkedPtr
> InOrderCPU::skedCache
;
402 InOrderCPU::createFrontEndSked()
404 RSkedPtr res_sked
= new ResourceSked();
406 StageScheduler
F(res_sked
, stage_num
++);
407 StageScheduler
D(res_sked
, stage_num
++);
410 F
.needs(FetchSeq
, FetchSeqUnit::AssignNextPC
);
411 F
.needs(ICache
, FetchUnit::InitiateFetch
);
414 D
.needs(ICache
, FetchUnit::CompleteFetch
);
415 D
.needs(Decode
, DecodeUnit::DecodeInst
);
416 D
.needs(BPred
, BranchPredictor::PredictBranch
);
417 D
.needs(FetchSeq
, FetchSeqUnit::UpdateTargetPC
);
420 DPRINTF(SkedCache
, "Resource Sked created for instruction Front End\n");
426 InOrderCPU::createFaultSked()
428 RSkedPtr res_sked
= new ResourceSked();
429 StageScheduler
W(res_sked
, NumStages
- 1);
430 W
.needs(Grad
, GraduationUnit::CheckFault
);
431 DPRINTF(SkedCache
, "Resource Sked created for instruction Faults\n");
436 InOrderCPU::createBackEndSked(DynInstPtr inst
)
438 RSkedPtr res_sked
= lookupSked(inst
);
439 if (res_sked
!= NULL
) {
440 DPRINTF(SkedCache
, "Found %s in sked cache.\n",
444 res_sked
= new ResourceSked();
447 int stage_num
= ThePipeline::BackEndStartStage
;
448 StageScheduler
X(res_sked
, stage_num
++);
449 StageScheduler
M(res_sked
, stage_num
++);
450 StageScheduler
W(res_sked
, stage_num
++);
452 if (!inst
->staticInst
) {
453 warn_once("Static Instruction Object Not Set. Can't Create"
454 " Back End Schedule");
459 X
.needs(RegManager
, UseDefUnit::MarkDestRegs
);
460 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
461 if (!idx
|| !inst
->isStore()) {
462 X
.needs(RegManager
, UseDefUnit::ReadSrcReg
, idx
);
466 //@todo: schedule non-spec insts to operate on this cycle
467 // as long as all previous insts are done
468 if ( inst
->isNonSpeculative() ) {
469 // skip execution of non speculative insts until later
470 } else if ( inst
->isMemRef() ) {
471 if ( inst
->isLoad() ) {
472 X
.needs(AGEN
, AGENUnit::GenerateAddr
);
474 } else if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
475 X
.needs(MDU
, MultDivUnit::StartMultDiv
);
477 X
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
481 if (!inst
->isNonSpeculative()) {
482 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
483 M
.needs(MDU
, MultDivUnit::EndMultDiv
);
486 if ( inst
->isLoad() ) {
487 M
.needs(DCache
, CacheUnit::InitiateReadData
);
489 M
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
490 } else if ( inst
->isStore() ) {
491 for (int i
= 1; i
< inst
->numSrcRegs(); i
++ ) {
492 M
.needs(RegManager
, UseDefUnit::ReadSrcReg
, i
);
494 M
.needs(AGEN
, AGENUnit::GenerateAddr
);
495 M
.needs(DCache
, CacheUnit::InitiateWriteData
);
497 M
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
502 if (!inst
->isNonSpeculative()) {
503 if ( inst
->isLoad() ) {
504 W
.needs(DCache
, CacheUnit::CompleteReadData
);
506 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
507 } else if ( inst
->isStore() ) {
508 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
510 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
513 // Finally, Execute Speculative Data
514 if (inst
->isMemRef()) {
515 if (inst
->isLoad()) {
516 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
517 W
.needs(DCache
, CacheUnit::InitiateReadData
);
519 W
.needs(DCache
, CacheUnit::InitSecondSplitRead
);
520 W
.needs(DCache
, CacheUnit::CompleteReadData
);
522 W
.needs(DCache
, CacheUnit::CompleteSecondSplitRead
);
523 } else if (inst
->isStore()) {
524 if ( inst
->numSrcRegs() >= 2 ) {
525 W
.needs(RegManager
, UseDefUnit::ReadSrcReg
, 1);
527 W
.needs(AGEN
, AGENUnit::GenerateAddr
);
528 W
.needs(DCache
, CacheUnit::InitiateWriteData
);
530 W
.needs(DCache
, CacheUnit::InitSecondSplitWrite
);
531 W
.needs(DCache
, CacheUnit::CompleteWriteData
);
533 W
.needs(DCache
, CacheUnit::CompleteSecondSplitWrite
);
536 W
.needs(ExecUnit
, ExecutionUnit::ExecuteInst
);
540 W
.needs(Grad
, GraduationUnit::CheckFault
);
542 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
543 W
.needs(RegManager
, UseDefUnit::WriteDestReg
, idx
);
546 if (inst
->isControl())
547 W
.needs(BPred
, BranchPredictor::UpdatePredictor
);
549 W
.needs(Grad
, GraduationUnit::GraduateInst
);
551 // Insert Back Schedule into our cache of
552 // resource schedules
553 addToSkedCache(inst
, res_sked
);
555 DPRINTF(SkedCache
, "Back End Sked Created for instruction: %s (%08p)\n",
556 inst
->instName(), inst
->getMachInst());
563 InOrderCPU::regStats()
565 /* Register the Resource Pool's stats here.*/
568 /* Register for each Pipeline Stage */
569 for (int stage_num
=0; stage_num
< ThePipeline::NumStages
; stage_num
++) {
570 pipelineStage
[stage_num
]->regStats();
573 /* Register any of the InOrderCPU's stats here.*/
575 .name(name() + ".instsPerContextSwitch")
576 .desc("Instructions Committed Per Context Switch")
577 .prereq(instsPerCtxtSwitch
);
580 .name(name() + ".contextSwitches")
581 .desc("Number of context switches");
584 .name(name() + ".comLoads")
585 .desc("Number of Load instructions committed");
588 .name(name() + ".comStores")
589 .desc("Number of Store instructions committed");
592 .name(name() + ".comBranches")
593 .desc("Number of Branches instructions committed");
596 .name(name() + ".comNops")
597 .desc("Number of Nop instructions committed");
600 .name(name() + ".comNonSpec")
601 .desc("Number of Non-Speculative instructions committed");
604 .name(name() + ".comInts")
605 .desc("Number of Integer instructions committed");
608 .name(name() + ".comFloats")
609 .desc("Number of Floating Point instructions committed");
612 .name(name() + ".timesIdled")
613 .desc("Number of times that the entire CPU went into an idle state and"
614 " unscheduled itself")
618 .name(name() + ".idleCycles")
619 .desc("Number of cycles cpu's stages were not processed");
622 .name(name() + ".runCycles")
623 .desc("Number of cycles cpu stages are processed.");
626 .name(name() + ".activity")
627 .desc("Percentage of cycles cpu is active")
629 activity
= (runCycles
/ numCycles
) * 100;
633 .name(name() + ".threadCycles")
634 .desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
637 .name(name() + ".smtCycles")
638 .desc("Total number of cycles that the CPU was in SMT-mode");
642 .name(name() + ".committedInsts")
643 .desc("Number of Instructions Simulated (Per-Thread)");
647 .name(name() + ".smtCommittedInsts")
648 .desc("Number of SMT Instructions Simulated (Per-Thread)");
651 .name(name() + ".committedInsts_total")
652 .desc("Number of Instructions Simulated (Total)");
655 .name(name() + ".cpi")
656 .desc("CPI: Cycles Per Instruction (Per-Thread)")
658 cpi
= numCycles
/ committedInsts
;
661 .name(name() + ".smt_cpi")
662 .desc("CPI: Total SMT-CPI")
664 smtCpi
= smtCycles
/ smtCommittedInsts
;
667 .name(name() + ".cpi_total")
668 .desc("CPI: Total CPI of All Threads")
670 totalCpi
= numCycles
/ totalCommittedInsts
;
673 .name(name() + ".ipc")
674 .desc("IPC: Instructions Per Cycle (Per-Thread)")
676 ipc
= committedInsts
/ numCycles
;
679 .name(name() + ".smt_ipc")
680 .desc("IPC: Total SMT-IPC")
682 smtIpc
= smtCommittedInsts
/ smtCycles
;
685 .name(name() + ".ipc_total")
686 .desc("IPC: Total IPC of All Threads")
688 totalIpc
= totalCommittedInsts
/ numCycles
;
697 DPRINTF(InOrderCPU
, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
701 bool pipes_idle
= true;
703 //Tick each of the stages
704 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
705 pipelineStage
[stNum
]->tick();
707 pipes_idle
= pipes_idle
&& pipelineStage
[stNum
]->idle
;
710 checkForInterrupts();
717 // Now advance the time buffers one tick
718 timeBuffer
.advance();
719 for (int sqNum
=0; sqNum
< NumStages
- 1; sqNum
++) {
720 stageQueue
[sqNum
]->advance();
722 activityRec
.advance();
724 // Any squashed events, or insts then remove them now
725 cleanUpRemovedEvents();
726 cleanUpRemovedInsts();
728 // Re-schedule CPU for this cycle
729 if (!tickEvent
.scheduled()) {
730 if (_status
== SwitchedOut
) {
732 lastRunningCycle
= curTick();
733 } else if (!activityRec
.active()) {
734 DPRINTF(InOrderCPU
, "sleeping CPU.\n");
735 lastRunningCycle
= curTick();
738 //Tick next_tick = curTick() + cycles(1);
739 //tickEvent.schedule(next_tick);
740 schedule(&tickEvent
, nextCycle(curTick() + 1));
741 DPRINTF(InOrderCPU
, "Scheduled CPU for next tick @ %i.\n",
742 nextCycle(curTick() + 1));
747 updateThreadPriority();
754 if (!deferRegistration
) {
755 registerThreadContexts();
758 // Set inSyscall so that the CPU doesn't squash when initially
759 // setting up registers.
760 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
761 thread
[tid
]->inSyscall
= true;
764 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
765 ThreadContext
*src_tc
= threadContexts
[tid
];
766 TheISA::initCPU(src_tc
, src_tc
->contextId());
771 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
772 thread
[tid
]->inSyscall
= false;
774 // Call Initializiation Routine for Resource Pool
779 InOrderCPU::getPort(const std::string
&if_name
, int idx
)
781 return resPool
->getPort(if_name
, idx
);
786 InOrderCPU::hwrei(ThreadID tid
)
788 #if THE_ISA == ALPHA_ISA
789 // Need to clear the lock flag upon returning from an interrupt.
790 setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG
, false, tid
);
792 thread
[tid
]->kernelStats
->hwrei();
793 // FIXME: XXX check for interrupts? XXX
801 InOrderCPU::simPalCheck(int palFunc
, ThreadID tid
)
803 #if THE_ISA == ALPHA_ISA
804 if (this->thread
[tid
]->kernelStats
)
805 this->thread
[tid
]->kernelStats
->callpal(palFunc
,
806 this->threadContexts
[tid
]);
811 if (--System::numSystemsRunning
== 0)
812 exitSimLoop("all cpus halted");
817 if (this->system
->breakpoint())
826 InOrderCPU::checkForInterrupts()
828 for (int i
= 0; i
< threadContexts
.size(); i
++) {
829 ThreadContext
*tc
= threadContexts
[i
];
831 if (interrupts
->checkInterrupts(tc
)) {
832 Fault interrupt
= interrupts
->getInterrupt(tc
);
834 if (interrupt
!= NoFault
) {
835 DPRINTF(Interrupt
, "Processing Intterupt for [tid:%i].\n",
838 ThreadID tid
= tc
->threadId();
839 interrupts
->updateIntrInfo(tc
);
841 // Squash from Last Stage in Pipeline
842 unsigned last_stage
= NumStages
- 1;
843 dummyTrapInst
[tid
]->squashingStage
= last_stage
;
844 pipelineStage
[last_stage
]->setupSquash(dummyTrapInst
[tid
],
847 // By default, setupSquash will always squash from stage + 1
848 pipelineStage
[BackEndStartStage
- 1]->setupSquash(dummyTrapInst
[tid
],
851 // Schedule Squash Through-out Resource Pool
852 resPool
->scheduleEvent(
853 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
,
854 dummyTrapInst
[tid
], 0);
856 // Finally, Setup Trap to happen at end of cycle
857 trapContext(interrupt
, tid
, dummyTrapInst
[tid
]);
864 InOrderCPU::getInterrupts()
866 // Check if there are any outstanding interrupts
867 return interrupts
->getInterrupt(threadContexts
[0]);
872 InOrderCPU::processInterrupts(Fault interrupt
)
874 // Check for interrupts here. For now can copy the code that
875 // exists within isa_fullsys_traits.hh. Also assume that thread 0
876 // is the one that handles the interrupts.
877 // @todo: Possibly consolidate the interrupt checking code.
878 // @todo: Allow other threads to handle interrupts.
880 assert(interrupt
!= NoFault
);
881 interrupts
->updateIntrInfo(threadContexts
[0]);
883 DPRINTF(InOrderCPU
, "Interrupt %s being handled\n", interrupt
->name());
885 // Note: Context ID ok here? Impl. of FS mode needs to revisit this
886 trap(interrupt
, threadContexts
[0]->contextId(), dummyBufferInst
);
891 InOrderCPU::updateMemPorts()
893 // Update all ThreadContext's memory ports (Functional/Virtual
895 ThreadID size
= thread
.size();
896 for (ThreadID i
= 0; i
< size
; ++i
)
897 thread
[i
]->connectMemPorts(thread
[i
]->getTC());
902 InOrderCPU::trapContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
904 scheduleCpuEvent(Trap
, fault
, tid
, inst
, delay
);
908 InOrderCPU::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
910 fault
->invoke(tcBase(tid
), inst
->staticInst
);
911 removePipelineStalls(tid
);
915 InOrderCPU::squashFromMemStall(DynInstPtr inst
, ThreadID tid
, int delay
)
917 scheduleCpuEvent(SquashFromMemStall
, NoFault
, tid
, inst
, delay
);
922 InOrderCPU::squashDueToMemStall(int stage_num
, InstSeqNum seq_num
,
925 DPRINTF(InOrderCPU
, "Squashing Pipeline Stages Due to Memory Stall...\n");
927 // Squash all instructions in each stage including
928 // instruction that caused the squash (seq_num - 1)
929 // NOTE: The stage bandwidth needs to be cleared so thats why
930 // the stalling instruction is squashed as well. The stalled
931 // instruction is previously placed in another intermediate buffer
932 // while it's stall is being handled.
933 InstSeqNum squash_seq_num
= seq_num
- 1;
935 for (int stNum
=stage_num
; stNum
>= 0 ; stNum
--) {
936 pipelineStage
[stNum
]->squashDueToMemStall(squash_seq_num
, tid
);
941 InOrderCPU::scheduleCpuEvent(CPUEventType c_event
, Fault fault
,
942 ThreadID tid
, DynInstPtr inst
,
943 unsigned delay
, CPUEventPri event_pri
)
945 CPUEvent
*cpu_event
= new CPUEvent(this, c_event
, fault
, tid
, inst
,
948 Tick sked_tick
= nextCycle(curTick() + ticks(delay
));
950 DPRINTF(InOrderCPU
, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
951 eventNames
[c_event
], curTick() + delay
, tid
);
952 schedule(cpu_event
, sked_tick
);
954 cpu_event
->process();
955 cpuEventRemoveList
.push(cpu_event
);
958 // Broadcast event to the Resource Pool
959 // Need to reset tid just in case this is a dummy instruction
961 resPool
->scheduleEvent(c_event
, inst
, 0, 0, tid
);
965 InOrderCPU::isThreadActive(ThreadID tid
)
967 list
<ThreadID
>::iterator isActive
=
968 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
970 return (isActive
!= activeThreads
.end());
974 InOrderCPU::isThreadReady(ThreadID tid
)
976 list
<ThreadID
>::iterator isReady
=
977 std::find(readyThreads
.begin(), readyThreads
.end(), tid
);
979 return (isReady
!= readyThreads
.end());
983 InOrderCPU::isThreadSuspended(ThreadID tid
)
985 list
<ThreadID
>::iterator isSuspended
=
986 std::find(suspendedThreads
.begin(), suspendedThreads
.end(), tid
);
988 return (isSuspended
!= suspendedThreads
.end());
992 InOrderCPU::activateNextReadyThread()
994 if (readyThreads
.size() >= 1) {
995 ThreadID ready_tid
= readyThreads
.front();
997 // Activate in Pipeline
998 activateThread(ready_tid
);
1000 // Activate in Resource Pool
1001 resPool
->activateThread(ready_tid
);
1003 list
<ThreadID
>::iterator ready_it
=
1004 std::find(readyThreads
.begin(), readyThreads
.end(), ready_tid
);
1005 readyThreads
.erase(ready_it
);
1008 "Attempting to activate new thread, but No Ready Threads to"
1011 "Unable to switch to next active thread.\n");
1016 InOrderCPU::activateThread(ThreadID tid
)
1018 if (isThreadSuspended(tid
)) {
1020 "Removing [tid:%i] from suspended threads list.\n", tid
);
1022 list
<ThreadID
>::iterator susp_it
=
1023 std::find(suspendedThreads
.begin(), suspendedThreads
.end(),
1025 suspendedThreads
.erase(susp_it
);
1028 if (threadModel
== SwitchOnCacheMiss
&&
1029 numActiveThreads() == 1) {
1031 "Ignoring activation of [tid:%i], since [tid:%i] is "
1032 "already running.\n", tid
, activeThreadId());
1034 DPRINTF(InOrderCPU
,"Placing [tid:%i] on ready threads list\n",
1037 readyThreads
.push_back(tid
);
1039 } else if (!isThreadActive(tid
)) {
1041 "Adding [tid:%i] to active threads list.\n", tid
);
1042 activeThreads
.push_back(tid
);
1044 activateThreadInPipeline(tid
);
1046 thread
[tid
]->lastActivate
= curTick();
1048 tcBase(tid
)->setStatus(ThreadContext::Active
);
1057 InOrderCPU::activateThreadInPipeline(ThreadID tid
)
1059 for (int stNum
=0; stNum
< NumStages
; stNum
++) {
1060 pipelineStage
[stNum
]->activateThread(tid
);
1065 InOrderCPU::deactivateContext(ThreadID tid
, int delay
)
1067 DPRINTF(InOrderCPU
,"[tid:%i]: Deactivating ...\n", tid
);
1069 scheduleCpuEvent(DeactivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1071 // Be sure to signal that there's some activity so the CPU doesn't
1072 // deschedule itself.
1073 activityRec
.activity();
1079 InOrderCPU::deactivateThread(ThreadID tid
)
1081 DPRINTF(InOrderCPU
, "[tid:%i]: Calling deactivate thread.\n", tid
);
1083 if (isThreadActive(tid
)) {
1084 DPRINTF(InOrderCPU
,"[tid:%i]: Removing from active threads list\n",
1086 list
<ThreadID
>::iterator thread_it
=
1087 std::find(activeThreads
.begin(), activeThreads
.end(), tid
);
1089 removePipelineStalls(*thread_it
);
1091 activeThreads
.erase(thread_it
);
1093 // Ideally, this should be triggered from the
1094 // suspendContext/Thread functions
1095 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1098 assert(!isThreadActive(tid
));
1102 InOrderCPU::removePipelineStalls(ThreadID tid
)
1104 DPRINTF(InOrderCPU
,"[tid:%i]: Removing all pipeline stalls\n",
1107 for (int stNum
= 0; stNum
< NumStages
; stNum
++) {
1108 pipelineStage
[stNum
]->removeStalls(tid
);
1114 InOrderCPU::updateThreadPriority()
1116 if (activeThreads
.size() > 1)
1118 //DEFAULT TO ROUND ROBIN SCHEME
1119 //e.g. Move highest priority to end of thread list
1120 list
<ThreadID
>::iterator list_begin
= activeThreads
.begin();
1121 list
<ThreadID
>::iterator list_end
= activeThreads
.end();
1123 unsigned high_thread
= *list_begin
;
1125 activeThreads
.erase(list_begin
);
1127 activeThreads
.push_back(high_thread
);
1132 InOrderCPU::tickThreadStats()
1134 /** Keep track of cycles that each thread is active */
1135 list
<ThreadID
>::iterator thread_it
= activeThreads
.begin();
1136 while (thread_it
!= activeThreads
.end()) {
1137 threadCycles
[*thread_it
]++;
1141 // Keep track of cycles where SMT is active
1142 if (activeThreads
.size() > 1) {
1148 InOrderCPU::activateContext(ThreadID tid
, int delay
)
1150 DPRINTF(InOrderCPU
,"[tid:%i]: Activating ...\n", tid
);
1153 scheduleCpuEvent(ActivateThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1155 // Be sure to signal that there's some activity so the CPU doesn't
1156 // deschedule itself.
1157 activityRec
.activity();
1163 InOrderCPU::activateNextReadyContext(int delay
)
1165 DPRINTF(InOrderCPU
,"Activating next ready thread\n");
1167 scheduleCpuEvent(ActivateNextReadyThread
, NoFault
, 0/*tid*/, dummyInst
[0],
1168 delay
, ActivateNextReadyThread_Pri
);
1170 // Be sure to signal that there's some activity so the CPU doesn't
1171 // deschedule itself.
1172 activityRec
.activity();
1178 InOrderCPU::haltContext(ThreadID tid
, int delay
)
1180 DPRINTF(InOrderCPU
, "[tid:%i]: Calling Halt Context...\n", tid
);
1182 scheduleCpuEvent(HaltThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1184 activityRec
.activity();
1188 InOrderCPU::haltThread(ThreadID tid
)
1190 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Halted Threads List...\n", tid
);
1191 deactivateThread(tid
);
1192 squashThreadInPipeline(tid
);
1193 haltedThreads
.push_back(tid
);
1195 tcBase(tid
)->setStatus(ThreadContext::Halted
);
1197 if (threadModel
== SwitchOnCacheMiss
) {
1198 activateNextReadyContext();
1203 InOrderCPU::suspendContext(ThreadID tid
, int delay
)
1205 scheduleCpuEvent(SuspendThread
, NoFault
, tid
, dummyInst
[tid
], delay
);
1209 InOrderCPU::suspendThread(ThreadID tid
)
1211 DPRINTF(InOrderCPU
, "[tid:%i]: Placing on Suspended Threads List...\n",
1213 deactivateThread(tid
);
1214 suspendedThreads
.push_back(tid
);
1215 thread
[tid
]->lastSuspend
= curTick();
1217 tcBase(tid
)->setStatus(ThreadContext::Suspended
);
1221 InOrderCPU::squashThreadInPipeline(ThreadID tid
)
1223 //Squash all instructions in each stage
1224 for (int stNum
=NumStages
- 1; stNum
>= 0 ; stNum
--) {
1225 pipelineStage
[stNum
]->squash(0 /*seq_num*/, tid
);
1230 InOrderCPU::getPipeStage(int stage_num
)
1232 return pipelineStage
[stage_num
];
1237 InOrderCPU::flattenRegIdx(RegIndex reg_idx
, RegType
®_type
, ThreadID tid
)
1239 if (reg_idx
< FP_Base_DepTag
) {
1241 return isa
[tid
].flattenIntIndex(reg_idx
);
1242 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1243 reg_type
= FloatType
;
1244 reg_idx
-= FP_Base_DepTag
;
1245 return isa
[tid
].flattenFloatIndex(reg_idx
);
1247 reg_type
= MiscType
;
1248 return reg_idx
- TheISA::Ctrl_Base_DepTag
;
1253 InOrderCPU::readIntReg(RegIndex reg_idx
, ThreadID tid
)
1255 DPRINTF(IntRegs
, "[tid:%i]: Reading Int. Reg %i as %x\n",
1256 tid
, reg_idx
, intRegs
[tid
][reg_idx
]);
1258 return intRegs
[tid
][reg_idx
];
1262 InOrderCPU::readFloatReg(RegIndex reg_idx
, ThreadID tid
)
1264 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1265 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1267 return floatRegs
.f
[tid
][reg_idx
];
1271 InOrderCPU::readFloatRegBits(RegIndex reg_idx
, ThreadID tid
)
1273 DPRINTF(FloatRegs
, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
1274 tid
, reg_idx
, floatRegs
.i
[tid
][reg_idx
], floatRegs
.f
[tid
][reg_idx
]);
1276 return floatRegs
.i
[tid
][reg_idx
];
1280 InOrderCPU::setIntReg(RegIndex reg_idx
, uint64_t val
, ThreadID tid
)
1282 if (reg_idx
== TheISA::ZeroReg
) {
1283 DPRINTF(IntRegs
, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
1284 "(Int. Reg %i) to %x\n", tid
, reg_idx
, val
);
1287 DPRINTF(IntRegs
, "[tid:%i]: Setting Int. Reg %i to %x\n",
1290 intRegs
[tid
][reg_idx
] = val
;
1296 InOrderCPU::setFloatReg(RegIndex reg_idx
, FloatReg val
, ThreadID tid
)
1298 floatRegs
.f
[tid
][reg_idx
] = val
;
1299 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1302 floatRegs
.i
[tid
][reg_idx
],
1303 floatRegs
.f
[tid
][reg_idx
]);
1308 InOrderCPU::setFloatRegBits(RegIndex reg_idx
, FloatRegBits val
, ThreadID tid
)
1310 floatRegs
.i
[tid
][reg_idx
] = val
;
1311 DPRINTF(FloatRegs
, "[tid:%i]: Setting Float. Reg %i bits to "
1314 floatRegs
.i
[tid
][reg_idx
],
1315 floatRegs
.f
[tid
][reg_idx
]);
1319 InOrderCPU::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
1321 // If Default value is set, then retrieve target thread
1322 if (tid
== InvalidThreadID
) {
1323 tid
= TheISA::getTargetThread(tcBase(tid
));
1326 if (reg_idx
< FP_Base_DepTag
) {
1327 // Integer Register File
1328 return readIntReg(reg_idx
, tid
);
1329 } else if (reg_idx
< Ctrl_Base_DepTag
) {
1330 // Float Register File
1331 reg_idx
-= FP_Base_DepTag
;
1332 return readFloatRegBits(reg_idx
, tid
);
1334 reg_idx
-= Ctrl_Base_DepTag
;
1335 return readMiscReg(reg_idx
, tid
); // Misc. Register File
1339 InOrderCPU::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
1342 // If Default value is set, then retrieve target thread
1343 if (tid
== InvalidThreadID
) {
1344 tid
= TheISA::getTargetThread(tcBase(tid
));
1347 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
1348 setIntReg(reg_idx
, val
, tid
);
1349 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
1350 reg_idx
-= FP_Base_DepTag
;
1351 setFloatRegBits(reg_idx
, val
, tid
);
1353 reg_idx
-= Ctrl_Base_DepTag
;
1354 setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
1359 InOrderCPU::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
1361 return isa
[tid
].readMiscRegNoEffect(misc_reg
);
1365 InOrderCPU::readMiscReg(int misc_reg
, ThreadID tid
)
1367 DPRINTF(InOrderCPU
, "MiscReg: %i\n", misc_reg
);
1368 DPRINTF(InOrderCPU
, "tid: %i\n", tid
);
1369 DPRINTF(InOrderCPU
, "tcBase: %x\n", tcBase(tid
));
1370 DPRINTF(InOrderCPU
, "isa-tid: %x\n", &isa
[tid
]);
1372 return isa
[tid
].readMiscReg(misc_reg
, tcBase(tid
));
1376 InOrderCPU::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1378 isa
[tid
].setMiscRegNoEffect(misc_reg
, val
);
1382 InOrderCPU::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
1384 isa
[tid
].setMiscReg(misc_reg
, val
, tcBase(tid
));
1389 InOrderCPU::addInst(DynInstPtr inst
)
1391 ThreadID tid
= inst
->readTid();
1393 instList
[tid
].push_back(inst
);
1395 return --(instList
[tid
].end());
1399 InOrderCPU::findInst(InstSeqNum seq_num
, ThreadID tid
)
1401 ListIt it
= instList
[tid
].begin();
1402 ListIt end
= instList
[tid
].end();
1405 if ((*it
)->seqNum
== seq_num
)
1407 else if ((*it
)->seqNum
> seq_num
)
1413 return instList
[tid
].end();
1417 InOrderCPU::updateContextSwitchStats()
1419 // Set Average Stat Here, then reset to 0
1420 instsPerCtxtSwitch
= instsPerSwitch
;
1426 InOrderCPU::instDone(DynInstPtr inst
, ThreadID tid
)
1428 // Set the nextPC to be fetched if this is the last instruction
1431 // This contributes to the precise state of the CPU
1432 // which can be used when restoring a thread to the CPU after after any
1433 // type of context switching activity (fork, exception, etc.)
1434 TheISA::PCState comm_pc
= inst
->pcState();
1435 lastCommittedPC
[tid
] = comm_pc
;
1436 TheISA::advancePC(comm_pc
, inst
->staticInst
);
1437 pcState(comm_pc
, tid
);
1439 //@todo: may be unnecessary with new-ISA-specific branch handling code
1440 if (inst
->isControl()) {
1441 thread
[tid
]->lastGradIsBranch
= true;
1442 thread
[tid
]->lastBranchPC
= inst
->pcState();
1443 TheISA::advancePC(thread
[tid
]->lastBranchPC
, inst
->staticInst
);
1445 thread
[tid
]->lastGradIsBranch
= false;
1449 // Finalize Trace Data For Instruction
1450 if (inst
->traceData
) {
1451 //inst->traceData->setCycle(curTick());
1452 inst
->traceData
->setFetchSeq(inst
->seqNum
);
1453 //inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
1454 inst
->traceData
->dump();
1455 delete inst
->traceData
;
1456 inst
->traceData
= NULL
;
1459 // Increment active thread's instruction count
1462 // Increment thread-state's instruction count
1463 thread
[tid
]->numInst
++;
1465 // Increment thread-state's instruction stats
1466 thread
[tid
]->numInsts
++;
1468 // Count committed insts per thread stats
1469 committedInsts
[tid
]++;
1471 // Count total insts committed stat
1472 totalCommittedInsts
++;
1474 // Count SMT-committed insts per thread stat
1475 if (numActiveThreads() > 1) {
1476 smtCommittedInsts
[tid
]++;
1479 // Instruction-Mix Stats
1480 if (inst
->isLoad()) {
1482 } else if (inst
->isStore()) {
1484 } else if (inst
->isControl()) {
1486 } else if (inst
->isNop()) {
1488 } else if (inst
->isNonSpeculative()) {
1490 } else if (inst
->isInteger()) {
1492 } else if (inst
->isFloating()) {
1496 // Check for instruction-count-based events.
1497 comInstEventQueue
[tid
]->serviceEvents(thread
[tid
]->numInst
);
1499 // Finally, remove instruction from CPU
1503 // currently unused function, but substitute repetitive code w/this function
1506 InOrderCPU::addToRemoveList(DynInstPtr inst
)
1508 removeInstsThisCycle
= true;
1509 if (!inst
->isRemoveList()) {
1510 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1511 "[sn:%lli] to remove list\n",
1512 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1513 inst
->setRemoveList();
1514 removeList
.push(inst
->getInstListIt());
1516 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1517 "[sn:%lli], already remove list\n",
1518 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1524 InOrderCPU::removeInst(DynInstPtr inst
)
1526 DPRINTF(InOrderCPU
, "Removing graduated instruction [tid:%i] PC %s "
1528 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1530 removeInstsThisCycle
= true;
1532 // Remove the instruction.
1533 if (!inst
->isRemoveList()) {
1534 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1535 "[sn:%lli] to remove list\n",
1536 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1537 inst
->setRemoveList();
1538 removeList
.push(inst
->getInstListIt());
1540 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i] PC %s "
1541 "[sn:%lli], already on remove list\n",
1542 inst
->threadNumber
, inst
->pcState(), inst
->seqNum
);
1548 InOrderCPU::removeInstsUntil(const InstSeqNum
&seq_num
, ThreadID tid
)
1550 //assert(!instList[tid].empty());
1552 removeInstsThisCycle
= true;
1554 ListIt inst_iter
= instList
[tid
].end();
1558 DPRINTF(InOrderCPU
, "Squashing instructions from CPU instruction "
1559 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1560 tid
, seq_num
, (*inst_iter
)->seqNum
);
1562 while ((*inst_iter
)->seqNum
> seq_num
) {
1564 bool break_loop
= (inst_iter
== instList
[tid
].begin());
1566 squashInstIt(inst_iter
, tid
);
1577 InOrderCPU::squashInstIt(const ListIt inst_it
, ThreadID tid
)
1579 DynInstPtr inst
= (*inst_it
);
1580 if (inst
->threadNumber
== tid
) {
1581 DPRINTF(InOrderCPU
, "Squashing instruction, "
1582 "[tid:%i] [sn:%lli] PC %s\n",
1587 inst
->setSquashed();
1588 archRegDepMap
[tid
].remove(inst
);
1590 if (!inst
->isRemoveList()) {
1591 DPRINTF(InOrderCPU
, "Pushing instruction [tid:%i] PC %s "
1592 "[sn:%lli] to remove list\n",
1593 inst
->threadNumber
, inst
->pcState(),
1595 inst
->setRemoveList();
1596 removeList
.push(inst_it
);
1598 DPRINTF(InOrderCPU
, "Ignoring instruction removal for [tid:%i]"
1599 " PC %s [sn:%lli], already on remove list\n",
1600 inst
->threadNumber
, inst
->pcState(),
1610 InOrderCPU::cleanUpRemovedInsts()
1612 while (!removeList
.empty()) {
1613 DPRINTF(InOrderCPU
, "Removing instruction, "
1614 "[tid:%i] [sn:%lli] PC %s\n",
1615 (*removeList
.front())->threadNumber
,
1616 (*removeList
.front())->seqNum
,
1617 (*removeList
.front())->pcState());
1619 DynInstPtr inst
= *removeList
.front();
1620 ThreadID tid
= inst
->threadNumber
;
1622 // Remove From Register Dependency Map, If Necessary
1623 // archRegDepMap[tid].remove(inst);
1625 // Clear if Non-Speculative
1626 if (inst
->staticInst
&&
1627 inst
->seqNum
== nonSpecSeqNum
[tid
] &&
1628 nonSpecInstActive
[tid
] == true) {
1629 nonSpecInstActive
[tid
] = false;
1632 inst
->onInstList
= false;
1634 instList
[tid
].erase(removeList
.front());
1639 removeInstsThisCycle
= false;
1643 InOrderCPU::cleanUpRemovedEvents()
1645 while (!cpuEventRemoveList
.empty()) {
1646 Event
*cpu_event
= cpuEventRemoveList
.front();
1647 cpuEventRemoveList
.pop();
1654 InOrderCPU::dumpInsts()
1658 ListIt inst_list_it
= instList
[0].begin();
1660 cprintf("Dumping Instruction List\n");
1662 while (inst_list_it
!= instList
[0].end()) {
1663 cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1665 num
, (*inst_list_it
)->pcState(),
1666 (*inst_list_it
)->threadNumber
,
1667 (*inst_list_it
)->seqNum
, (*inst_list_it
)->isIssued(),
1668 (*inst_list_it
)->isSquashed());
1675 InOrderCPU::wakeCPU()
1677 if (/*activityRec.active() || */tickEvent
.scheduled()) {
1678 DPRINTF(Activity
, "CPU already running.\n");
1682 DPRINTF(Activity
, "Waking up CPU\n");
1684 Tick extra_cycles
= tickToCycles((curTick() - 1) - lastRunningCycle
);
1686 idleCycles
+= extra_cycles
;
1687 for (int stage_num
= 0; stage_num
< NumStages
; stage_num
++) {
1688 pipelineStage
[stage_num
]->idleCycles
+= extra_cycles
;
1691 numCycles
+= extra_cycles
;
1693 schedule(&tickEvent
, nextCycle(curTick()));
1697 // Lots of copied full system code...place into BaseCPU class?
1699 InOrderCPU::wakeup()
1701 if (thread
[0]->status() != ThreadContext::Suspended
)
1706 DPRINTF(Quiesce
, "Suspended Processor woken\n");
1707 threadContexts
[0]->activate();
1713 InOrderCPU::syscallContext(Fault fault
, ThreadID tid
, DynInstPtr inst
, int delay
)
1715 //@todo: squash behind syscall
1716 scheduleCpuEvent(Syscall
, fault
, tid
, inst
, delay
, Syscall_Pri
);
1720 InOrderCPU::syscall(int64_t callnum
, ThreadID tid
)
1722 DPRINTF(InOrderCPU
, "[tid:%i] Executing syscall().\n\n", tid
);
1724 DPRINTF(Activity
,"Activity: syscall() called.\n");
1726 // Temporarily increase this by one to account for the syscall
1728 ++(this->thread
[tid
]->funcExeInst
);
1730 // Execute the actual syscall.
1731 this->thread
[tid
]->syscall(callnum
);
1733 // Decrease funcExeInst by one as the normal commit will handle
1735 --(this->thread
[tid
]->funcExeInst
);
1737 // Clear Non-Speculative Block Variable
1738 nonSpecInstActive
[tid
] = false;
1743 InOrderCPU::getITBPtr()
1745 CacheUnit
*itb_res
=
1746 dynamic_cast<CacheUnit
*>(resPool
->getResource(fetchPortIdx
));
1747 return itb_res
->tlb();
1752 InOrderCPU::getDTBPtr()
1754 CacheUnit
*dtb_res
=
1755 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1756 return dtb_res
->tlb();
1760 InOrderCPU::read(DynInstPtr inst
, Addr addr
,
1761 uint8_t *data
, unsigned size
, unsigned flags
)
1763 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1764 // you want to run w/out caches?
1765 CacheUnit
*cache_res
=
1766 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1768 return cache_res
->read(inst
, addr
, data
, size
, flags
);
1772 InOrderCPU::write(DynInstPtr inst
, uint8_t *data
, unsigned size
,
1773 Addr addr
, unsigned flags
, uint64_t *write_res
)
1775 //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
1776 // you want to run w/out caches?
1777 CacheUnit
*cache_res
=
1778 dynamic_cast<CacheUnit
*>(resPool
->getResource(dataPortIdx
));
1779 return cache_res
->write(inst
, data
, size
, addr
, flags
, write_res
);